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581 lines
14 KiB
581 lines
14 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* Rockchip usb PHY driver |
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* |
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* Copyright (C) 2014 Yunzhi Li <[email protected]> |
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* Copyright (C) 2014 ROCKCHIP, Inc. |
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*/ |
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|
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#include <linux/clk.h> |
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#include <linux/clk-provider.h> |
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#include <linux/io.h> |
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#include <linux/kernel.h> |
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#include <linux/module.h> |
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#include <linux/mutex.h> |
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#include <linux/of.h> |
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#include <linux/of_address.h> |
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#include <linux/of_platform.h> |
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#include <linux/phy/phy.h> |
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#include <linux/platform_device.h> |
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#include <linux/regulator/consumer.h> |
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#include <linux/reset.h> |
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#include <linux/regmap.h> |
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#include <linux/mfd/syscon.h> |
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#include <linux/delay.h> |
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|
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static int enable_usb_uart; |
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|
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#define HIWORD_UPDATE(val, mask) \ |
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((val) | (mask) << 16) |
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|
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#define UOC_CON0 0x00 |
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#define UOC_CON0_SIDDQ BIT(13) |
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#define UOC_CON0_DISABLE BIT(4) |
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#define UOC_CON0_COMMON_ON_N BIT(0) |
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|
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#define UOC_CON2 0x08 |
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#define UOC_CON2_SOFT_CON_SEL BIT(2) |
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|
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#define UOC_CON3 0x0c |
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/* bits present on rk3188 and rk3288 phys */ |
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#define UOC_CON3_UTMI_TERMSEL_FULLSPEED BIT(5) |
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#define UOC_CON3_UTMI_XCVRSEELCT_FSTRANSC (1 << 3) |
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#define UOC_CON3_UTMI_XCVRSEELCT_MASK (3 << 3) |
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#define UOC_CON3_UTMI_OPMODE_NODRIVING (1 << 1) |
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#define UOC_CON3_UTMI_OPMODE_MASK (3 << 1) |
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#define UOC_CON3_UTMI_SUSPENDN BIT(0) |
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|
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struct rockchip_usb_phys { |
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int reg; |
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const char *pll_name; |
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}; |
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|
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struct rockchip_usb_phy_base; |
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struct rockchip_usb_phy_pdata { |
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struct rockchip_usb_phys *phys; |
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int (*init_usb_uart)(struct regmap *grf, |
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const struct rockchip_usb_phy_pdata *pdata); |
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int usb_uart_phy; |
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}; |
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|
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struct rockchip_usb_phy_base { |
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struct device *dev; |
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struct regmap *reg_base; |
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const struct rockchip_usb_phy_pdata *pdata; |
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}; |
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|
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struct rockchip_usb_phy { |
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struct rockchip_usb_phy_base *base; |
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struct device_node *np; |
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unsigned int reg_offset; |
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struct clk *clk; |
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struct clk *clk480m; |
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struct clk_hw clk480m_hw; |
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struct phy *phy; |
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bool uart_enabled; |
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struct reset_control *reset; |
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struct regulator *vbus; |
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}; |
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|
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static int rockchip_usb_phy_power(struct rockchip_usb_phy *phy, |
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bool siddq) |
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{ |
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u32 val = HIWORD_UPDATE(siddq ? UOC_CON0_SIDDQ : 0, UOC_CON0_SIDDQ); |
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|
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return regmap_write(phy->base->reg_base, phy->reg_offset, val); |
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} |
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|
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static unsigned long rockchip_usb_phy480m_recalc_rate(struct clk_hw *hw, |
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unsigned long parent_rate) |
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{ |
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return 480000000; |
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} |
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|
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static void rockchip_usb_phy480m_disable(struct clk_hw *hw) |
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{ |
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struct rockchip_usb_phy *phy = container_of(hw, |
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struct rockchip_usb_phy, |
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clk480m_hw); |
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|
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if (phy->vbus) |
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regulator_disable(phy->vbus); |
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|
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/* Power down usb phy analog blocks by set siddq 1 */ |
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rockchip_usb_phy_power(phy, 1); |
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} |
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|
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static int rockchip_usb_phy480m_enable(struct clk_hw *hw) |
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{ |
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struct rockchip_usb_phy *phy = container_of(hw, |
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struct rockchip_usb_phy, |
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clk480m_hw); |
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|
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/* Power up usb phy analog blocks by set siddq 0 */ |
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return rockchip_usb_phy_power(phy, 0); |
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} |
|
|
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static int rockchip_usb_phy480m_is_enabled(struct clk_hw *hw) |
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{ |
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struct rockchip_usb_phy *phy = container_of(hw, |
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struct rockchip_usb_phy, |
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clk480m_hw); |
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int ret; |
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u32 val; |
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|
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ret = regmap_read(phy->base->reg_base, phy->reg_offset, &val); |
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if (ret < 0) |
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return ret; |
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|
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return (val & UOC_CON0_SIDDQ) ? 0 : 1; |
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} |
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|
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static const struct clk_ops rockchip_usb_phy480m_ops = { |
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.enable = rockchip_usb_phy480m_enable, |
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.disable = rockchip_usb_phy480m_disable, |
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.is_enabled = rockchip_usb_phy480m_is_enabled, |
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.recalc_rate = rockchip_usb_phy480m_recalc_rate, |
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}; |
|
|
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static int rockchip_usb_phy_power_off(struct phy *_phy) |
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{ |
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struct rockchip_usb_phy *phy = phy_get_drvdata(_phy); |
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|
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if (phy->uart_enabled) |
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return -EBUSY; |
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|
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clk_disable_unprepare(phy->clk480m); |
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|
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return 0; |
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} |
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|
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static int rockchip_usb_phy_power_on(struct phy *_phy) |
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{ |
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struct rockchip_usb_phy *phy = phy_get_drvdata(_phy); |
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|
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if (phy->uart_enabled) |
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return -EBUSY; |
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|
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if (phy->vbus) { |
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int ret; |
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|
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ret = regulator_enable(phy->vbus); |
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if (ret) |
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return ret; |
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} |
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|
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return clk_prepare_enable(phy->clk480m); |
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} |
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|
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static int rockchip_usb_phy_reset(struct phy *_phy) |
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{ |
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struct rockchip_usb_phy *phy = phy_get_drvdata(_phy); |
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|
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if (phy->reset) { |
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reset_control_assert(phy->reset); |
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udelay(10); |
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reset_control_deassert(phy->reset); |
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} |
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|
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return 0; |
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} |
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|
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static const struct phy_ops ops = { |
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.power_on = rockchip_usb_phy_power_on, |
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.power_off = rockchip_usb_phy_power_off, |
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.reset = rockchip_usb_phy_reset, |
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.owner = THIS_MODULE, |
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}; |
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|
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static void rockchip_usb_phy_action(void *data) |
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{ |
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struct rockchip_usb_phy *rk_phy = data; |
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|
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if (!rk_phy->uart_enabled) { |
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of_clk_del_provider(rk_phy->np); |
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clk_unregister(rk_phy->clk480m); |
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} |
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|
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if (rk_phy->clk) |
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clk_put(rk_phy->clk); |
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} |
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|
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static int rockchip_usb_phy_init(struct rockchip_usb_phy_base *base, |
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struct device_node *child) |
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{ |
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struct rockchip_usb_phy *rk_phy; |
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unsigned int reg_offset; |
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const char *clk_name; |
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struct clk_init_data init; |
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int err, i; |
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|
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rk_phy = devm_kzalloc(base->dev, sizeof(*rk_phy), GFP_KERNEL); |
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if (!rk_phy) |
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return -ENOMEM; |
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|
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rk_phy->base = base; |
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rk_phy->np = child; |
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|
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if (of_property_read_u32(child, "reg", ®_offset)) { |
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dev_err(base->dev, "missing reg property in node %pOFn\n", |
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child); |
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return -EINVAL; |
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} |
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|
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rk_phy->reset = of_reset_control_get(child, "phy-reset"); |
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if (IS_ERR(rk_phy->reset)) |
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rk_phy->reset = NULL; |
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rk_phy->reg_offset = reg_offset; |
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rk_phy->clk = of_clk_get_by_name(child, "phyclk"); |
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if (IS_ERR(rk_phy->clk)) |
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rk_phy->clk = NULL; |
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i = 0; |
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init.name = NULL; |
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while (base->pdata->phys[i].reg) { |
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if (base->pdata->phys[i].reg == reg_offset) { |
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init.name = base->pdata->phys[i].pll_name; |
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break; |
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} |
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i++; |
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} |
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|
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if (!init.name) { |
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dev_err(base->dev, "phy data not found\n"); |
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return -EINVAL; |
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} |
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|
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if (enable_usb_uart && base->pdata->usb_uart_phy == i) { |
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dev_dbg(base->dev, "phy%d used as uart output\n", i); |
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rk_phy->uart_enabled = true; |
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} else { |
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if (rk_phy->clk) { |
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clk_name = __clk_get_name(rk_phy->clk); |
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init.flags = 0; |
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init.parent_names = &clk_name; |
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init.num_parents = 1; |
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} else { |
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init.flags = 0; |
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init.parent_names = NULL; |
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init.num_parents = 0; |
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} |
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init.ops = &rockchip_usb_phy480m_ops; |
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rk_phy->clk480m_hw.init = &init; |
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rk_phy->clk480m = clk_register(base->dev, &rk_phy->clk480m_hw); |
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if (IS_ERR(rk_phy->clk480m)) { |
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err = PTR_ERR(rk_phy->clk480m); |
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goto err_clk; |
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} |
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err = of_clk_add_provider(child, of_clk_src_simple_get, |
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rk_phy->clk480m); |
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if (err < 0) |
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goto err_clk_prov; |
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} |
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err = devm_add_action_or_reset(base->dev, rockchip_usb_phy_action, |
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rk_phy); |
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if (err) |
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return err; |
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|
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rk_phy->phy = devm_phy_create(base->dev, child, &ops); |
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if (IS_ERR(rk_phy->phy)) { |
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dev_err(base->dev, "failed to create PHY\n"); |
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return PTR_ERR(rk_phy->phy); |
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} |
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phy_set_drvdata(rk_phy->phy, rk_phy); |
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rk_phy->vbus = devm_regulator_get_optional(&rk_phy->phy->dev, "vbus"); |
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if (IS_ERR(rk_phy->vbus)) { |
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if (PTR_ERR(rk_phy->vbus) == -EPROBE_DEFER) |
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return PTR_ERR(rk_phy->vbus); |
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rk_phy->vbus = NULL; |
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} |
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|
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/* |
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* When acting as uart-pipe, just keep clock on otherwise |
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* only power up usb phy when it use, so disable it when init |
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*/ |
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if (rk_phy->uart_enabled) |
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return clk_prepare_enable(rk_phy->clk); |
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else |
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return rockchip_usb_phy_power(rk_phy, 1); |
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err_clk_prov: |
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if (!rk_phy->uart_enabled) |
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clk_unregister(rk_phy->clk480m); |
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err_clk: |
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if (rk_phy->clk) |
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clk_put(rk_phy->clk); |
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return err; |
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} |
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static const struct rockchip_usb_phy_pdata rk3066a_pdata = { |
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.phys = (struct rockchip_usb_phys[]){ |
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{ .reg = 0x17c, .pll_name = "sclk_otgphy0_480m" }, |
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{ .reg = 0x188, .pll_name = "sclk_otgphy1_480m" }, |
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{ /* sentinel */ } |
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}, |
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}; |
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static int __init rockchip_init_usb_uart_common(struct regmap *grf, |
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const struct rockchip_usb_phy_pdata *pdata) |
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{ |
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int regoffs = pdata->phys[pdata->usb_uart_phy].reg; |
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int ret; |
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u32 val; |
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|
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/* |
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* COMMON_ON and DISABLE settings are described in the TRM, |
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* but were not present in the original code. |
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* Also disable the analog phy components to save power. |
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*/ |
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val = HIWORD_UPDATE(UOC_CON0_COMMON_ON_N |
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| UOC_CON0_DISABLE |
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| UOC_CON0_SIDDQ, |
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UOC_CON0_COMMON_ON_N |
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| UOC_CON0_DISABLE |
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| UOC_CON0_SIDDQ); |
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ret = regmap_write(grf, regoffs + UOC_CON0, val); |
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if (ret) |
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return ret; |
|
|
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val = HIWORD_UPDATE(UOC_CON2_SOFT_CON_SEL, |
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UOC_CON2_SOFT_CON_SEL); |
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ret = regmap_write(grf, regoffs + UOC_CON2, val); |
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if (ret) |
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return ret; |
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|
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val = HIWORD_UPDATE(UOC_CON3_UTMI_OPMODE_NODRIVING |
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| UOC_CON3_UTMI_XCVRSEELCT_FSTRANSC |
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| UOC_CON3_UTMI_TERMSEL_FULLSPEED, |
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UOC_CON3_UTMI_SUSPENDN |
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| UOC_CON3_UTMI_OPMODE_MASK |
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| UOC_CON3_UTMI_XCVRSEELCT_MASK |
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| UOC_CON3_UTMI_TERMSEL_FULLSPEED); |
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ret = regmap_write(grf, UOC_CON3, val); |
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if (ret) |
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return ret; |
|
|
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return 0; |
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} |
|
|
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#define RK3188_UOC0_CON0 0x10c |
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#define RK3188_UOC0_CON0_BYPASSSEL BIT(9) |
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#define RK3188_UOC0_CON0_BYPASSDMEN BIT(8) |
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|
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/* |
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* Enable the bypass of uart2 data through the otg usb phy. |
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* See description of rk3288-variant for details. |
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*/ |
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static int __init rk3188_init_usb_uart(struct regmap *grf, |
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const struct rockchip_usb_phy_pdata *pdata) |
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{ |
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u32 val; |
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int ret; |
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|
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ret = rockchip_init_usb_uart_common(grf, pdata); |
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if (ret) |
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return ret; |
|
|
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val = HIWORD_UPDATE(RK3188_UOC0_CON0_BYPASSSEL |
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| RK3188_UOC0_CON0_BYPASSDMEN, |
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RK3188_UOC0_CON0_BYPASSSEL |
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| RK3188_UOC0_CON0_BYPASSDMEN); |
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ret = regmap_write(grf, RK3188_UOC0_CON0, val); |
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if (ret) |
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return ret; |
|
|
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return 0; |
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} |
|
|
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static const struct rockchip_usb_phy_pdata rk3188_pdata = { |
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.phys = (struct rockchip_usb_phys[]){ |
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{ .reg = 0x10c, .pll_name = "sclk_otgphy0_480m" }, |
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{ .reg = 0x11c, .pll_name = "sclk_otgphy1_480m" }, |
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{ /* sentinel */ } |
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}, |
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.init_usb_uart = rk3188_init_usb_uart, |
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.usb_uart_phy = 0, |
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}; |
|
|
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#define RK3288_UOC0_CON3 0x32c |
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#define RK3288_UOC0_CON3_BYPASSDMEN BIT(6) |
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#define RK3288_UOC0_CON3_BYPASSSEL BIT(7) |
|
|
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/* |
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* Enable the bypass of uart2 data through the otg usb phy. |
|
* Original description in the TRM. |
|
* 1. Disable the OTG block by setting OTGDISABLE0 to 1’b1. |
|
* 2. Disable the pull-up resistance on the D+ line by setting |
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* OPMODE0[1:0] to 2’b01. |
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* 3. To ensure that the XO, Bias, and PLL blocks are powered down in Suspend |
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* mode, set COMMONONN to 1’b1. |
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* 4. Place the USB PHY in Suspend mode by setting SUSPENDM0 to 1’b0. |
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* 5. Set BYPASSSEL0 to 1’b1. |
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* 6. To transmit data, controls BYPASSDMEN0, and BYPASSDMDATA0. |
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* To receive data, monitor FSVPLUS0. |
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* |
|
* The actual code in the vendor kernel does some things differently. |
|
*/ |
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static int __init rk3288_init_usb_uart(struct regmap *grf, |
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const struct rockchip_usb_phy_pdata *pdata) |
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{ |
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u32 val; |
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int ret; |
|
|
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ret = rockchip_init_usb_uart_common(grf, pdata); |
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if (ret) |
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return ret; |
|
|
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val = HIWORD_UPDATE(RK3288_UOC0_CON3_BYPASSSEL |
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| RK3288_UOC0_CON3_BYPASSDMEN, |
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RK3288_UOC0_CON3_BYPASSSEL |
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| RK3288_UOC0_CON3_BYPASSDMEN); |
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ret = regmap_write(grf, RK3288_UOC0_CON3, val); |
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if (ret) |
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return ret; |
|
|
|
return 0; |
|
} |
|
|
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static const struct rockchip_usb_phy_pdata rk3288_pdata = { |
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.phys = (struct rockchip_usb_phys[]){ |
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{ .reg = 0x320, .pll_name = "sclk_otgphy0_480m" }, |
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{ .reg = 0x334, .pll_name = "sclk_otgphy1_480m" }, |
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{ .reg = 0x348, .pll_name = "sclk_otgphy2_480m" }, |
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{ /* sentinel */ } |
|
}, |
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.init_usb_uart = rk3288_init_usb_uart, |
|
.usb_uart_phy = 0, |
|
}; |
|
|
|
static int rockchip_usb_phy_probe(struct platform_device *pdev) |
|
{ |
|
struct device *dev = &pdev->dev; |
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struct rockchip_usb_phy_base *phy_base; |
|
struct phy_provider *phy_provider; |
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const struct of_device_id *match; |
|
struct device_node *child; |
|
int err; |
|
|
|
phy_base = devm_kzalloc(dev, sizeof(*phy_base), GFP_KERNEL); |
|
if (!phy_base) |
|
return -ENOMEM; |
|
|
|
match = of_match_device(dev->driver->of_match_table, dev); |
|
if (!match || !match->data) { |
|
dev_err(dev, "missing phy data\n"); |
|
return -EINVAL; |
|
} |
|
|
|
phy_base->pdata = match->data; |
|
|
|
phy_base->dev = dev; |
|
phy_base->reg_base = ERR_PTR(-ENODEV); |
|
if (dev->parent && dev->parent->of_node) |
|
phy_base->reg_base = syscon_node_to_regmap( |
|
dev->parent->of_node); |
|
if (IS_ERR(phy_base->reg_base)) |
|
phy_base->reg_base = syscon_regmap_lookup_by_phandle( |
|
dev->of_node, "rockchip,grf"); |
|
if (IS_ERR(phy_base->reg_base)) { |
|
dev_err(&pdev->dev, "Missing rockchip,grf property\n"); |
|
return PTR_ERR(phy_base->reg_base); |
|
} |
|
|
|
for_each_available_child_of_node(dev->of_node, child) { |
|
err = rockchip_usb_phy_init(phy_base, child); |
|
if (err) { |
|
of_node_put(child); |
|
return err; |
|
} |
|
} |
|
|
|
phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); |
|
return PTR_ERR_OR_ZERO(phy_provider); |
|
} |
|
|
|
static const struct of_device_id rockchip_usb_phy_dt_ids[] = { |
|
{ .compatible = "rockchip,rk3066a-usb-phy", .data = &rk3066a_pdata }, |
|
{ .compatible = "rockchip,rk3188-usb-phy", .data = &rk3188_pdata }, |
|
{ .compatible = "rockchip,rk3288-usb-phy", .data = &rk3288_pdata }, |
|
{} |
|
}; |
|
|
|
MODULE_DEVICE_TABLE(of, rockchip_usb_phy_dt_ids); |
|
|
|
static struct platform_driver rockchip_usb_driver = { |
|
.probe = rockchip_usb_phy_probe, |
|
.driver = { |
|
.name = "rockchip-usb-phy", |
|
.of_match_table = rockchip_usb_phy_dt_ids, |
|
}, |
|
}; |
|
|
|
module_platform_driver(rockchip_usb_driver); |
|
|
|
#ifndef MODULE |
|
static int __init rockchip_init_usb_uart(void) |
|
{ |
|
const struct of_device_id *match; |
|
const struct rockchip_usb_phy_pdata *data; |
|
struct device_node *np; |
|
struct regmap *grf; |
|
int ret; |
|
|
|
if (!enable_usb_uart) |
|
return 0; |
|
|
|
np = of_find_matching_node_and_match(NULL, rockchip_usb_phy_dt_ids, |
|
&match); |
|
if (!np) { |
|
pr_err("%s: failed to find usbphy node\n", __func__); |
|
return -ENOTSUPP; |
|
} |
|
|
|
pr_debug("%s: using settings for %s\n", __func__, match->compatible); |
|
data = match->data; |
|
|
|
if (!data->init_usb_uart) { |
|
pr_err("%s: usb-uart not available on %s\n", |
|
__func__, match->compatible); |
|
return -ENOTSUPP; |
|
} |
|
|
|
grf = ERR_PTR(-ENODEV); |
|
if (np->parent) |
|
grf = syscon_node_to_regmap(np->parent); |
|
if (IS_ERR(grf)) |
|
grf = syscon_regmap_lookup_by_phandle(np, "rockchip,grf"); |
|
if (IS_ERR(grf)) { |
|
pr_err("%s: Missing rockchip,grf property, %lu\n", |
|
__func__, PTR_ERR(grf)); |
|
return PTR_ERR(grf); |
|
} |
|
|
|
ret = data->init_usb_uart(grf, data); |
|
if (ret) { |
|
pr_err("%s: could not init usb_uart, %d\n", __func__, ret); |
|
enable_usb_uart = 0; |
|
return ret; |
|
} |
|
|
|
return 0; |
|
} |
|
early_initcall(rockchip_init_usb_uart); |
|
|
|
static int __init rockchip_usb_uart(char *buf) |
|
{ |
|
enable_usb_uart = true; |
|
return 0; |
|
} |
|
early_param("rockchip.usb_uart", rockchip_usb_uart); |
|
#endif |
|
|
|
MODULE_AUTHOR("Yunzhi Li <[email protected]>"); |
|
MODULE_DESCRIPTION("Rockchip USB 2.0 PHY driver"); |
|
MODULE_LICENSE("GPL v2");
|
|
|