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426 lines
12 KiB
426 lines
12 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* Rockchip emmc PHY driver |
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* |
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* Copyright (C) 2016 Shawn Lin <[email protected]> |
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* Copyright (C) 2016 ROCKCHIP, Inc. |
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*/ |
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#include <linux/clk.h> |
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#include <linux/delay.h> |
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#include <linux/mfd/syscon.h> |
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#include <linux/module.h> |
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#include <linux/of.h> |
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#include <linux/of_address.h> |
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#include <linux/phy/phy.h> |
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#include <linux/platform_device.h> |
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#include <linux/regmap.h> |
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/* |
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* The higher 16-bit of this register is used for write protection |
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* only if BIT(x + 16) set to 1 the BIT(x) can be written. |
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*/ |
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#define HIWORD_UPDATE(val, mask, shift) \ |
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((val) << (shift) | (mask) << ((shift) + 16)) |
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/* Register definition */ |
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#define GRF_EMMCPHY_CON0 0x0 |
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#define GRF_EMMCPHY_CON1 0x4 |
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#define GRF_EMMCPHY_CON2 0x8 |
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#define GRF_EMMCPHY_CON3 0xc |
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#define GRF_EMMCPHY_CON4 0x10 |
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#define GRF_EMMCPHY_CON5 0x14 |
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#define GRF_EMMCPHY_CON6 0x18 |
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#define GRF_EMMCPHY_STATUS 0x20 |
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#define PHYCTRL_PDB_MASK 0x1 |
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#define PHYCTRL_PDB_SHIFT 0x0 |
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#define PHYCTRL_PDB_PWR_ON 0x1 |
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#define PHYCTRL_PDB_PWR_OFF 0x0 |
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#define PHYCTRL_ENDLL_MASK 0x1 |
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#define PHYCTRL_ENDLL_SHIFT 0x1 |
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#define PHYCTRL_ENDLL_ENABLE 0x1 |
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#define PHYCTRL_ENDLL_DISABLE 0x0 |
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#define PHYCTRL_CALDONE_MASK 0x1 |
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#define PHYCTRL_CALDONE_SHIFT 0x6 |
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#define PHYCTRL_CALDONE_DONE 0x1 |
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#define PHYCTRL_CALDONE_GOING 0x0 |
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#define PHYCTRL_DLLRDY_MASK 0x1 |
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#define PHYCTRL_DLLRDY_SHIFT 0x5 |
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#define PHYCTRL_DLLRDY_DONE 0x1 |
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#define PHYCTRL_DLLRDY_GOING 0x0 |
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#define PHYCTRL_FREQSEL_200M 0x0 |
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#define PHYCTRL_FREQSEL_50M 0x1 |
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#define PHYCTRL_FREQSEL_100M 0x2 |
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#define PHYCTRL_FREQSEL_150M 0x3 |
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#define PHYCTRL_FREQSEL_MASK 0x3 |
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#define PHYCTRL_FREQSEL_SHIFT 0xc |
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#define PHYCTRL_DR_MASK 0x7 |
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#define PHYCTRL_DR_SHIFT 0x4 |
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#define PHYCTRL_DR_50OHM 0x0 |
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#define PHYCTRL_DR_33OHM 0x1 |
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#define PHYCTRL_DR_66OHM 0x2 |
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#define PHYCTRL_DR_100OHM 0x3 |
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#define PHYCTRL_DR_40OHM 0x4 |
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#define PHYCTRL_OTAPDLYENA 0x1 |
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#define PHYCTRL_OTAPDLYENA_MASK 0x1 |
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#define PHYCTRL_OTAPDLYENA_SHIFT 0xb |
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#define PHYCTRL_OTAPDLYSEL_DEFAULT 0x4 |
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#define PHYCTRL_OTAPDLYSEL_MAXVALUE 0xf |
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#define PHYCTRL_OTAPDLYSEL_MASK 0xf |
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#define PHYCTRL_OTAPDLYSEL_SHIFT 0x7 |
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#define PHYCTRL_REN_STRB_DISABLE 0x0 |
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#define PHYCTRL_REN_STRB_ENABLE 0x1 |
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#define PHYCTRL_REN_STRB_MASK 0x1 |
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#define PHYCTRL_REN_STRB_SHIFT 0x9 |
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#define PHYCTRL_IS_CALDONE(x) \ |
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((((x) >> PHYCTRL_CALDONE_SHIFT) & \ |
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PHYCTRL_CALDONE_MASK) == PHYCTRL_CALDONE_DONE) |
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#define PHYCTRL_IS_DLLRDY(x) \ |
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((((x) >> PHYCTRL_DLLRDY_SHIFT) & \ |
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PHYCTRL_DLLRDY_MASK) == PHYCTRL_DLLRDY_DONE) |
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struct rockchip_emmc_phy { |
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unsigned int reg_offset; |
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struct regmap *reg_base; |
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struct clk *emmcclk; |
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unsigned int drive_impedance; |
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unsigned int enable_strobe_pulldown; |
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unsigned int output_tapdelay_select; |
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}; |
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static int rockchip_emmc_phy_power(struct phy *phy, bool on_off) |
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{ |
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struct rockchip_emmc_phy *rk_phy = phy_get_drvdata(phy); |
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unsigned int caldone; |
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unsigned int dllrdy; |
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unsigned int freqsel = PHYCTRL_FREQSEL_200M; |
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unsigned long rate; |
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int ret; |
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/* |
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* Keep phyctrl_pdb and phyctrl_endll low to allow |
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* initialization of CALIO state M/C DFFs |
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*/ |
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regmap_write(rk_phy->reg_base, |
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rk_phy->reg_offset + GRF_EMMCPHY_CON6, |
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HIWORD_UPDATE(PHYCTRL_PDB_PWR_OFF, |
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PHYCTRL_PDB_MASK, |
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PHYCTRL_PDB_SHIFT)); |
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regmap_write(rk_phy->reg_base, |
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rk_phy->reg_offset + GRF_EMMCPHY_CON6, |
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HIWORD_UPDATE(PHYCTRL_ENDLL_DISABLE, |
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PHYCTRL_ENDLL_MASK, |
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PHYCTRL_ENDLL_SHIFT)); |
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/* Already finish power_off above */ |
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if (on_off == PHYCTRL_PDB_PWR_OFF) |
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return 0; |
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rate = clk_get_rate(rk_phy->emmcclk); |
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if (rate != 0) { |
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unsigned long ideal_rate; |
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unsigned long diff; |
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switch (rate) { |
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case 1 ... 74999999: |
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ideal_rate = 50000000; |
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freqsel = PHYCTRL_FREQSEL_50M; |
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break; |
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case 75000000 ... 124999999: |
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ideal_rate = 100000000; |
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freqsel = PHYCTRL_FREQSEL_100M; |
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break; |
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case 125000000 ... 174999999: |
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ideal_rate = 150000000; |
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freqsel = PHYCTRL_FREQSEL_150M; |
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break; |
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default: |
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ideal_rate = 200000000; |
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break; |
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} |
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diff = (rate > ideal_rate) ? |
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rate - ideal_rate : ideal_rate - rate; |
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/* |
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* In order for tuning delays to be accurate we need to be |
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* pretty spot on for the DLL range, so warn if we're too |
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* far off. Also warn if we're above the 200 MHz max. Don't |
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* warn for really slow rates since we won't be tuning then. |
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*/ |
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if ((rate > 50000000 && diff > 15000000) || (rate > 200000000)) |
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dev_warn(&phy->dev, "Unsupported rate: %lu\n", rate); |
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} |
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/* |
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* According to the user manual, calpad calibration |
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* cycle takes more than 2us without the minimal recommended |
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* value, so we may need a little margin here |
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*/ |
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udelay(3); |
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regmap_write(rk_phy->reg_base, |
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rk_phy->reg_offset + GRF_EMMCPHY_CON6, |
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HIWORD_UPDATE(PHYCTRL_PDB_PWR_ON, |
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PHYCTRL_PDB_MASK, |
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PHYCTRL_PDB_SHIFT)); |
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/* |
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* According to the user manual, it asks driver to wait 5us for |
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* calpad busy trimming. However it is documented that this value is |
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* PVT(A.K.A process,voltage and temperature) relevant, so some |
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* failure cases are found which indicates we should be more tolerant |
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* to calpad busy trimming. |
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*/ |
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ret = regmap_read_poll_timeout(rk_phy->reg_base, |
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rk_phy->reg_offset + GRF_EMMCPHY_STATUS, |
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caldone, PHYCTRL_IS_CALDONE(caldone), |
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0, 50); |
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if (ret) { |
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pr_err("%s: caldone failed, ret=%d\n", __func__, ret); |
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return ret; |
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} |
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/* Set the frequency of the DLL operation */ |
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regmap_write(rk_phy->reg_base, |
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rk_phy->reg_offset + GRF_EMMCPHY_CON0, |
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HIWORD_UPDATE(freqsel, PHYCTRL_FREQSEL_MASK, |
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PHYCTRL_FREQSEL_SHIFT)); |
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/* Turn on the DLL */ |
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regmap_write(rk_phy->reg_base, |
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rk_phy->reg_offset + GRF_EMMCPHY_CON6, |
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HIWORD_UPDATE(PHYCTRL_ENDLL_ENABLE, |
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PHYCTRL_ENDLL_MASK, |
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PHYCTRL_ENDLL_SHIFT)); |
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/* |
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* We turned on the DLL even though the rate was 0 because we the |
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* clock might be turned on later. ...but we can't wait for the DLL |
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* to lock when the rate is 0 because it will never lock with no |
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* input clock. |
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* |
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* Technically we should be checking the lock later when the clock |
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* is turned on, but for now we won't. |
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*/ |
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if (rate == 0) |
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return 0; |
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/* |
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* After enabling analog DLL circuits docs say that we need 10.2 us if |
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* our source clock is at 50 MHz and that lock time scales linearly |
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* with clock speed. If we are powering on the PHY and the card clock |
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* is super slow (like 100 kHZ) this could take as long as 5.1 ms as |
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* per the math: 10.2 us * (50000000 Hz / 100000 Hz) => 5.1 ms |
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* Hopefully we won't be running at 100 kHz, but we should still make |
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* sure we wait long enough. |
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* |
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* NOTE: There appear to be corner cases where the DLL seems to take |
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* extra long to lock for reasons that aren't understood. In some |
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* extreme cases we've seen it take up to over 10ms (!). We'll be |
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* generous and give it 50ms. |
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*/ |
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ret = regmap_read_poll_timeout(rk_phy->reg_base, |
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rk_phy->reg_offset + GRF_EMMCPHY_STATUS, |
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dllrdy, PHYCTRL_IS_DLLRDY(dllrdy), |
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0, 50 * USEC_PER_MSEC); |
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if (ret) { |
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pr_err("%s: dllrdy failed. ret=%d\n", __func__, ret); |
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return ret; |
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} |
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return 0; |
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} |
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static int rockchip_emmc_phy_init(struct phy *phy) |
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{ |
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struct rockchip_emmc_phy *rk_phy = phy_get_drvdata(phy); |
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int ret = 0; |
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/* |
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* We purposely get the clock here and not in probe to avoid the |
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* circular dependency problem. We expect: |
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* - PHY driver to probe |
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* - SDHCI driver to start probe |
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* - SDHCI driver to register it's clock |
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* - SDHCI driver to get the PHY |
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* - SDHCI driver to init the PHY |
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* |
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* The clock is optional, using clk_get_optional() to get the clock |
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* and do error processing if the return value != NULL |
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* |
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* NOTE: we don't do anything special for EPROBE_DEFER here. Given the |
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* above expected use case, EPROBE_DEFER isn't sensible to expect, so |
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* it's just like any other error. |
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*/ |
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rk_phy->emmcclk = clk_get_optional(&phy->dev, "emmcclk"); |
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if (IS_ERR(rk_phy->emmcclk)) { |
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ret = PTR_ERR(rk_phy->emmcclk); |
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dev_err(&phy->dev, "Error getting emmcclk: %d\n", ret); |
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rk_phy->emmcclk = NULL; |
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} |
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return ret; |
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} |
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static int rockchip_emmc_phy_exit(struct phy *phy) |
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{ |
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struct rockchip_emmc_phy *rk_phy = phy_get_drvdata(phy); |
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clk_put(rk_phy->emmcclk); |
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return 0; |
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} |
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static int rockchip_emmc_phy_power_off(struct phy *phy) |
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{ |
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/* Power down emmc phy analog blocks */ |
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return rockchip_emmc_phy_power(phy, PHYCTRL_PDB_PWR_OFF); |
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} |
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static int rockchip_emmc_phy_power_on(struct phy *phy) |
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{ |
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struct rockchip_emmc_phy *rk_phy = phy_get_drvdata(phy); |
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/* Drive impedance: from DTS */ |
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regmap_write(rk_phy->reg_base, |
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rk_phy->reg_offset + GRF_EMMCPHY_CON6, |
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HIWORD_UPDATE(rk_phy->drive_impedance, |
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PHYCTRL_DR_MASK, |
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PHYCTRL_DR_SHIFT)); |
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/* Output tap delay: enable */ |
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regmap_write(rk_phy->reg_base, |
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rk_phy->reg_offset + GRF_EMMCPHY_CON0, |
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HIWORD_UPDATE(PHYCTRL_OTAPDLYENA, |
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PHYCTRL_OTAPDLYENA_MASK, |
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PHYCTRL_OTAPDLYENA_SHIFT)); |
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/* Output tap delay */ |
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regmap_write(rk_phy->reg_base, |
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rk_phy->reg_offset + GRF_EMMCPHY_CON0, |
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HIWORD_UPDATE(rk_phy->output_tapdelay_select, |
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PHYCTRL_OTAPDLYSEL_MASK, |
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PHYCTRL_OTAPDLYSEL_SHIFT)); |
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/* Internal pull-down for strobe line */ |
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regmap_write(rk_phy->reg_base, |
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rk_phy->reg_offset + GRF_EMMCPHY_CON2, |
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HIWORD_UPDATE(rk_phy->enable_strobe_pulldown, |
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PHYCTRL_REN_STRB_MASK, |
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PHYCTRL_REN_STRB_SHIFT)); |
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/* Power up emmc phy analog blocks */ |
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return rockchip_emmc_phy_power(phy, PHYCTRL_PDB_PWR_ON); |
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} |
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static const struct phy_ops ops = { |
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.init = rockchip_emmc_phy_init, |
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.exit = rockchip_emmc_phy_exit, |
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.power_on = rockchip_emmc_phy_power_on, |
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.power_off = rockchip_emmc_phy_power_off, |
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.owner = THIS_MODULE, |
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}; |
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static u32 convert_drive_impedance_ohm(struct platform_device *pdev, u32 dr_ohm) |
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{ |
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switch (dr_ohm) { |
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case 100: |
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return PHYCTRL_DR_100OHM; |
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case 66: |
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return PHYCTRL_DR_66OHM; |
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case 50: |
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return PHYCTRL_DR_50OHM; |
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case 40: |
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return PHYCTRL_DR_40OHM; |
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case 33: |
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return PHYCTRL_DR_33OHM; |
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} |
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dev_warn(&pdev->dev, "Invalid value %u for drive-impedance-ohm.\n", |
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dr_ohm); |
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return PHYCTRL_DR_50OHM; |
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} |
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static int rockchip_emmc_phy_probe(struct platform_device *pdev) |
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{ |
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struct device *dev = &pdev->dev; |
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struct rockchip_emmc_phy *rk_phy; |
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struct phy *generic_phy; |
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struct phy_provider *phy_provider; |
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struct regmap *grf; |
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unsigned int reg_offset; |
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u32 val; |
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if (!dev->parent || !dev->parent->of_node) |
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return -ENODEV; |
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grf = syscon_node_to_regmap(dev->parent->of_node); |
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if (IS_ERR(grf)) { |
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dev_err(dev, "Missing rockchip,grf property\n"); |
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return PTR_ERR(grf); |
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} |
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rk_phy = devm_kzalloc(dev, sizeof(*rk_phy), GFP_KERNEL); |
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if (!rk_phy) |
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return -ENOMEM; |
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if (of_property_read_u32(dev->of_node, "reg", ®_offset)) { |
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dev_err(dev, "missing reg property in node %pOFn\n", |
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dev->of_node); |
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return -EINVAL; |
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} |
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rk_phy->reg_offset = reg_offset; |
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rk_phy->reg_base = grf; |
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rk_phy->drive_impedance = PHYCTRL_DR_50OHM; |
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rk_phy->enable_strobe_pulldown = PHYCTRL_REN_STRB_DISABLE; |
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rk_phy->output_tapdelay_select = PHYCTRL_OTAPDLYSEL_DEFAULT; |
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if (!of_property_read_u32(dev->of_node, "drive-impedance-ohm", &val)) |
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rk_phy->drive_impedance = convert_drive_impedance_ohm(pdev, val); |
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if (of_property_read_bool(dev->of_node, "rockchip,enable-strobe-pulldown")) |
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rk_phy->enable_strobe_pulldown = PHYCTRL_REN_STRB_ENABLE; |
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if (!of_property_read_u32(dev->of_node, "rockchip,output-tapdelay-select", &val)) { |
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if (val <= PHYCTRL_OTAPDLYSEL_MAXVALUE) |
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rk_phy->output_tapdelay_select = val; |
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else |
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dev_err(dev, "output-tapdelay-select exceeds limit, apply default\n"); |
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} |
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generic_phy = devm_phy_create(dev, dev->of_node, &ops); |
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if (IS_ERR(generic_phy)) { |
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dev_err(dev, "failed to create PHY\n"); |
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return PTR_ERR(generic_phy); |
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} |
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phy_set_drvdata(generic_phy, rk_phy); |
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phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); |
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return PTR_ERR_OR_ZERO(phy_provider); |
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} |
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static const struct of_device_id rockchip_emmc_phy_dt_ids[] = { |
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{ .compatible = "rockchip,rk3399-emmc-phy" }, |
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{} |
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}; |
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MODULE_DEVICE_TABLE(of, rockchip_emmc_phy_dt_ids); |
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static struct platform_driver rockchip_emmc_driver = { |
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.probe = rockchip_emmc_phy_probe, |
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.driver = { |
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.name = "rockchip-emmc-phy", |
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.of_match_table = rockchip_emmc_phy_dt_ids, |
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}, |
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}; |
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module_platform_driver(rockchip_emmc_driver); |
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MODULE_AUTHOR("Shawn Lin <[email protected]>"); |
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MODULE_DESCRIPTION("Rockchip EMMC PHY driver"); |
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MODULE_LICENSE("GPL v2");
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