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341 lines
9.2 KiB
341 lines
9.2 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* Copyright (C) 2015 Linaro, Ltd. |
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* Rob Herring <[email protected]> |
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* |
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* Based on vendor driver: |
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* Copyright (C) 2013 Marvell Inc. |
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* Author: Chao Xie <[email protected]> |
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*/ |
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#include <linux/delay.h> |
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#include <linux/slab.h> |
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#include <linux/of.h> |
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#include <linux/of_device.h> |
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#include <linux/io.h> |
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#include <linux/iopoll.h> |
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#include <linux/err.h> |
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#include <linux/clk.h> |
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#include <linux/module.h> |
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#include <linux/platform_device.h> |
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#include <linux/phy/phy.h> |
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/* USB PXA1928 PHY mapping */ |
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#define PHY_28NM_PLL_REG0 0x0 |
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#define PHY_28NM_PLL_REG1 0x4 |
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#define PHY_28NM_CAL_REG 0x8 |
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#define PHY_28NM_TX_REG0 0x0c |
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#define PHY_28NM_TX_REG1 0x10 |
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#define PHY_28NM_RX_REG0 0x14 |
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#define PHY_28NM_RX_REG1 0x18 |
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#define PHY_28NM_DIG_REG0 0x1c |
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#define PHY_28NM_DIG_REG1 0x20 |
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#define PHY_28NM_TEST_REG0 0x24 |
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#define PHY_28NM_TEST_REG1 0x28 |
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#define PHY_28NM_MOC_REG 0x2c |
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#define PHY_28NM_PHY_RESERVE 0x30 |
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#define PHY_28NM_OTG_REG 0x34 |
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#define PHY_28NM_CHRG_DET 0x38 |
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#define PHY_28NM_CTRL_REG0 0xc4 |
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#define PHY_28NM_CTRL_REG1 0xc8 |
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#define PHY_28NM_CTRL_REG2 0xd4 |
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#define PHY_28NM_CTRL_REG3 0xdc |
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/* PHY_28NM_PLL_REG0 */ |
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#define PHY_28NM_PLL_READY BIT(31) |
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#define PHY_28NM_PLL_SELLPFR_SHIFT 28 |
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#define PHY_28NM_PLL_SELLPFR_MASK (0x3 << 28) |
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#define PHY_28NM_PLL_FBDIV_SHIFT 16 |
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#define PHY_28NM_PLL_FBDIV_MASK (0x1ff << 16) |
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#define PHY_28NM_PLL_ICP_SHIFT 8 |
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#define PHY_28NM_PLL_ICP_MASK (0x7 << 8) |
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#define PHY_28NM_PLL_REFDIV_SHIFT 0 |
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#define PHY_28NM_PLL_REFDIV_MASK 0x7f |
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/* PHY_28NM_PLL_REG1 */ |
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#define PHY_28NM_PLL_PU_BY_REG BIT(1) |
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#define PHY_28NM_PLL_PU_PLL BIT(0) |
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/* PHY_28NM_CAL_REG */ |
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#define PHY_28NM_PLL_PLLCAL_DONE BIT(31) |
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#define PHY_28NM_PLL_IMPCAL_DONE BIT(23) |
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#define PHY_28NM_PLL_KVCO_SHIFT 16 |
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#define PHY_28NM_PLL_KVCO_MASK (0x7 << 16) |
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#define PHY_28NM_PLL_CAL12_SHIFT 20 |
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#define PHY_28NM_PLL_CAL12_MASK (0x3 << 20) |
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#define PHY_28NM_IMPCAL_VTH_SHIFT 8 |
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#define PHY_28NM_IMPCAL_VTH_MASK (0x7 << 8) |
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#define PHY_28NM_PLLCAL_START_SHIFT 22 |
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#define PHY_28NM_IMPCAL_START_SHIFT 13 |
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/* PHY_28NM_TX_REG0 */ |
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#define PHY_28NM_TX_PU_BY_REG BIT(25) |
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#define PHY_28NM_TX_PU_ANA BIT(24) |
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#define PHY_28NM_TX_AMP_SHIFT 20 |
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#define PHY_28NM_TX_AMP_MASK (0x7 << 20) |
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/* PHY_28NM_RX_REG0 */ |
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#define PHY_28NM_RX_SQ_THRESH_SHIFT 0 |
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#define PHY_28NM_RX_SQ_THRESH_MASK (0xf << 0) |
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/* PHY_28NM_RX_REG1 */ |
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#define PHY_28NM_RX_SQCAL_DONE BIT(31) |
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/* PHY_28NM_DIG_REG0 */ |
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#define PHY_28NM_DIG_BITSTAFFING_ERR BIT(31) |
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#define PHY_28NM_DIG_SYNC_ERR BIT(30) |
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#define PHY_28NM_DIG_SQ_FILT_SHIFT 16 |
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#define PHY_28NM_DIG_SQ_FILT_MASK (0x7 << 16) |
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#define PHY_28NM_DIG_SQ_BLK_SHIFT 12 |
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#define PHY_28NM_DIG_SQ_BLK_MASK (0x7 << 12) |
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#define PHY_28NM_DIG_SYNC_NUM_SHIFT 0 |
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#define PHY_28NM_DIG_SYNC_NUM_MASK (0x3 << 0) |
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#define PHY_28NM_PLL_LOCK_BYPASS BIT(7) |
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/* PHY_28NM_OTG_REG */ |
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#define PHY_28NM_OTG_CONTROL_BY_PIN BIT(5) |
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#define PHY_28NM_OTG_PU_OTG BIT(4) |
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#define PHY_28NM_CHGDTC_ENABLE_SWITCH_DM_SHIFT_28 13 |
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#define PHY_28NM_CHGDTC_ENABLE_SWITCH_DP_SHIFT_28 12 |
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#define PHY_28NM_CHGDTC_VSRC_CHARGE_SHIFT_28 10 |
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#define PHY_28NM_CHGDTC_VDAT_CHARGE_SHIFT_28 8 |
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#define PHY_28NM_CHGDTC_CDP_DM_AUTO_SWITCH_SHIFT_28 7 |
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#define PHY_28NM_CHGDTC_DP_DM_SWAP_SHIFT_28 6 |
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#define PHY_28NM_CHGDTC_PU_CHRG_DTC_SHIFT_28 5 |
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#define PHY_28NM_CHGDTC_PD_EN_SHIFT_28 4 |
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#define PHY_28NM_CHGDTC_DCP_EN_SHIFT_28 3 |
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#define PHY_28NM_CHGDTC_CDP_EN_SHIFT_28 2 |
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#define PHY_28NM_CHGDTC_TESTMON_CHRGDTC_SHIFT_28 0 |
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#define PHY_28NM_CTRL1_CHRG_DTC_OUT_SHIFT_28 4 |
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#define PHY_28NM_CTRL1_VBUSDTC_OUT_SHIFT_28 2 |
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#define PHY_28NM_CTRL3_OVERWRITE BIT(0) |
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#define PHY_28NM_CTRL3_VBUS_VALID BIT(4) |
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#define PHY_28NM_CTRL3_AVALID BIT(5) |
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#define PHY_28NM_CTRL3_BVALID BIT(6) |
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struct mv_usb2_phy { |
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struct phy *phy; |
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struct platform_device *pdev; |
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void __iomem *base; |
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struct clk *clk; |
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}; |
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static int wait_for_reg(void __iomem *reg, u32 mask, u32 ms) |
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{ |
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u32 val; |
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return readl_poll_timeout(reg, val, ((val & mask) == mask), |
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1000, 1000 * ms); |
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} |
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static int mv_usb2_phy_28nm_init(struct phy *phy) |
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{ |
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struct mv_usb2_phy *mv_phy = phy_get_drvdata(phy); |
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struct platform_device *pdev = mv_phy->pdev; |
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void __iomem *base = mv_phy->base; |
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u32 reg; |
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int ret; |
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clk_prepare_enable(mv_phy->clk); |
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/* PHY_28NM_PLL_REG0 */ |
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reg = readl(base + PHY_28NM_PLL_REG0) & |
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~(PHY_28NM_PLL_SELLPFR_MASK | PHY_28NM_PLL_FBDIV_MASK |
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| PHY_28NM_PLL_ICP_MASK | PHY_28NM_PLL_REFDIV_MASK); |
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writel(reg | (0x1 << PHY_28NM_PLL_SELLPFR_SHIFT |
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| 0xf0 << PHY_28NM_PLL_FBDIV_SHIFT |
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| 0x3 << PHY_28NM_PLL_ICP_SHIFT |
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| 0xd << PHY_28NM_PLL_REFDIV_SHIFT), |
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base + PHY_28NM_PLL_REG0); |
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/* PHY_28NM_PLL_REG1 */ |
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reg = readl(base + PHY_28NM_PLL_REG1); |
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writel(reg | PHY_28NM_PLL_PU_PLL | PHY_28NM_PLL_PU_BY_REG, |
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base + PHY_28NM_PLL_REG1); |
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/* PHY_28NM_TX_REG0 */ |
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reg = readl(base + PHY_28NM_TX_REG0) & ~PHY_28NM_TX_AMP_MASK; |
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writel(reg | PHY_28NM_TX_PU_BY_REG | 0x3 << PHY_28NM_TX_AMP_SHIFT | |
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PHY_28NM_TX_PU_ANA, |
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base + PHY_28NM_TX_REG0); |
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/* PHY_28NM_RX_REG0 */ |
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reg = readl(base + PHY_28NM_RX_REG0) & ~PHY_28NM_RX_SQ_THRESH_MASK; |
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writel(reg | 0xa << PHY_28NM_RX_SQ_THRESH_SHIFT, |
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base + PHY_28NM_RX_REG0); |
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/* PHY_28NM_DIG_REG0 */ |
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reg = readl(base + PHY_28NM_DIG_REG0) & |
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~(PHY_28NM_DIG_BITSTAFFING_ERR | PHY_28NM_DIG_SYNC_ERR | |
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PHY_28NM_DIG_SQ_FILT_MASK | PHY_28NM_DIG_SQ_BLK_MASK | |
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PHY_28NM_DIG_SYNC_NUM_MASK); |
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writel(reg | (0x1 << PHY_28NM_DIG_SYNC_NUM_SHIFT | |
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PHY_28NM_PLL_LOCK_BYPASS), |
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base + PHY_28NM_DIG_REG0); |
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/* PHY_28NM_OTG_REG */ |
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reg = readl(base + PHY_28NM_OTG_REG) | PHY_28NM_OTG_PU_OTG; |
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writel(reg & ~PHY_28NM_OTG_CONTROL_BY_PIN, base + PHY_28NM_OTG_REG); |
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/* |
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* Calibration Timing |
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* ____________________________ |
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* CAL START ___| |
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* ____________________ |
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* CAL_DONE ___________| |
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* | 400us | |
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*/ |
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/* Make sure PHY Calibration is ready */ |
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ret = wait_for_reg(base + PHY_28NM_CAL_REG, |
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PHY_28NM_PLL_PLLCAL_DONE | PHY_28NM_PLL_IMPCAL_DONE, |
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100); |
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if (ret) { |
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dev_warn(&pdev->dev, "USB PHY PLL calibrate not done after 100mS."); |
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goto err_clk; |
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} |
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ret = wait_for_reg(base + PHY_28NM_RX_REG1, |
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PHY_28NM_RX_SQCAL_DONE, 100); |
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if (ret) { |
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dev_warn(&pdev->dev, "USB PHY RX SQ calibrate not done after 100mS."); |
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goto err_clk; |
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} |
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/* Make sure PHY PLL is ready */ |
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ret = wait_for_reg(base + PHY_28NM_PLL_REG0, PHY_28NM_PLL_READY, 100); |
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if (ret) { |
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dev_warn(&pdev->dev, "PLL_READY not set after 100mS."); |
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goto err_clk; |
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} |
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return 0; |
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err_clk: |
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clk_disable_unprepare(mv_phy->clk); |
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return ret; |
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} |
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static int mv_usb2_phy_28nm_power_on(struct phy *phy) |
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{ |
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struct mv_usb2_phy *mv_phy = phy_get_drvdata(phy); |
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void __iomem *base = mv_phy->base; |
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writel(readl(base + PHY_28NM_CTRL_REG3) | |
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(PHY_28NM_CTRL3_OVERWRITE | PHY_28NM_CTRL3_VBUS_VALID | |
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PHY_28NM_CTRL3_AVALID | PHY_28NM_CTRL3_BVALID), |
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base + PHY_28NM_CTRL_REG3); |
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return 0; |
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} |
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static int mv_usb2_phy_28nm_power_off(struct phy *phy) |
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{ |
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struct mv_usb2_phy *mv_phy = phy_get_drvdata(phy); |
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void __iomem *base = mv_phy->base; |
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writel(readl(base + PHY_28NM_CTRL_REG3) | |
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~(PHY_28NM_CTRL3_OVERWRITE | PHY_28NM_CTRL3_VBUS_VALID |
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| PHY_28NM_CTRL3_AVALID | PHY_28NM_CTRL3_BVALID), |
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base + PHY_28NM_CTRL_REG3); |
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return 0; |
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} |
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static int mv_usb2_phy_28nm_exit(struct phy *phy) |
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{ |
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struct mv_usb2_phy *mv_phy = phy_get_drvdata(phy); |
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void __iomem *base = mv_phy->base; |
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unsigned int val; |
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val = readw(base + PHY_28NM_PLL_REG1); |
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val &= ~PHY_28NM_PLL_PU_PLL; |
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writew(val, base + PHY_28NM_PLL_REG1); |
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/* power down PHY Analog part */ |
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val = readw(base + PHY_28NM_TX_REG0); |
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val &= ~PHY_28NM_TX_PU_ANA; |
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writew(val, base + PHY_28NM_TX_REG0); |
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/* power down PHY OTG part */ |
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val = readw(base + PHY_28NM_OTG_REG); |
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val &= ~PHY_28NM_OTG_PU_OTG; |
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writew(val, base + PHY_28NM_OTG_REG); |
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clk_disable_unprepare(mv_phy->clk); |
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return 0; |
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} |
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static const struct phy_ops usb_ops = { |
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.init = mv_usb2_phy_28nm_init, |
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.power_on = mv_usb2_phy_28nm_power_on, |
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.power_off = mv_usb2_phy_28nm_power_off, |
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.exit = mv_usb2_phy_28nm_exit, |
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.owner = THIS_MODULE, |
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}; |
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static int mv_usb2_phy_probe(struct platform_device *pdev) |
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{ |
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struct phy_provider *phy_provider; |
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struct mv_usb2_phy *mv_phy; |
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mv_phy = devm_kzalloc(&pdev->dev, sizeof(*mv_phy), GFP_KERNEL); |
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if (!mv_phy) |
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return -ENOMEM; |
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mv_phy->pdev = pdev; |
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mv_phy->clk = devm_clk_get(&pdev->dev, NULL); |
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if (IS_ERR(mv_phy->clk)) { |
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dev_err(&pdev->dev, "failed to get clock.\n"); |
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return PTR_ERR(mv_phy->clk); |
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} |
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mv_phy->base = devm_platform_ioremap_resource(pdev, 0); |
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if (IS_ERR(mv_phy->base)) |
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return PTR_ERR(mv_phy->base); |
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mv_phy->phy = devm_phy_create(&pdev->dev, pdev->dev.of_node, &usb_ops); |
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if (IS_ERR(mv_phy->phy)) |
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return PTR_ERR(mv_phy->phy); |
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phy_set_drvdata(mv_phy->phy, mv_phy); |
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phy_provider = devm_of_phy_provider_register(&pdev->dev, of_phy_simple_xlate); |
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return PTR_ERR_OR_ZERO(phy_provider); |
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} |
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static const struct of_device_id mv_usbphy_dt_match[] = { |
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{ .compatible = "marvell,pxa1928-usb-phy", }, |
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{}, |
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}; |
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MODULE_DEVICE_TABLE(of, mv_usbphy_dt_match); |
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static struct platform_driver mv_usb2_phy_driver = { |
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.probe = mv_usb2_phy_probe, |
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.driver = { |
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.name = "mv-usb2-phy", |
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.of_match_table = of_match_ptr(mv_usbphy_dt_match), |
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}, |
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}; |
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module_platform_driver(mv_usb2_phy_driver); |
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MODULE_AUTHOR("Rob Herring <[email protected]>"); |
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MODULE_DESCRIPTION("Marvell USB2 phy driver"); |
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MODULE_LICENSE("GPL v2");
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