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503 lines
11 KiB
503 lines
11 KiB
// SPDX-License-Identifier: GPL-2.0-or-later |
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/* |
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* Fitipower FC0012 tuner driver |
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* |
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* Copyright (C) 2012 Hans-Frieder Vogt <[email protected]> |
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*/ |
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|
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#include "fc0012.h" |
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#include "fc0012-priv.h" |
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|
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static int fc0012_writereg(struct fc0012_priv *priv, u8 reg, u8 val) |
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{ |
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u8 buf[2] = {reg, val}; |
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struct i2c_msg msg = { |
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.addr = priv->cfg->i2c_address, .flags = 0, .buf = buf, .len = 2 |
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}; |
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if (i2c_transfer(priv->i2c, &msg, 1) != 1) { |
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dev_err(&priv->i2c->dev, |
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"%s: I2C write reg failed, reg: %02x, val: %02x\n", |
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KBUILD_MODNAME, reg, val); |
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return -EREMOTEIO; |
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} |
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return 0; |
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} |
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static int fc0012_readreg(struct fc0012_priv *priv, u8 reg, u8 *val) |
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{ |
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struct i2c_msg msg[2] = { |
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{ .addr = priv->cfg->i2c_address, .flags = 0, |
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.buf = ®, .len = 1 }, |
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{ .addr = priv->cfg->i2c_address, .flags = I2C_M_RD, |
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.buf = val, .len = 1 }, |
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}; |
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if (i2c_transfer(priv->i2c, msg, 2) != 2) { |
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dev_err(&priv->i2c->dev, |
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"%s: I2C read reg failed, reg: %02x\n", |
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KBUILD_MODNAME, reg); |
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return -EREMOTEIO; |
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} |
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return 0; |
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} |
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static void fc0012_release(struct dvb_frontend *fe) |
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{ |
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kfree(fe->tuner_priv); |
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fe->tuner_priv = NULL; |
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} |
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static int fc0012_init(struct dvb_frontend *fe) |
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{ |
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struct fc0012_priv *priv = fe->tuner_priv; |
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int i, ret = 0; |
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unsigned char reg[] = { |
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0x00, /* dummy reg. 0 */ |
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0x05, /* reg. 0x01 */ |
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0x10, /* reg. 0x02 */ |
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0x00, /* reg. 0x03 */ |
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0x00, /* reg. 0x04 */ |
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0x0f, /* reg. 0x05: may also be 0x0a */ |
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0x00, /* reg. 0x06: divider 2, VCO slow */ |
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0x00, /* reg. 0x07: may also be 0x0f */ |
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0xff, /* reg. 0x08: AGC Clock divide by 256, AGC gain 1/256, |
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Loop Bw 1/8 */ |
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0x6e, /* reg. 0x09: Disable LoopThrough, Enable LoopThrough: 0x6f */ |
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0xb8, /* reg. 0x0a: Disable LO Test Buffer */ |
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0x82, /* reg. 0x0b: Output Clock is same as clock frequency, |
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may also be 0x83 */ |
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0xfc, /* reg. 0x0c: depending on AGC Up-Down mode, may need 0xf8 */ |
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0x02, /* reg. 0x0d: AGC Not Forcing & LNA Forcing, 0x02 for DVB-T */ |
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0x00, /* reg. 0x0e */ |
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0x00, /* reg. 0x0f */ |
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0x00, /* reg. 0x10: may also be 0x0d */ |
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0x00, /* reg. 0x11 */ |
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0x1f, /* reg. 0x12: Set to maximum gain */ |
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0x08, /* reg. 0x13: Set to Middle Gain: 0x08, |
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Low Gain: 0x00, High Gain: 0x10, enable IX2: 0x80 */ |
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0x00, /* reg. 0x14 */ |
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0x04, /* reg. 0x15: Enable LNA COMPS */ |
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}; |
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switch (priv->cfg->xtal_freq) { |
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case FC_XTAL_27_MHZ: |
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case FC_XTAL_28_8_MHZ: |
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reg[0x07] |= 0x20; |
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break; |
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case FC_XTAL_36_MHZ: |
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default: |
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break; |
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} |
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if (priv->cfg->dual_master) |
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reg[0x0c] |= 0x02; |
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if (priv->cfg->loop_through) |
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reg[0x09] |= 0x01; |
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if (fe->ops.i2c_gate_ctrl) |
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fe->ops.i2c_gate_ctrl(fe, 1); /* open I2C-gate */ |
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for (i = 1; i < sizeof(reg); i++) { |
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ret = fc0012_writereg(priv, i, reg[i]); |
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if (ret) |
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break; |
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} |
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if (fe->ops.i2c_gate_ctrl) |
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fe->ops.i2c_gate_ctrl(fe, 0); /* close I2C-gate */ |
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if (ret) |
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dev_err(&priv->i2c->dev, "%s: fc0012_writereg failed: %d\n", |
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KBUILD_MODNAME, ret); |
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return ret; |
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} |
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static int fc0012_set_params(struct dvb_frontend *fe) |
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{ |
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struct fc0012_priv *priv = fe->tuner_priv; |
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int i, ret = 0; |
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struct dtv_frontend_properties *p = &fe->dtv_property_cache; |
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u32 freq = p->frequency / 1000; |
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u32 delsys = p->delivery_system; |
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unsigned char reg[7], am, pm, multi, tmp; |
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unsigned long f_vco; |
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unsigned short xtal_freq_khz_2, xin, xdiv; |
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bool vco_select = false; |
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if (fe->callback) { |
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ret = fe->callback(priv->i2c, DVB_FRONTEND_COMPONENT_TUNER, |
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FC_FE_CALLBACK_VHF_ENABLE, (freq > 300000 ? 0 : 1)); |
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if (ret) |
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goto exit; |
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} |
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switch (priv->cfg->xtal_freq) { |
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case FC_XTAL_27_MHZ: |
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xtal_freq_khz_2 = 27000 / 2; |
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break; |
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case FC_XTAL_36_MHZ: |
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xtal_freq_khz_2 = 36000 / 2; |
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break; |
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case FC_XTAL_28_8_MHZ: |
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default: |
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xtal_freq_khz_2 = 28800 / 2; |
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break; |
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} |
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/* select frequency divider and the frequency of VCO */ |
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if (freq < 37084) { /* freq * 96 < 3560000 */ |
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multi = 96; |
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reg[5] = 0x82; |
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reg[6] = 0x00; |
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} else if (freq < 55625) { /* freq * 64 < 3560000 */ |
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multi = 64; |
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reg[5] = 0x82; |
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reg[6] = 0x02; |
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} else if (freq < 74167) { /* freq * 48 < 3560000 */ |
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multi = 48; |
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reg[5] = 0x42; |
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reg[6] = 0x00; |
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} else if (freq < 111250) { /* freq * 32 < 3560000 */ |
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multi = 32; |
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reg[5] = 0x42; |
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reg[6] = 0x02; |
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} else if (freq < 148334) { /* freq * 24 < 3560000 */ |
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multi = 24; |
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reg[5] = 0x22; |
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reg[6] = 0x00; |
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} else if (freq < 222500) { /* freq * 16 < 3560000 */ |
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multi = 16; |
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reg[5] = 0x22; |
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reg[6] = 0x02; |
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} else if (freq < 296667) { /* freq * 12 < 3560000 */ |
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multi = 12; |
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reg[5] = 0x12; |
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reg[6] = 0x00; |
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} else if (freq < 445000) { /* freq * 8 < 3560000 */ |
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multi = 8; |
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reg[5] = 0x12; |
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reg[6] = 0x02; |
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} else if (freq < 593334) { /* freq * 6 < 3560000 */ |
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multi = 6; |
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reg[5] = 0x0a; |
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reg[6] = 0x00; |
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} else { |
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multi = 4; |
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reg[5] = 0x0a; |
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reg[6] = 0x02; |
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} |
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f_vco = freq * multi; |
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if (f_vco >= 3060000) { |
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reg[6] |= 0x08; |
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vco_select = true; |
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} |
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if (freq >= 45000) { |
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/* From divided value (XDIV) determined the FA and FP value */ |
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xdiv = (unsigned short)(f_vco / xtal_freq_khz_2); |
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if ((f_vco - xdiv * xtal_freq_khz_2) >= (xtal_freq_khz_2 / 2)) |
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xdiv++; |
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pm = (unsigned char)(xdiv / 8); |
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am = (unsigned char)(xdiv - (8 * pm)); |
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if (am < 2) { |
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reg[1] = am + 8; |
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reg[2] = pm - 1; |
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} else { |
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reg[1] = am; |
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reg[2] = pm; |
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} |
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} else { |
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/* fix for frequency less than 45 MHz */ |
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reg[1] = 0x06; |
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reg[2] = 0x11; |
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} |
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/* fix clock out */ |
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reg[6] |= 0x20; |
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/* From VCO frequency determines the XIN ( fractional part of Delta |
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Sigma PLL) and divided value (XDIV) */ |
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xin = (unsigned short)(f_vco - (f_vco / xtal_freq_khz_2) * xtal_freq_khz_2); |
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xin = (xin << 15) / xtal_freq_khz_2; |
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if (xin >= 16384) |
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xin += 32768; |
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reg[3] = xin >> 8; /* xin with 9 bit resolution */ |
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reg[4] = xin & 0xff; |
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if (delsys == SYS_DVBT) { |
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reg[6] &= 0x3f; /* bits 6 and 7 describe the bandwidth */ |
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switch (p->bandwidth_hz) { |
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case 6000000: |
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reg[6] |= 0x80; |
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break; |
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case 7000000: |
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reg[6] |= 0x40; |
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break; |
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case 8000000: |
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default: |
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break; |
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} |
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} else { |
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dev_err(&priv->i2c->dev, "%s: modulation type not supported!\n", |
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KBUILD_MODNAME); |
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return -EINVAL; |
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} |
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/* modified for Realtek demod */ |
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reg[5] |= 0x07; |
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if (fe->ops.i2c_gate_ctrl) |
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fe->ops.i2c_gate_ctrl(fe, 1); /* open I2C-gate */ |
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for (i = 1; i <= 6; i++) { |
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ret = fc0012_writereg(priv, i, reg[i]); |
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if (ret) |
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goto exit; |
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} |
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/* VCO Calibration */ |
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ret = fc0012_writereg(priv, 0x0e, 0x80); |
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if (!ret) |
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ret = fc0012_writereg(priv, 0x0e, 0x00); |
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/* VCO Re-Calibration if needed */ |
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if (!ret) |
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ret = fc0012_writereg(priv, 0x0e, 0x00); |
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if (!ret) { |
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msleep(10); |
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ret = fc0012_readreg(priv, 0x0e, &tmp); |
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} |
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if (ret) |
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goto exit; |
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/* vco selection */ |
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tmp &= 0x3f; |
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if (vco_select) { |
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if (tmp > 0x3c) { |
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reg[6] &= ~0x08; |
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ret = fc0012_writereg(priv, 0x06, reg[6]); |
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if (!ret) |
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ret = fc0012_writereg(priv, 0x0e, 0x80); |
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if (!ret) |
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ret = fc0012_writereg(priv, 0x0e, 0x00); |
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} |
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} else { |
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if (tmp < 0x02) { |
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reg[6] |= 0x08; |
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ret = fc0012_writereg(priv, 0x06, reg[6]); |
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if (!ret) |
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ret = fc0012_writereg(priv, 0x0e, 0x80); |
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if (!ret) |
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ret = fc0012_writereg(priv, 0x0e, 0x00); |
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} |
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} |
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priv->frequency = p->frequency; |
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priv->bandwidth = p->bandwidth_hz; |
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exit: |
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if (fe->ops.i2c_gate_ctrl) |
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fe->ops.i2c_gate_ctrl(fe, 0); /* close I2C-gate */ |
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if (ret) |
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dev_warn(&priv->i2c->dev, "%s: %s failed: %d\n", |
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KBUILD_MODNAME, __func__, ret); |
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return ret; |
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} |
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static int fc0012_get_frequency(struct dvb_frontend *fe, u32 *frequency) |
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{ |
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struct fc0012_priv *priv = fe->tuner_priv; |
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*frequency = priv->frequency; |
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return 0; |
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} |
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static int fc0012_get_if_frequency(struct dvb_frontend *fe, u32 *frequency) |
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{ |
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*frequency = 0; /* Zero-IF */ |
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return 0; |
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} |
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static int fc0012_get_bandwidth(struct dvb_frontend *fe, u32 *bandwidth) |
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{ |
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struct fc0012_priv *priv = fe->tuner_priv; |
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*bandwidth = priv->bandwidth; |
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return 0; |
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} |
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#define INPUT_ADC_LEVEL -8 |
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static int fc0012_get_rf_strength(struct dvb_frontend *fe, u16 *strength) |
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{ |
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struct fc0012_priv *priv = fe->tuner_priv; |
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int ret; |
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unsigned char tmp; |
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int int_temp, lna_gain, int_lna, tot_agc_gain, power; |
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static const int fc0012_lna_gain_table[] = { |
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/* low gain */ |
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-63, -58, -99, -73, |
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-63, -65, -54, -60, |
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/* middle gain */ |
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71, 70, 68, 67, |
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65, 63, 61, 58, |
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/* high gain */ |
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197, 191, 188, 186, |
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184, 182, 181, 179, |
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}; |
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if (fe->ops.i2c_gate_ctrl) |
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fe->ops.i2c_gate_ctrl(fe, 1); /* open I2C-gate */ |
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ret = fc0012_writereg(priv, 0x12, 0x00); |
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if (ret) |
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goto err; |
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ret = fc0012_readreg(priv, 0x12, &tmp); |
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if (ret) |
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goto err; |
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int_temp = tmp; |
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ret = fc0012_readreg(priv, 0x13, &tmp); |
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if (ret) |
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goto err; |
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lna_gain = tmp & 0x1f; |
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if (fe->ops.i2c_gate_ctrl) |
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fe->ops.i2c_gate_ctrl(fe, 0); /* close I2C-gate */ |
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if (lna_gain < ARRAY_SIZE(fc0012_lna_gain_table)) { |
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int_lna = fc0012_lna_gain_table[lna_gain]; |
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tot_agc_gain = (abs((int_temp >> 5) - 7) - 2 + |
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(int_temp & 0x1f)) * 2; |
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power = INPUT_ADC_LEVEL - tot_agc_gain - int_lna / 10; |
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if (power >= 45) |
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*strength = 255; /* 100% */ |
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else if (power < -95) |
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*strength = 0; |
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else |
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*strength = (power + 95) * 255 / 140; |
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*strength |= *strength << 8; |
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} else { |
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ret = -1; |
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} |
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goto exit; |
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err: |
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if (fe->ops.i2c_gate_ctrl) |
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fe->ops.i2c_gate_ctrl(fe, 0); /* close I2C-gate */ |
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exit: |
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if (ret) |
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dev_warn(&priv->i2c->dev, "%s: %s failed: %d\n", |
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KBUILD_MODNAME, __func__, ret); |
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return ret; |
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} |
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static const struct dvb_tuner_ops fc0012_tuner_ops = { |
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.info = { |
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.name = "Fitipower FC0012", |
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.frequency_min_hz = 37 * MHz, /* estimate */ |
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.frequency_max_hz = 862 * MHz, /* estimate */ |
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}, |
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.release = fc0012_release, |
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.init = fc0012_init, |
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.set_params = fc0012_set_params, |
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.get_frequency = fc0012_get_frequency, |
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.get_if_frequency = fc0012_get_if_frequency, |
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.get_bandwidth = fc0012_get_bandwidth, |
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.get_rf_strength = fc0012_get_rf_strength, |
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}; |
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struct dvb_frontend *fc0012_attach(struct dvb_frontend *fe, |
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struct i2c_adapter *i2c, const struct fc0012_config *cfg) |
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{ |
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struct fc0012_priv *priv; |
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int ret; |
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u8 chip_id; |
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if (fe->ops.i2c_gate_ctrl) |
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fe->ops.i2c_gate_ctrl(fe, 1); |
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priv = kzalloc(sizeof(struct fc0012_priv), GFP_KERNEL); |
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if (!priv) { |
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ret = -ENOMEM; |
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dev_err(&i2c->dev, "%s: kzalloc() failed\n", KBUILD_MODNAME); |
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goto err; |
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} |
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priv->cfg = cfg; |
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priv->i2c = i2c; |
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/* check if the tuner is there */ |
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ret = fc0012_readreg(priv, 0x00, &chip_id); |
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if (ret < 0) |
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goto err; |
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dev_dbg(&i2c->dev, "%s: chip_id=%02x\n", __func__, chip_id); |
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switch (chip_id) { |
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case 0xa1: |
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break; |
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default: |
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ret = -ENODEV; |
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goto err; |
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} |
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dev_info(&i2c->dev, "%s: Fitipower FC0012 successfully identified\n", |
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KBUILD_MODNAME); |
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if (priv->cfg->loop_through) { |
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ret = fc0012_writereg(priv, 0x09, 0x6f); |
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if (ret < 0) |
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goto err; |
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} |
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/* |
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* TODO: Clock out en or div? |
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* For dual tuner configuration clearing bit [0] is required. |
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*/ |
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if (priv->cfg->clock_out) { |
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ret = fc0012_writereg(priv, 0x0b, 0x82); |
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if (ret < 0) |
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goto err; |
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} |
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fe->tuner_priv = priv; |
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memcpy(&fe->ops.tuner_ops, &fc0012_tuner_ops, |
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sizeof(struct dvb_tuner_ops)); |
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err: |
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if (fe->ops.i2c_gate_ctrl) |
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fe->ops.i2c_gate_ctrl(fe, 0); |
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if (ret) { |
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dev_dbg(&i2c->dev, "%s: failed: %d\n", __func__, ret); |
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kfree(priv); |
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return NULL; |
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} |
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return fe; |
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} |
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EXPORT_SYMBOL(fc0012_attach); |
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MODULE_DESCRIPTION("Fitipower FC0012 silicon tuner driver"); |
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MODULE_AUTHOR("Hans-Frieder Vogt <[email protected]>"); |
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MODULE_LICENSE("GPL"); |
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MODULE_VERSION("0.6");
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