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274 lines
8.7 KiB
274 lines
8.7 KiB
/* SPDX-License-Identifier: GPL-2.0-or-later */ |
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/* |
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* Copyright (c) 2010 Sascha Hauer <[email protected]> |
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* Copyright (C) 2005-2009 Freescale Semiconductor, Inc. |
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*/ |
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#ifndef __IPU_PRV_H__ |
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#define __IPU_PRV_H__ |
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struct ipu_soc; |
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#include <linux/types.h> |
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#include <linux/device.h> |
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#include <linux/clk.h> |
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#include <linux/platform_device.h> |
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#include <video/imx-ipu-v3.h> |
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#define IPU_MCU_T_DEFAULT 8 |
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#define IPU_CM_IDMAC_REG_OFS 0x00008000 |
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#define IPU_CM_IC_REG_OFS 0x00020000 |
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#define IPU_CM_IRT_REG_OFS 0x00028000 |
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#define IPU_CM_CSI0_REG_OFS 0x00030000 |
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#define IPU_CM_CSI1_REG_OFS 0x00038000 |
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#define IPU_CM_SMFC_REG_OFS 0x00050000 |
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#define IPU_CM_DC_REG_OFS 0x00058000 |
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#define IPU_CM_DMFC_REG_OFS 0x00060000 |
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/* Register addresses */ |
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/* IPU Common registers */ |
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#define IPU_CM_REG(offset) (offset) |
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#define IPU_CONF IPU_CM_REG(0) |
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#define IPU_SRM_PRI1 IPU_CM_REG(0x00a0) |
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#define IPU_SRM_PRI2 IPU_CM_REG(0x00a4) |
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#define IPU_FS_PROC_FLOW1 IPU_CM_REG(0x00a8) |
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#define IPU_FS_PROC_FLOW2 IPU_CM_REG(0x00ac) |
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#define IPU_FS_PROC_FLOW3 IPU_CM_REG(0x00b0) |
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#define IPU_FS_DISP_FLOW1 IPU_CM_REG(0x00b4) |
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#define IPU_FS_DISP_FLOW2 IPU_CM_REG(0x00b8) |
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#define IPU_SKIP IPU_CM_REG(0x00bc) |
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#define IPU_DISP_ALT_CONF IPU_CM_REG(0x00c0) |
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#define IPU_DISP_GEN IPU_CM_REG(0x00c4) |
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#define IPU_DISP_ALT1 IPU_CM_REG(0x00c8) |
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#define IPU_DISP_ALT2 IPU_CM_REG(0x00cc) |
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#define IPU_DISP_ALT3 IPU_CM_REG(0x00d0) |
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#define IPU_DISP_ALT4 IPU_CM_REG(0x00d4) |
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#define IPU_SNOOP IPU_CM_REG(0x00d8) |
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#define IPU_MEM_RST IPU_CM_REG(0x00dc) |
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#define IPU_PM IPU_CM_REG(0x00e0) |
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#define IPU_GPR IPU_CM_REG(0x00e4) |
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#define IPU_CHA_DB_MODE_SEL(ch) IPU_CM_REG(0x0150 + 4 * ((ch) / 32)) |
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#define IPU_ALT_CHA_DB_MODE_SEL(ch) IPU_CM_REG(0x0168 + 4 * ((ch) / 32)) |
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#define IPU_CHA_CUR_BUF(ch) IPU_CM_REG(0x023C + 4 * ((ch) / 32)) |
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#define IPU_ALT_CUR_BUF0 IPU_CM_REG(0x0244) |
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#define IPU_ALT_CUR_BUF1 IPU_CM_REG(0x0248) |
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#define IPU_SRM_STAT IPU_CM_REG(0x024C) |
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#define IPU_PROC_TASK_STAT IPU_CM_REG(0x0250) |
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#define IPU_DISP_TASK_STAT IPU_CM_REG(0x0254) |
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#define IPU_CHA_BUF0_RDY(ch) IPU_CM_REG(0x0268 + 4 * ((ch) / 32)) |
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#define IPU_CHA_BUF1_RDY(ch) IPU_CM_REG(0x0270 + 4 * ((ch) / 32)) |
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#define IPU_CHA_BUF2_RDY(ch) IPU_CM_REG(0x0288 + 4 * ((ch) / 32)) |
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#define IPU_ALT_CHA_BUF0_RDY(ch) IPU_CM_REG(0x0278 + 4 * ((ch) / 32)) |
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#define IPU_ALT_CHA_BUF1_RDY(ch) IPU_CM_REG(0x0280 + 4 * ((ch) / 32)) |
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#define IPU_INT_CTRL(n) IPU_CM_REG(0x003C + 4 * (n)) |
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#define IPU_INT_STAT(n) IPU_CM_REG(0x0200 + 4 * (n)) |
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/* SRM_PRI2 */ |
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#define DP_S_SRM_MODE_MASK (0x3 << 3) |
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#define DP_S_SRM_MODE_NOW (0x3 << 3) |
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#define DP_S_SRM_MODE_NEXT_FRAME (0x1 << 3) |
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/* FS_PROC_FLOW1 */ |
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#define FS_PRPENC_ROT_SRC_SEL_MASK (0xf << 0) |
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#define FS_PRPENC_ROT_SRC_SEL_ENC (0x7 << 0) |
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#define FS_PRPVF_ROT_SRC_SEL_MASK (0xf << 8) |
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#define FS_PRPVF_ROT_SRC_SEL_VF (0x8 << 8) |
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#define FS_PP_SRC_SEL_MASK (0xf << 12) |
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#define FS_PP_ROT_SRC_SEL_MASK (0xf << 16) |
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#define FS_PP_ROT_SRC_SEL_PP (0x5 << 16) |
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#define FS_VDI1_SRC_SEL_MASK (0x3 << 20) |
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#define FS_VDI3_SRC_SEL_MASK (0x3 << 20) |
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#define FS_PRP_SRC_SEL_MASK (0xf << 24) |
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#define FS_VDI_SRC_SEL_MASK (0x3 << 28) |
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#define FS_VDI_SRC_SEL_CSI_DIRECT (0x1 << 28) |
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#define FS_VDI_SRC_SEL_VDOA (0x2 << 28) |
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/* FS_PROC_FLOW2 */ |
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#define FS_PRP_ENC_DEST_SEL_MASK (0xf << 0) |
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#define FS_PRP_ENC_DEST_SEL_IRT_ENC (0x1 << 0) |
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#define FS_PRPVF_DEST_SEL_MASK (0xf << 4) |
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#define FS_PRPVF_DEST_SEL_IRT_VF (0x1 << 4) |
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#define FS_PRPVF_ROT_DEST_SEL_MASK (0xf << 8) |
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#define FS_PP_DEST_SEL_MASK (0xf << 12) |
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#define FS_PP_DEST_SEL_IRT_PP (0x3 << 12) |
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#define FS_PP_ROT_DEST_SEL_MASK (0xf << 16) |
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#define FS_PRPENC_ROT_DEST_SEL_MASK (0xf << 20) |
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#define FS_PRP_DEST_SEL_MASK (0xf << 24) |
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#define IPU_DI0_COUNTER_RELEASE (1 << 24) |
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#define IPU_DI1_COUNTER_RELEASE (1 << 25) |
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#define IPU_IDMAC_REG(offset) (offset) |
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#define IDMAC_CONF IPU_IDMAC_REG(0x0000) |
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#define IDMAC_CHA_EN(ch) IPU_IDMAC_REG(0x0004 + 4 * ((ch) / 32)) |
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#define IDMAC_SEP_ALPHA IPU_IDMAC_REG(0x000c) |
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#define IDMAC_ALT_SEP_ALPHA IPU_IDMAC_REG(0x0010) |
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#define IDMAC_CHA_PRI(ch) IPU_IDMAC_REG(0x0014 + 4 * ((ch) / 32)) |
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#define IDMAC_WM_EN(ch) IPU_IDMAC_REG(0x001c + 4 * ((ch) / 32)) |
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#define IDMAC_CH_LOCK_EN_1 IPU_IDMAC_REG(0x0024) |
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#define IDMAC_CH_LOCK_EN_2 IPU_IDMAC_REG(0x0028) |
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#define IDMAC_SUB_ADDR_0 IPU_IDMAC_REG(0x002c) |
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#define IDMAC_SUB_ADDR_1 IPU_IDMAC_REG(0x0030) |
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#define IDMAC_SUB_ADDR_2 IPU_IDMAC_REG(0x0034) |
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#define IDMAC_BAND_EN(ch) IPU_IDMAC_REG(0x0040 + 4 * ((ch) / 32)) |
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#define IDMAC_CHA_BUSY(ch) IPU_IDMAC_REG(0x0100 + 4 * ((ch) / 32)) |
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#define IPU_NUM_IRQS (32 * 15) |
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enum ipu_modules { |
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IPU_CONF_CSI0_EN = (1 << 0), |
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IPU_CONF_CSI1_EN = (1 << 1), |
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IPU_CONF_IC_EN = (1 << 2), |
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IPU_CONF_ROT_EN = (1 << 3), |
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IPU_CONF_ISP_EN = (1 << 4), |
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IPU_CONF_DP_EN = (1 << 5), |
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IPU_CONF_DI0_EN = (1 << 6), |
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IPU_CONF_DI1_EN = (1 << 7), |
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IPU_CONF_SMFC_EN = (1 << 8), |
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IPU_CONF_DC_EN = (1 << 9), |
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IPU_CONF_DMFC_EN = (1 << 10), |
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IPU_CONF_VDI_EN = (1 << 12), |
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IPU_CONF_IDMAC_DIS = (1 << 22), |
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IPU_CONF_IC_DMFC_SEL = (1 << 25), |
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IPU_CONF_IC_DMFC_SYNC = (1 << 26), |
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IPU_CONF_VDI_DMFC_SYNC = (1 << 27), |
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IPU_CONF_CSI0_DATA_SOURCE = (1 << 28), |
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IPU_CONF_CSI1_DATA_SOURCE = (1 << 29), |
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IPU_CONF_IC_INPUT = (1 << 30), |
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IPU_CONF_CSI_SEL = (1 << 31), |
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}; |
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struct ipuv3_channel { |
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unsigned int num; |
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struct ipu_soc *ipu; |
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struct list_head list; |
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}; |
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struct ipu_cpmem; |
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struct ipu_csi; |
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struct ipu_dc_priv; |
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struct ipu_dmfc_priv; |
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struct ipu_di; |
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struct ipu_ic_priv; |
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struct ipu_vdi; |
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struct ipu_image_convert_priv; |
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struct ipu_smfc_priv; |
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struct ipu_pre; |
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struct ipu_prg; |
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struct ipu_devtype; |
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struct ipu_soc { |
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struct device *dev; |
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const struct ipu_devtype *devtype; |
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enum ipuv3_type ipu_type; |
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spinlock_t lock; |
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struct mutex channel_lock; |
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struct list_head channels; |
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void __iomem *cm_reg; |
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void __iomem *idmac_reg; |
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int id; |
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int usecount; |
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struct clk *clk; |
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int irq_sync; |
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int irq_err; |
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struct irq_domain *domain; |
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struct ipu_cpmem *cpmem_priv; |
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struct ipu_dc_priv *dc_priv; |
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struct ipu_dp_priv *dp_priv; |
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struct ipu_dmfc_priv *dmfc_priv; |
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struct ipu_di *di_priv[2]; |
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struct ipu_csi *csi_priv[2]; |
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struct ipu_ic_priv *ic_priv; |
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struct ipu_vdi *vdi_priv; |
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struct ipu_image_convert_priv *image_convert_priv; |
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struct ipu_smfc_priv *smfc_priv; |
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struct ipu_prg *prg_priv; |
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}; |
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static inline u32 ipu_idmac_read(struct ipu_soc *ipu, unsigned offset) |
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{ |
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return readl(ipu->idmac_reg + offset); |
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} |
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static inline void ipu_idmac_write(struct ipu_soc *ipu, u32 value, |
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unsigned offset) |
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{ |
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writel(value, ipu->idmac_reg + offset); |
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} |
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void ipu_srm_dp_update(struct ipu_soc *ipu, bool sync); |
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int ipu_module_enable(struct ipu_soc *ipu, u32 mask); |
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int ipu_module_disable(struct ipu_soc *ipu, u32 mask); |
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bool ipu_idmac_channel_busy(struct ipu_soc *ipu, unsigned int chno); |
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int ipu_csi_init(struct ipu_soc *ipu, struct device *dev, int id, |
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unsigned long base, u32 module, struct clk *clk_ipu); |
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void ipu_csi_exit(struct ipu_soc *ipu, int id); |
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int ipu_ic_init(struct ipu_soc *ipu, struct device *dev, |
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unsigned long base, unsigned long tpmem_base); |
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void ipu_ic_exit(struct ipu_soc *ipu); |
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int ipu_vdi_init(struct ipu_soc *ipu, struct device *dev, |
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unsigned long base, u32 module); |
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void ipu_vdi_exit(struct ipu_soc *ipu); |
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int ipu_image_convert_init(struct ipu_soc *ipu, struct device *dev); |
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void ipu_image_convert_exit(struct ipu_soc *ipu); |
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int ipu_di_init(struct ipu_soc *ipu, struct device *dev, int id, |
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unsigned long base, u32 module, struct clk *ipu_clk); |
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void ipu_di_exit(struct ipu_soc *ipu, int id); |
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int ipu_dmfc_init(struct ipu_soc *ipu, struct device *dev, unsigned long base, |
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struct clk *ipu_clk); |
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void ipu_dmfc_exit(struct ipu_soc *ipu); |
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int ipu_dp_init(struct ipu_soc *ipu, struct device *dev, unsigned long base); |
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void ipu_dp_exit(struct ipu_soc *ipu); |
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int ipu_dc_init(struct ipu_soc *ipu, struct device *dev, unsigned long base, |
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unsigned long template_base); |
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void ipu_dc_exit(struct ipu_soc *ipu); |
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int ipu_cpmem_init(struct ipu_soc *ipu, struct device *dev, unsigned long base); |
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void ipu_cpmem_exit(struct ipu_soc *ipu); |
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int ipu_smfc_init(struct ipu_soc *ipu, struct device *dev, unsigned long base); |
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void ipu_smfc_exit(struct ipu_soc *ipu); |
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struct ipu_pre *ipu_pre_lookup_by_phandle(struct device *dev, const char *name, |
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int index); |
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int ipu_pre_get_available_count(void); |
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int ipu_pre_get(struct ipu_pre *pre); |
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void ipu_pre_put(struct ipu_pre *pre); |
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u32 ipu_pre_get_baddr(struct ipu_pre *pre); |
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void ipu_pre_configure(struct ipu_pre *pre, unsigned int width, |
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unsigned int height, unsigned int stride, u32 format, |
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uint64_t modifier, unsigned int bufaddr); |
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void ipu_pre_update(struct ipu_pre *pre, unsigned int bufaddr); |
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bool ipu_pre_update_pending(struct ipu_pre *pre); |
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struct ipu_prg *ipu_prg_lookup_by_phandle(struct device *dev, const char *name, |
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int ipu_id); |
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extern struct platform_driver ipu_pre_drv; |
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extern struct platform_driver ipu_prg_drv; |
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#endif /* __IPU_PRV_H__ */
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