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267 lines
7.2 KiB
267 lines
7.2 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* Copyright (c) 2022 MediaTek Inc. |
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* Author: Jianjun Wang <[email protected]> |
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*/ |
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#include <linux/bitfield.h> |
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#include <linux/module.h> |
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#include <linux/nvmem-consumer.h> |
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#include <linux/of_device.h> |
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#include <linux/phy/phy.h> |
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#include <linux/platform_device.h> |
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#include <linux/slab.h> |
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#include "phy-mtk-io.h" |
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#define PEXTP_ANA_GLB_00_REG 0x9000 |
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/* Internal Resistor Selection of TX Bias Current */ |
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#define EFUSE_GLB_INTR_SEL GENMASK(28, 24) |
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#define PEXTP_ANA_LN0_TRX_REG 0xa000 |
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#define PEXTP_ANA_TX_REG 0x04 |
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/* TX PMOS impedance selection */ |
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#define EFUSE_LN_TX_PMOS_SEL GENMASK(5, 2) |
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/* TX NMOS impedance selection */ |
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#define EFUSE_LN_TX_NMOS_SEL GENMASK(11, 8) |
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#define PEXTP_ANA_RX_REG 0x3c |
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/* RX impedance selection */ |
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#define EFUSE_LN_RX_SEL GENMASK(3, 0) |
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#define PEXTP_ANA_LANE_OFFSET 0x100 |
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/** |
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* struct mtk_pcie_lane_efuse - eFuse data for each lane |
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* @tx_pmos: TX PMOS impedance selection data |
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* @tx_nmos: TX NMOS impedance selection data |
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* @rx_data: RX impedance selection data |
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* @lane_efuse_supported: software eFuse data is supported for this lane |
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*/ |
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struct mtk_pcie_lane_efuse { |
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u32 tx_pmos; |
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u32 tx_nmos; |
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u32 rx_data; |
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bool lane_efuse_supported; |
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}; |
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/** |
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* struct mtk_pcie_phy_data - phy data for each SoC |
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* @num_lanes: supported lane numbers |
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* @sw_efuse_supported: support software to load eFuse data |
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*/ |
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struct mtk_pcie_phy_data { |
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int num_lanes; |
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bool sw_efuse_supported; |
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}; |
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/** |
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* struct mtk_pcie_phy - PCIe phy driver main structure |
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* @dev: pointer to device |
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* @phy: pointer to generic phy |
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* @sif_base: IO mapped register base address of system interface |
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* @data: pointer to SoC dependent data |
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* @sw_efuse_en: software eFuse enable status |
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* @efuse_glb_intr: internal resistor selection of TX bias current data |
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* @efuse: pointer to eFuse data for each lane |
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*/ |
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struct mtk_pcie_phy { |
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struct device *dev; |
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struct phy *phy; |
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void __iomem *sif_base; |
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const struct mtk_pcie_phy_data *data; |
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bool sw_efuse_en; |
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u32 efuse_glb_intr; |
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struct mtk_pcie_lane_efuse *efuse; |
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}; |
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static void mtk_pcie_efuse_set_lane(struct mtk_pcie_phy *pcie_phy, |
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unsigned int lane) |
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{ |
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struct mtk_pcie_lane_efuse *data = &pcie_phy->efuse[lane]; |
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void __iomem *addr; |
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if (!data->lane_efuse_supported) |
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return; |
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addr = pcie_phy->sif_base + PEXTP_ANA_LN0_TRX_REG + |
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lane * PEXTP_ANA_LANE_OFFSET; |
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mtk_phy_update_bits(addr + PEXTP_ANA_TX_REG, EFUSE_LN_TX_PMOS_SEL, |
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FIELD_PREP(EFUSE_LN_TX_PMOS_SEL, data->tx_pmos)); |
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mtk_phy_update_bits(addr + PEXTP_ANA_TX_REG, EFUSE_LN_TX_NMOS_SEL, |
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FIELD_PREP(EFUSE_LN_TX_NMOS_SEL, data->tx_nmos)); |
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mtk_phy_update_bits(addr + PEXTP_ANA_RX_REG, EFUSE_LN_RX_SEL, |
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FIELD_PREP(EFUSE_LN_RX_SEL, data->rx_data)); |
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} |
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/** |
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* mtk_pcie_phy_init() - Initialize the phy |
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* @phy: the phy to be initialized |
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* |
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* Initialize the phy by setting the efuse data. |
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* The hardware settings will be reset during suspend, it should be |
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* reinitialized when the consumer calls phy_init() again on resume. |
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*/ |
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static int mtk_pcie_phy_init(struct phy *phy) |
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{ |
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struct mtk_pcie_phy *pcie_phy = phy_get_drvdata(phy); |
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int i; |
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if (!pcie_phy->sw_efuse_en) |
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return 0; |
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/* Set global data */ |
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mtk_phy_update_bits(pcie_phy->sif_base + PEXTP_ANA_GLB_00_REG, |
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EFUSE_GLB_INTR_SEL, |
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FIELD_PREP(EFUSE_GLB_INTR_SEL, pcie_phy->efuse_glb_intr)); |
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for (i = 0; i < pcie_phy->data->num_lanes; i++) |
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mtk_pcie_efuse_set_lane(pcie_phy, i); |
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return 0; |
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} |
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static const struct phy_ops mtk_pcie_phy_ops = { |
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.init = mtk_pcie_phy_init, |
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.owner = THIS_MODULE, |
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}; |
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static int mtk_pcie_efuse_read_for_lane(struct mtk_pcie_phy *pcie_phy, |
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unsigned int lane) |
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{ |
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struct mtk_pcie_lane_efuse *efuse = &pcie_phy->efuse[lane]; |
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struct device *dev = pcie_phy->dev; |
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char efuse_id[16]; |
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int ret; |
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snprintf(efuse_id, sizeof(efuse_id), "tx_ln%d_pmos", lane); |
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ret = nvmem_cell_read_variable_le_u32(dev, efuse_id, &efuse->tx_pmos); |
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if (ret) |
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return dev_err_probe(dev, ret, "Failed to read %s\n", efuse_id); |
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snprintf(efuse_id, sizeof(efuse_id), "tx_ln%d_nmos", lane); |
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ret = nvmem_cell_read_variable_le_u32(dev, efuse_id, &efuse->tx_nmos); |
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if (ret) |
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return dev_err_probe(dev, ret, "Failed to read %s\n", efuse_id); |
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snprintf(efuse_id, sizeof(efuse_id), "rx_ln%d", lane); |
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ret = nvmem_cell_read_variable_le_u32(dev, efuse_id, &efuse->rx_data); |
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if (ret) |
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return dev_err_probe(dev, ret, "Failed to read %s\n", efuse_id); |
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if (!(efuse->tx_pmos || efuse->tx_nmos || efuse->rx_data)) |
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return dev_err_probe(dev, -EINVAL, |
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"No eFuse data found for lane%d, but dts enable it\n", |
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lane); |
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efuse->lane_efuse_supported = true; |
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return 0; |
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} |
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static int mtk_pcie_read_efuse(struct mtk_pcie_phy *pcie_phy) |
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{ |
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struct device *dev = pcie_phy->dev; |
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bool nvmem_enabled; |
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int ret, i; |
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/* nvmem data is optional */ |
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nvmem_enabled = device_property_present(dev, "nvmem-cells"); |
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if (!nvmem_enabled) |
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return 0; |
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ret = nvmem_cell_read_variable_le_u32(dev, "glb_intr", |
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&pcie_phy->efuse_glb_intr); |
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if (ret) |
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return dev_err_probe(dev, ret, "Failed to read glb_intr\n"); |
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pcie_phy->sw_efuse_en = true; |
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pcie_phy->efuse = devm_kzalloc(dev, pcie_phy->data->num_lanes * |
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sizeof(*pcie_phy->efuse), GFP_KERNEL); |
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if (!pcie_phy->efuse) |
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return -ENOMEM; |
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for (i = 0; i < pcie_phy->data->num_lanes; i++) { |
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ret = mtk_pcie_efuse_read_for_lane(pcie_phy, i); |
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if (ret) |
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return ret; |
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} |
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return 0; |
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} |
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static int mtk_pcie_phy_probe(struct platform_device *pdev) |
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{ |
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struct device *dev = &pdev->dev; |
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struct phy_provider *provider; |
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struct mtk_pcie_phy *pcie_phy; |
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int ret; |
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pcie_phy = devm_kzalloc(dev, sizeof(*pcie_phy), GFP_KERNEL); |
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if (!pcie_phy) |
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return -ENOMEM; |
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pcie_phy->sif_base = devm_platform_ioremap_resource_byname(pdev, "sif"); |
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if (IS_ERR(pcie_phy->sif_base)) |
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return dev_err_probe(dev, PTR_ERR(pcie_phy->sif_base), |
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"Failed to map phy-sif base\n"); |
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pcie_phy->phy = devm_phy_create(dev, dev->of_node, &mtk_pcie_phy_ops); |
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if (IS_ERR(pcie_phy->phy)) |
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return dev_err_probe(dev, PTR_ERR(pcie_phy->phy), |
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"Failed to create PCIe phy\n"); |
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pcie_phy->dev = dev; |
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pcie_phy->data = of_device_get_match_data(dev); |
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if (!pcie_phy->data) |
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return dev_err_probe(dev, -EINVAL, "Failed to get phy data\n"); |
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if (pcie_phy->data->sw_efuse_supported) { |
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/* |
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* Failed to read the efuse data is not a fatal problem, |
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* ignore the failure and keep going. |
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*/ |
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ret = mtk_pcie_read_efuse(pcie_phy); |
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if (ret == -EPROBE_DEFER || ret == -ENOMEM) |
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return ret; |
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} |
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phy_set_drvdata(pcie_phy->phy, pcie_phy); |
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provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); |
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if (IS_ERR(provider)) |
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return dev_err_probe(dev, PTR_ERR(provider), |
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"PCIe phy probe failed\n"); |
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return 0; |
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} |
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static const struct mtk_pcie_phy_data mt8195_data = { |
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.num_lanes = 2, |
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.sw_efuse_supported = true, |
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}; |
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static const struct of_device_id mtk_pcie_phy_of_match[] = { |
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{ .compatible = "mediatek,mt8195-pcie-phy", .data = &mt8195_data }, |
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{ }, |
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}; |
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MODULE_DEVICE_TABLE(of, mtk_pcie_phy_of_match); |
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static struct platform_driver mtk_pcie_phy_driver = { |
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.probe = mtk_pcie_phy_probe, |
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.driver = { |
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.name = "mtk-pcie-phy", |
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.of_match_table = mtk_pcie_phy_of_match, |
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}, |
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}; |
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module_platform_driver(mtk_pcie_phy_driver); |
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MODULE_DESCRIPTION("MediaTek PCIe PHY driver"); |
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MODULE_AUTHOR("Jianjun Wang <[email protected]>"); |
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MODULE_LICENSE("GPL");
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