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566 lines
13 KiB
566 lines
13 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* pci-j721e - PCIe controller driver for TI's J721E SoCs |
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* |
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* Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com |
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* Author: Kishon Vijay Abraham I <[email protected]> |
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*/ |
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|
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#include <linux/clk.h> |
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#include <linux/delay.h> |
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#include <linux/gpio/consumer.h> |
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#include <linux/io.h> |
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#include <linux/irqchip/chained_irq.h> |
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#include <linux/irqdomain.h> |
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#include <linux/mfd/syscon.h> |
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#include <linux/of.h> |
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#include <linux/of_device.h> |
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#include <linux/of_irq.h> |
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#include <linux/pci.h> |
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#include <linux/pm_runtime.h> |
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#include <linux/regmap.h> |
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|
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#include "../../pci.h" |
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#include "pcie-cadence.h" |
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|
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#define ENABLE_REG_SYS_2 0x108 |
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#define STATUS_REG_SYS_2 0x508 |
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#define STATUS_CLR_REG_SYS_2 0x708 |
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#define LINK_DOWN BIT(1) |
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#define J7200_LINK_DOWN BIT(10) |
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|
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#define J721E_PCIE_USER_CMD_STATUS 0x4 |
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#define LINK_TRAINING_ENABLE BIT(0) |
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#define J721E_PCIE_USER_LINKSTATUS 0x14 |
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#define LINK_STATUS GENMASK(1, 0) |
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|
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enum link_status { |
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NO_RECEIVERS_DETECTED, |
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LINK_TRAINING_IN_PROGRESS, |
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LINK_UP_DL_IN_PROGRESS, |
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LINK_UP_DL_COMPLETED, |
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}; |
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|
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#define J721E_MODE_RC BIT(7) |
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#define LANE_COUNT_MASK BIT(8) |
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#define LANE_COUNT(n) ((n) << 8) |
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|
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#define GENERATION_SEL_MASK GENMASK(1, 0) |
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|
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#define MAX_LANES 2 |
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struct j721e_pcie { |
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struct cdns_pcie *cdns_pcie; |
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struct clk *refclk; |
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u32 mode; |
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u32 num_lanes; |
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void __iomem *user_cfg_base; |
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void __iomem *intd_cfg_base; |
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u32 linkdown_irq_regfield; |
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}; |
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|
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enum j721e_pcie_mode { |
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PCI_MODE_RC, |
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PCI_MODE_EP, |
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}; |
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struct j721e_pcie_data { |
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enum j721e_pcie_mode mode; |
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unsigned int quirk_retrain_flag:1; |
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unsigned int quirk_detect_quiet_flag:1; |
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u32 linkdown_irq_regfield; |
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unsigned int byte_access_allowed:1; |
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}; |
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|
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static inline u32 j721e_pcie_user_readl(struct j721e_pcie *pcie, u32 offset) |
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{ |
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return readl(pcie->user_cfg_base + offset); |
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} |
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static inline void j721e_pcie_user_writel(struct j721e_pcie *pcie, u32 offset, |
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u32 value) |
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{ |
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writel(value, pcie->user_cfg_base + offset); |
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} |
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|
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static inline u32 j721e_pcie_intd_readl(struct j721e_pcie *pcie, u32 offset) |
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{ |
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return readl(pcie->intd_cfg_base + offset); |
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} |
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static inline void j721e_pcie_intd_writel(struct j721e_pcie *pcie, u32 offset, |
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u32 value) |
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{ |
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writel(value, pcie->intd_cfg_base + offset); |
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} |
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static irqreturn_t j721e_pcie_link_irq_handler(int irq, void *priv) |
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{ |
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struct j721e_pcie *pcie = priv; |
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struct device *dev = pcie->cdns_pcie->dev; |
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u32 reg; |
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reg = j721e_pcie_intd_readl(pcie, STATUS_REG_SYS_2); |
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if (!(reg & pcie->linkdown_irq_regfield)) |
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return IRQ_NONE; |
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|
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dev_err(dev, "LINK DOWN!\n"); |
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j721e_pcie_intd_writel(pcie, STATUS_CLR_REG_SYS_2, pcie->linkdown_irq_regfield); |
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return IRQ_HANDLED; |
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} |
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static void j721e_pcie_config_link_irq(struct j721e_pcie *pcie) |
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{ |
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u32 reg; |
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reg = j721e_pcie_intd_readl(pcie, ENABLE_REG_SYS_2); |
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reg |= pcie->linkdown_irq_regfield; |
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j721e_pcie_intd_writel(pcie, ENABLE_REG_SYS_2, reg); |
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} |
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static int j721e_pcie_start_link(struct cdns_pcie *cdns_pcie) |
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{ |
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struct j721e_pcie *pcie = dev_get_drvdata(cdns_pcie->dev); |
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u32 reg; |
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reg = j721e_pcie_user_readl(pcie, J721E_PCIE_USER_CMD_STATUS); |
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reg |= LINK_TRAINING_ENABLE; |
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j721e_pcie_user_writel(pcie, J721E_PCIE_USER_CMD_STATUS, reg); |
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|
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return 0; |
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} |
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static void j721e_pcie_stop_link(struct cdns_pcie *cdns_pcie) |
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{ |
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struct j721e_pcie *pcie = dev_get_drvdata(cdns_pcie->dev); |
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u32 reg; |
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reg = j721e_pcie_user_readl(pcie, J721E_PCIE_USER_CMD_STATUS); |
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reg &= ~LINK_TRAINING_ENABLE; |
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j721e_pcie_user_writel(pcie, J721E_PCIE_USER_CMD_STATUS, reg); |
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} |
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static bool j721e_pcie_link_up(struct cdns_pcie *cdns_pcie) |
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{ |
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struct j721e_pcie *pcie = dev_get_drvdata(cdns_pcie->dev); |
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u32 reg; |
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|
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reg = j721e_pcie_user_readl(pcie, J721E_PCIE_USER_LINKSTATUS); |
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reg &= LINK_STATUS; |
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if (reg == LINK_UP_DL_COMPLETED) |
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return true; |
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|
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return false; |
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} |
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|
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static const struct cdns_pcie_ops j721e_pcie_ops = { |
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.start_link = j721e_pcie_start_link, |
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.stop_link = j721e_pcie_stop_link, |
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.link_up = j721e_pcie_link_up, |
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}; |
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|
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static int j721e_pcie_set_mode(struct j721e_pcie *pcie, struct regmap *syscon, |
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unsigned int offset) |
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{ |
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struct device *dev = pcie->cdns_pcie->dev; |
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u32 mask = J721E_MODE_RC; |
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u32 mode = pcie->mode; |
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u32 val = 0; |
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int ret = 0; |
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|
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if (mode == PCI_MODE_RC) |
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val = J721E_MODE_RC; |
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|
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ret = regmap_update_bits(syscon, offset, mask, val); |
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if (ret) |
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dev_err(dev, "failed to set pcie mode\n"); |
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|
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return ret; |
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} |
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static int j721e_pcie_set_link_speed(struct j721e_pcie *pcie, |
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struct regmap *syscon, unsigned int offset) |
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{ |
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struct device *dev = pcie->cdns_pcie->dev; |
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struct device_node *np = dev->of_node; |
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int link_speed; |
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u32 val = 0; |
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int ret; |
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link_speed = of_pci_get_max_link_speed(np); |
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if (link_speed < 2) |
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link_speed = 2; |
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|
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val = link_speed - 1; |
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ret = regmap_update_bits(syscon, offset, GENERATION_SEL_MASK, val); |
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if (ret) |
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dev_err(dev, "failed to set link speed\n"); |
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return ret; |
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} |
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static int j721e_pcie_set_lane_count(struct j721e_pcie *pcie, |
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struct regmap *syscon, unsigned int offset) |
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{ |
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struct device *dev = pcie->cdns_pcie->dev; |
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u32 lanes = pcie->num_lanes; |
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u32 val = 0; |
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int ret; |
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|
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val = LANE_COUNT(lanes - 1); |
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ret = regmap_update_bits(syscon, offset, LANE_COUNT_MASK, val); |
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if (ret) |
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dev_err(dev, "failed to set link count\n"); |
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|
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return ret; |
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} |
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static int j721e_pcie_ctrl_init(struct j721e_pcie *pcie) |
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{ |
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struct device *dev = pcie->cdns_pcie->dev; |
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struct device_node *node = dev->of_node; |
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struct of_phandle_args args; |
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unsigned int offset = 0; |
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struct regmap *syscon; |
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int ret; |
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|
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syscon = syscon_regmap_lookup_by_phandle(node, "ti,syscon-pcie-ctrl"); |
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if (IS_ERR(syscon)) { |
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dev_err(dev, "Unable to get ti,syscon-pcie-ctrl regmap\n"); |
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return PTR_ERR(syscon); |
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} |
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|
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/* Do not error out to maintain old DT compatibility */ |
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ret = of_parse_phandle_with_fixed_args(node, "ti,syscon-pcie-ctrl", 1, |
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0, &args); |
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if (!ret) |
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offset = args.args[0]; |
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|
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ret = j721e_pcie_set_mode(pcie, syscon, offset); |
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if (ret < 0) { |
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dev_err(dev, "Failed to set pci mode\n"); |
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return ret; |
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} |
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ret = j721e_pcie_set_link_speed(pcie, syscon, offset); |
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if (ret < 0) { |
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dev_err(dev, "Failed to set link speed\n"); |
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return ret; |
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} |
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ret = j721e_pcie_set_lane_count(pcie, syscon, offset); |
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if (ret < 0) { |
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dev_err(dev, "Failed to set num-lanes\n"); |
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return ret; |
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} |
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return 0; |
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} |
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static int cdns_ti_pcie_config_read(struct pci_bus *bus, unsigned int devfn, |
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int where, int size, u32 *value) |
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{ |
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if (pci_is_root_bus(bus)) |
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return pci_generic_config_read32(bus, devfn, where, size, |
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value); |
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|
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return pci_generic_config_read(bus, devfn, where, size, value); |
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} |
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static int cdns_ti_pcie_config_write(struct pci_bus *bus, unsigned int devfn, |
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int where, int size, u32 value) |
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{ |
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if (pci_is_root_bus(bus)) |
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return pci_generic_config_write32(bus, devfn, where, size, |
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value); |
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return pci_generic_config_write(bus, devfn, where, size, value); |
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} |
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static struct pci_ops cdns_ti_pcie_host_ops = { |
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.map_bus = cdns_pci_map_bus, |
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.read = cdns_ti_pcie_config_read, |
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.write = cdns_ti_pcie_config_write, |
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}; |
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|
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static const struct j721e_pcie_data j721e_pcie_rc_data = { |
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.mode = PCI_MODE_RC, |
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.quirk_retrain_flag = true, |
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.byte_access_allowed = false, |
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.linkdown_irq_regfield = LINK_DOWN, |
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}; |
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static const struct j721e_pcie_data j721e_pcie_ep_data = { |
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.mode = PCI_MODE_EP, |
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.linkdown_irq_regfield = LINK_DOWN, |
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}; |
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|
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static const struct j721e_pcie_data j7200_pcie_rc_data = { |
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.mode = PCI_MODE_RC, |
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.quirk_detect_quiet_flag = true, |
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.linkdown_irq_regfield = J7200_LINK_DOWN, |
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.byte_access_allowed = true, |
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}; |
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|
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static const struct j721e_pcie_data j7200_pcie_ep_data = { |
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.mode = PCI_MODE_EP, |
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.quirk_detect_quiet_flag = true, |
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}; |
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|
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static const struct j721e_pcie_data am64_pcie_rc_data = { |
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.mode = PCI_MODE_RC, |
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.linkdown_irq_regfield = J7200_LINK_DOWN, |
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.byte_access_allowed = true, |
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}; |
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|
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static const struct j721e_pcie_data am64_pcie_ep_data = { |
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.mode = PCI_MODE_EP, |
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.linkdown_irq_regfield = J7200_LINK_DOWN, |
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}; |
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|
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static const struct of_device_id of_j721e_pcie_match[] = { |
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{ |
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.compatible = "ti,j721e-pcie-host", |
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.data = &j721e_pcie_rc_data, |
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}, |
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{ |
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.compatible = "ti,j721e-pcie-ep", |
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.data = &j721e_pcie_ep_data, |
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}, |
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{ |
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.compatible = "ti,j7200-pcie-host", |
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.data = &j7200_pcie_rc_data, |
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}, |
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{ |
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.compatible = "ti,j7200-pcie-ep", |
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.data = &j7200_pcie_ep_data, |
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}, |
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{ |
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.compatible = "ti,am64-pcie-host", |
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.data = &am64_pcie_rc_data, |
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}, |
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{ |
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.compatible = "ti,am64-pcie-ep", |
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.data = &am64_pcie_ep_data, |
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}, |
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{}, |
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}; |
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|
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static int j721e_pcie_probe(struct platform_device *pdev) |
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{ |
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struct device *dev = &pdev->dev; |
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struct device_node *node = dev->of_node; |
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struct pci_host_bridge *bridge; |
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const struct j721e_pcie_data *data; |
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struct cdns_pcie *cdns_pcie; |
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struct j721e_pcie *pcie; |
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struct cdns_pcie_rc *rc = NULL; |
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struct cdns_pcie_ep *ep = NULL; |
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struct gpio_desc *gpiod; |
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void __iomem *base; |
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struct clk *clk; |
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u32 num_lanes; |
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u32 mode; |
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int ret; |
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int irq; |
|
|
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data = of_device_get_match_data(dev); |
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if (!data) |
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return -EINVAL; |
|
|
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mode = (u32)data->mode; |
|
|
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pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL); |
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if (!pcie) |
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return -ENOMEM; |
|
|
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switch (mode) { |
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case PCI_MODE_RC: |
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if (!IS_ENABLED(CONFIG_PCIE_CADENCE_HOST)) |
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return -ENODEV; |
|
|
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bridge = devm_pci_alloc_host_bridge(dev, sizeof(*rc)); |
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if (!bridge) |
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return -ENOMEM; |
|
|
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if (!data->byte_access_allowed) |
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bridge->ops = &cdns_ti_pcie_host_ops; |
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rc = pci_host_bridge_priv(bridge); |
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rc->quirk_retrain_flag = data->quirk_retrain_flag; |
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rc->quirk_detect_quiet_flag = data->quirk_detect_quiet_flag; |
|
|
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cdns_pcie = &rc->pcie; |
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cdns_pcie->dev = dev; |
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cdns_pcie->ops = &j721e_pcie_ops; |
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pcie->cdns_pcie = cdns_pcie; |
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break; |
|
case PCI_MODE_EP: |
|
if (!IS_ENABLED(CONFIG_PCIE_CADENCE_EP)) |
|
return -ENODEV; |
|
|
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ep = devm_kzalloc(dev, sizeof(*ep), GFP_KERNEL); |
|
if (!ep) |
|
return -ENOMEM; |
|
|
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ep->quirk_detect_quiet_flag = data->quirk_detect_quiet_flag; |
|
|
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cdns_pcie = &ep->pcie; |
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cdns_pcie->dev = dev; |
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cdns_pcie->ops = &j721e_pcie_ops; |
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pcie->cdns_pcie = cdns_pcie; |
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break; |
|
default: |
|
dev_err(dev, "INVALID device type %d\n", mode); |
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return 0; |
|
} |
|
|
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pcie->mode = mode; |
|
pcie->linkdown_irq_regfield = data->linkdown_irq_regfield; |
|
|
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base = devm_platform_ioremap_resource_byname(pdev, "intd_cfg"); |
|
if (IS_ERR(base)) |
|
return PTR_ERR(base); |
|
pcie->intd_cfg_base = base; |
|
|
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base = devm_platform_ioremap_resource_byname(pdev, "user_cfg"); |
|
if (IS_ERR(base)) |
|
return PTR_ERR(base); |
|
pcie->user_cfg_base = base; |
|
|
|
ret = of_property_read_u32(node, "num-lanes", &num_lanes); |
|
if (ret || num_lanes > MAX_LANES) |
|
num_lanes = 1; |
|
pcie->num_lanes = num_lanes; |
|
|
|
if (dma_set_mask_and_coherent(dev, DMA_BIT_MASK(48))) |
|
return -EINVAL; |
|
|
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irq = platform_get_irq_byname(pdev, "link_state"); |
|
if (irq < 0) |
|
return irq; |
|
|
|
dev_set_drvdata(dev, pcie); |
|
pm_runtime_enable(dev); |
|
ret = pm_runtime_get_sync(dev); |
|
if (ret < 0) { |
|
dev_err(dev, "pm_runtime_get_sync failed\n"); |
|
goto err_get_sync; |
|
} |
|
|
|
ret = j721e_pcie_ctrl_init(pcie); |
|
if (ret < 0) { |
|
dev_err(dev, "pm_runtime_get_sync failed\n"); |
|
goto err_get_sync; |
|
} |
|
|
|
ret = devm_request_irq(dev, irq, j721e_pcie_link_irq_handler, 0, |
|
"j721e-pcie-link-down-irq", pcie); |
|
if (ret < 0) { |
|
dev_err(dev, "failed to request link state IRQ %d\n", irq); |
|
goto err_get_sync; |
|
} |
|
|
|
j721e_pcie_config_link_irq(pcie); |
|
|
|
switch (mode) { |
|
case PCI_MODE_RC: |
|
gpiod = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW); |
|
if (IS_ERR(gpiod)) { |
|
ret = PTR_ERR(gpiod); |
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if (ret != -EPROBE_DEFER) |
|
dev_err(dev, "Failed to get reset GPIO\n"); |
|
goto err_get_sync; |
|
} |
|
|
|
ret = cdns_pcie_init_phy(dev, cdns_pcie); |
|
if (ret) { |
|
dev_err(dev, "Failed to init phy\n"); |
|
goto err_get_sync; |
|
} |
|
|
|
clk = devm_clk_get_optional(dev, "pcie_refclk"); |
|
if (IS_ERR(clk)) { |
|
ret = PTR_ERR(clk); |
|
dev_err(dev, "failed to get pcie_refclk\n"); |
|
goto err_pcie_setup; |
|
} |
|
|
|
ret = clk_prepare_enable(clk); |
|
if (ret) { |
|
dev_err(dev, "failed to enable pcie_refclk\n"); |
|
goto err_pcie_setup; |
|
} |
|
pcie->refclk = clk; |
|
|
|
/* |
|
* "Power Sequencing and Reset Signal Timings" table in |
|
* PCI EXPRESS CARD ELECTROMECHANICAL SPECIFICATION, REV. 3.0 |
|
* indicates PERST# should be deasserted after minimum of 100us |
|
* once REFCLK is stable. The REFCLK to the connector in RC |
|
* mode is selected while enabling the PHY. So deassert PERST# |
|
* after 100 us. |
|
*/ |
|
if (gpiod) { |
|
usleep_range(100, 200); |
|
gpiod_set_value_cansleep(gpiod, 1); |
|
} |
|
|
|
ret = cdns_pcie_host_setup(rc); |
|
if (ret < 0) { |
|
clk_disable_unprepare(pcie->refclk); |
|
goto err_pcie_setup; |
|
} |
|
|
|
break; |
|
case PCI_MODE_EP: |
|
ret = cdns_pcie_init_phy(dev, cdns_pcie); |
|
if (ret) { |
|
dev_err(dev, "Failed to init phy\n"); |
|
goto err_get_sync; |
|
} |
|
|
|
ret = cdns_pcie_ep_setup(ep); |
|
if (ret < 0) |
|
goto err_pcie_setup; |
|
|
|
break; |
|
} |
|
|
|
return 0; |
|
|
|
err_pcie_setup: |
|
cdns_pcie_disable_phy(cdns_pcie); |
|
|
|
err_get_sync: |
|
pm_runtime_put(dev); |
|
pm_runtime_disable(dev); |
|
|
|
return ret; |
|
} |
|
|
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static int j721e_pcie_remove(struct platform_device *pdev) |
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{ |
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struct j721e_pcie *pcie = platform_get_drvdata(pdev); |
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struct cdns_pcie *cdns_pcie = pcie->cdns_pcie; |
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struct device *dev = &pdev->dev; |
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|
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clk_disable_unprepare(pcie->refclk); |
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cdns_pcie_disable_phy(cdns_pcie); |
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pm_runtime_put(dev); |
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pm_runtime_disable(dev); |
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return 0; |
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} |
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static struct platform_driver j721e_pcie_driver = { |
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.probe = j721e_pcie_probe, |
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.remove = j721e_pcie_remove, |
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.driver = { |
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.name = "j721e-pcie", |
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.of_match_table = of_j721e_pcie_match, |
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.suppress_bind_attrs = true, |
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}, |
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}; |
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builtin_platform_driver(j721e_pcie_driver);
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