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56 lines
1.2 KiB
56 lines
1.2 KiB
/* SPDX-License-Identifier: GPL-2.0-or-later */ |
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/* |
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* Copyright 2016 Maxime Ripard |
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* |
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* Maxime Ripard <[email protected]> |
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*/ |
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#ifndef _CCU_SUN8I_A23_A33_H_ |
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#define _CCU_SUN8I_A23_A33_H_ |
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#include <dt-bindings/clock/sun8i-a23-a33-ccu.h> |
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#include <dt-bindings/reset/sun8i-a23-a33-ccu.h> |
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#define CLK_PLL_CPUX 0 |
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#define CLK_PLL_AUDIO_BASE 1 |
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#define CLK_PLL_AUDIO 2 |
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#define CLK_PLL_AUDIO_2X 3 |
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#define CLK_PLL_AUDIO_4X 4 |
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#define CLK_PLL_AUDIO_8X 5 |
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#define CLK_PLL_VIDEO 6 |
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#define CLK_PLL_VIDEO_2X 7 |
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#define CLK_PLL_VE 8 |
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#define CLK_PLL_DDR0 9 |
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#define CLK_PLL_PERIPH 10 |
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#define CLK_PLL_PERIPH_2X 11 |
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#define CLK_PLL_GPU 12 |
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/* The PLL MIPI clock is exported */ |
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#define CLK_PLL_HSIC 14 |
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#define CLK_PLL_DE 15 |
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#define CLK_PLL_DDR1 16 |
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#define CLK_PLL_DDR 17 |
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/* The CPUX clock is exported */ |
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#define CLK_AXI 19 |
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#define CLK_AHB1 20 |
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#define CLK_APB1 21 |
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#define CLK_APB2 22 |
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/* All the bus gates are exported */ |
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/* The first part of the mod clocks is exported */ |
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#define CLK_DRAM 79 |
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/* Some more module clocks are exported */ |
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#define CLK_MBUS 95 |
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/* And the last module clocks are exported */ |
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#define CLK_NUMBER (CLK_ATS + 1) |
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#endif /* _CCU_SUN8I_A23_A33_H_ */
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