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429 lines
10 KiB
429 lines
10 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* Copyright (c) 2018-2020, The Linux Foundation. All rights reserved. |
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*/ |
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#include <linux/clk-provider.h> |
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#include <linux/module.h> |
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#include <linux/platform_device.h> |
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#include <linux/pm_runtime.h> |
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#include <linux/regmap.h> |
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#include <dt-bindings/clock/qcom,videocc-sm8250.h> |
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#include "clk-alpha-pll.h" |
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#include "clk-branch.h" |
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#include "clk-rcg.h" |
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#include "clk-regmap.h" |
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#include "clk-regmap-divider.h" |
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#include "common.h" |
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#include "reset.h" |
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#include "gdsc.h" |
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enum { |
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P_BI_TCXO, |
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P_VIDEO_PLL0_OUT_MAIN, |
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P_VIDEO_PLL1_OUT_MAIN, |
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}; |
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static struct pll_vco lucid_vco[] = { |
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{ 249600000, 2000000000, 0 }, |
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}; |
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static const struct alpha_pll_config video_pll0_config = { |
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.l = 0x25, |
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.alpha = 0x8000, |
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.config_ctl_val = 0x20485699, |
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.config_ctl_hi_val = 0x00002261, |
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.config_ctl_hi1_val = 0x329A699C, |
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.user_ctl_val = 0x00000000, |
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.user_ctl_hi_val = 0x00000805, |
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.user_ctl_hi1_val = 0x00000000, |
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}; |
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static struct clk_alpha_pll video_pll0 = { |
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.offset = 0x42c, |
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.vco_table = lucid_vco, |
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.num_vco = ARRAY_SIZE(lucid_vco), |
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.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], |
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.clkr = { |
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.hw.init = &(struct clk_init_data){ |
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.name = "video_pll0", |
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.parent_data = &(const struct clk_parent_data){ |
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.fw_name = "bi_tcxo", |
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}, |
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.num_parents = 1, |
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.ops = &clk_alpha_pll_lucid_ops, |
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}, |
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}, |
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}; |
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static const struct alpha_pll_config video_pll1_config = { |
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.l = 0x2B, |
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.alpha = 0xC000, |
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.config_ctl_val = 0x20485699, |
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.config_ctl_hi_val = 0x00002261, |
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.config_ctl_hi1_val = 0x329A699C, |
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.user_ctl_val = 0x00000000, |
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.user_ctl_hi_val = 0x00000805, |
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.user_ctl_hi1_val = 0x00000000, |
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}; |
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static struct clk_alpha_pll video_pll1 = { |
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.offset = 0x7d0, |
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.vco_table = lucid_vco, |
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.num_vco = ARRAY_SIZE(lucid_vco), |
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.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], |
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.clkr = { |
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.hw.init = &(struct clk_init_data){ |
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.name = "video_pll1", |
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.parent_data = &(const struct clk_parent_data){ |
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.fw_name = "bi_tcxo", |
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}, |
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.num_parents = 1, |
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.ops = &clk_alpha_pll_lucid_ops, |
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}, |
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}, |
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}; |
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static const struct parent_map video_cc_parent_map_1[] = { |
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{ P_BI_TCXO, 0 }, |
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{ P_VIDEO_PLL0_OUT_MAIN, 1 }, |
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}; |
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static const struct clk_parent_data video_cc_parent_data_1[] = { |
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{ .fw_name = "bi_tcxo" }, |
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{ .hw = &video_pll0.clkr.hw }, |
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}; |
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static const struct parent_map video_cc_parent_map_2[] = { |
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{ P_BI_TCXO, 0 }, |
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{ P_VIDEO_PLL1_OUT_MAIN, 1 }, |
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}; |
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static const struct clk_parent_data video_cc_parent_data_2[] = { |
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{ .fw_name = "bi_tcxo" }, |
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{ .hw = &video_pll1.clkr.hw }, |
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}; |
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static const struct freq_tbl ftbl_video_cc_mvs0_clk_src[] = { |
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F(19200000, P_BI_TCXO, 1, 0, 0), |
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F(720000000, P_VIDEO_PLL0_OUT_MAIN, 1, 0, 0), |
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F(1014000000, P_VIDEO_PLL0_OUT_MAIN, 1, 0, 0), |
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F(1098000000, P_VIDEO_PLL0_OUT_MAIN, 1, 0, 0), |
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F(1332000000, P_VIDEO_PLL0_OUT_MAIN, 1, 0, 0), |
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{ } |
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}; |
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static struct clk_rcg2 video_cc_mvs0_clk_src = { |
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.cmd_rcgr = 0xb94, |
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.mnd_width = 0, |
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.hid_width = 5, |
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.parent_map = video_cc_parent_map_1, |
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.freq_tbl = ftbl_video_cc_mvs0_clk_src, |
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.clkr.hw.init = &(struct clk_init_data){ |
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.name = "video_cc_mvs0_clk_src", |
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.parent_data = video_cc_parent_data_1, |
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.num_parents = ARRAY_SIZE(video_cc_parent_data_1), |
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.flags = CLK_SET_RATE_PARENT, |
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.ops = &clk_rcg2_shared_ops, |
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}, |
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}; |
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static const struct freq_tbl ftbl_video_cc_mvs1_clk_src[] = { |
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F(19200000, P_BI_TCXO, 1, 0, 0), |
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F(840000000, P_VIDEO_PLL1_OUT_MAIN, 1, 0, 0), |
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F(1098000000, P_VIDEO_PLL1_OUT_MAIN, 1, 0, 0), |
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F(1332000000, P_VIDEO_PLL1_OUT_MAIN, 1, 0, 0), |
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{ } |
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}; |
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static struct clk_rcg2 video_cc_mvs1_clk_src = { |
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.cmd_rcgr = 0xbb4, |
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.mnd_width = 0, |
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.hid_width = 5, |
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.parent_map = video_cc_parent_map_2, |
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.freq_tbl = ftbl_video_cc_mvs1_clk_src, |
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.clkr.hw.init = &(struct clk_init_data){ |
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.name = "video_cc_mvs1_clk_src", |
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.parent_data = video_cc_parent_data_2, |
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.num_parents = ARRAY_SIZE(video_cc_parent_data_2), |
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.flags = CLK_SET_RATE_PARENT, |
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.ops = &clk_rcg2_shared_ops, |
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}, |
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}; |
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static struct clk_regmap_div video_cc_mvs0c_div2_div_clk_src = { |
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.reg = 0xc54, |
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.shift = 0, |
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.width = 2, |
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.clkr.hw.init = &(struct clk_init_data) { |
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.name = "video_cc_mvs0c_div2_div_clk_src", |
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.parent_hws = (const struct clk_hw*[]){ |
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&video_cc_mvs0_clk_src.clkr.hw, |
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}, |
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.num_parents = 1, |
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.flags = CLK_SET_RATE_PARENT, |
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.ops = &clk_regmap_div_ro_ops, |
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}, |
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}; |
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static struct clk_regmap_div video_cc_mvs0_div_clk_src = { |
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.reg = 0xd54, |
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.shift = 0, |
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.width = 2, |
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.clkr.hw.init = &(struct clk_init_data) { |
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.name = "video_cc_mvs0_div_clk_src", |
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.parent_hws = (const struct clk_hw*[]){ |
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&video_cc_mvs0_clk_src.clkr.hw, |
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}, |
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.num_parents = 1, |
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.flags = CLK_SET_RATE_PARENT, |
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.ops = &clk_regmap_div_ro_ops, |
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}, |
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}; |
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static struct clk_regmap_div video_cc_mvs1c_div2_div_clk_src = { |
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.reg = 0xcf4, |
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.shift = 0, |
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.width = 2, |
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.clkr.hw.init = &(struct clk_init_data) { |
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.name = "video_cc_mvs1c_div2_div_clk_src", |
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.parent_hws = (const struct clk_hw*[]){ |
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&video_cc_mvs1_clk_src.clkr.hw, |
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}, |
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.num_parents = 1, |
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.flags = CLK_SET_RATE_PARENT, |
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.ops = &clk_regmap_div_ro_ops, |
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}, |
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}; |
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static struct clk_branch video_cc_mvs0c_clk = { |
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.halt_reg = 0xc34, |
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.halt_check = BRANCH_HALT, |
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.clkr = { |
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.enable_reg = 0xc34, |
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.enable_mask = BIT(0), |
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.hw.init = &(struct clk_init_data){ |
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.name = "video_cc_mvs0c_clk", |
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.parent_hws = (const struct clk_hw*[]){ |
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&video_cc_mvs0c_div2_div_clk_src.clkr.hw, |
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}, |
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.num_parents = 1, |
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.flags = CLK_SET_RATE_PARENT, |
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.ops = &clk_branch2_ops, |
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}, |
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}, |
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}; |
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static struct clk_branch video_cc_mvs0_clk = { |
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.halt_reg = 0xd34, |
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.halt_check = BRANCH_HALT_VOTED, |
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.clkr = { |
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.enable_reg = 0xd34, |
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.enable_mask = BIT(0), |
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.hw.init = &(struct clk_init_data){ |
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.name = "video_cc_mvs0_clk", |
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.parent_hws = (const struct clk_hw*[]){ |
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&video_cc_mvs0_div_clk_src.clkr.hw, |
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}, |
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.num_parents = 1, |
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.flags = CLK_SET_RATE_PARENT, |
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.ops = &clk_branch2_ops, |
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}, |
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}, |
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}; |
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static struct clk_branch video_cc_mvs1_div2_clk = { |
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.halt_reg = 0xdf4, |
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.halt_check = BRANCH_HALT_VOTED, |
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.clkr = { |
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.enable_reg = 0xdf4, |
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.enable_mask = BIT(0), |
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.hw.init = &(struct clk_init_data){ |
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.name = "video_cc_mvs1_div2_clk", |
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.parent_hws = (const struct clk_hw*[]){ |
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&video_cc_mvs1c_div2_div_clk_src.clkr.hw, |
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}, |
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.num_parents = 1, |
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.flags = CLK_SET_RATE_PARENT, |
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.ops = &clk_branch2_ops, |
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}, |
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}, |
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}; |
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static struct clk_branch video_cc_mvs1c_clk = { |
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.halt_reg = 0xcd4, |
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.halt_check = BRANCH_HALT_VOTED, |
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.clkr = { |
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.enable_reg = 0xcd4, |
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.enable_mask = BIT(0), |
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.hw.init = &(struct clk_init_data){ |
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.name = "video_cc_mvs1c_clk", |
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.parent_hws = (const struct clk_hw*[]){ |
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&video_cc_mvs1c_div2_div_clk_src.clkr.hw, |
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}, |
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.num_parents = 1, |
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.flags = CLK_SET_RATE_PARENT, |
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.ops = &clk_branch2_ops, |
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}, |
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}, |
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}; |
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static struct gdsc mvs0c_gdsc = { |
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.gdscr = 0xbf8, |
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.pd = { |
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.name = "mvs0c_gdsc", |
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}, |
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.flags = 0, |
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.pwrsts = PWRSTS_OFF_ON, |
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.supply = "mmcx", |
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}; |
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static struct gdsc mvs1c_gdsc = { |
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.gdscr = 0xc98, |
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.pd = { |
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.name = "mvs1c_gdsc", |
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}, |
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.flags = 0, |
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.pwrsts = PWRSTS_OFF_ON, |
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.supply = "mmcx", |
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}; |
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static struct gdsc mvs0_gdsc = { |
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.gdscr = 0xd18, |
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.pd = { |
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.name = "mvs0_gdsc", |
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}, |
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.flags = HW_CTRL, |
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.pwrsts = PWRSTS_OFF_ON, |
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.supply = "mmcx", |
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}; |
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static struct gdsc mvs1_gdsc = { |
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.gdscr = 0xd98, |
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.pd = { |
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.name = "mvs1_gdsc", |
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}, |
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.flags = HW_CTRL, |
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.pwrsts = PWRSTS_OFF_ON, |
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.supply = "mmcx", |
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}; |
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static struct clk_regmap *video_cc_sm8250_clocks[] = { |
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[VIDEO_CC_MVS0_CLK] = &video_cc_mvs0_clk.clkr, |
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[VIDEO_CC_MVS0_CLK_SRC] = &video_cc_mvs0_clk_src.clkr, |
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[VIDEO_CC_MVS0_DIV_CLK_SRC] = &video_cc_mvs0_div_clk_src.clkr, |
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[VIDEO_CC_MVS0C_CLK] = &video_cc_mvs0c_clk.clkr, |
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[VIDEO_CC_MVS0C_DIV2_DIV_CLK_SRC] = &video_cc_mvs0c_div2_div_clk_src.clkr, |
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[VIDEO_CC_MVS1_CLK_SRC] = &video_cc_mvs1_clk_src.clkr, |
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[VIDEO_CC_MVS1_DIV2_CLK] = &video_cc_mvs1_div2_clk.clkr, |
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[VIDEO_CC_MVS1C_CLK] = &video_cc_mvs1c_clk.clkr, |
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[VIDEO_CC_MVS1C_DIV2_DIV_CLK_SRC] = &video_cc_mvs1c_div2_div_clk_src.clkr, |
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[VIDEO_CC_PLL0] = &video_pll0.clkr, |
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[VIDEO_CC_PLL1] = &video_pll1.clkr, |
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}; |
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static const struct qcom_reset_map video_cc_sm8250_resets[] = { |
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[VIDEO_CC_CVP_INTERFACE_BCR] = { 0xe54 }, |
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[VIDEO_CC_CVP_MVS0_BCR] = { 0xd14 }, |
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[VIDEO_CC_MVS0C_CLK_ARES] = { 0xc34, 2 }, |
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[VIDEO_CC_CVP_MVS0C_BCR] = { 0xbf4 }, |
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[VIDEO_CC_CVP_MVS1_BCR] = { 0xd94 }, |
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[VIDEO_CC_MVS1C_CLK_ARES] = { 0xcd4, 2 }, |
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[VIDEO_CC_CVP_MVS1C_BCR] = { 0xc94 }, |
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}; |
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static struct gdsc *video_cc_sm8250_gdscs[] = { |
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[MVS0C_GDSC] = &mvs0c_gdsc, |
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[MVS1C_GDSC] = &mvs1c_gdsc, |
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[MVS0_GDSC] = &mvs0_gdsc, |
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[MVS1_GDSC] = &mvs1_gdsc, |
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}; |
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static const struct regmap_config video_cc_sm8250_regmap_config = { |
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.reg_bits = 32, |
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.reg_stride = 4, |
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.val_bits = 32, |
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.max_register = 0xf4c, |
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.fast_io = true, |
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}; |
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static const struct qcom_cc_desc video_cc_sm8250_desc = { |
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.config = &video_cc_sm8250_regmap_config, |
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.clks = video_cc_sm8250_clocks, |
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.num_clks = ARRAY_SIZE(video_cc_sm8250_clocks), |
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.resets = video_cc_sm8250_resets, |
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.num_resets = ARRAY_SIZE(video_cc_sm8250_resets), |
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.gdscs = video_cc_sm8250_gdscs, |
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.num_gdscs = ARRAY_SIZE(video_cc_sm8250_gdscs), |
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}; |
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static const struct of_device_id video_cc_sm8250_match_table[] = { |
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{ .compatible = "qcom,sm8250-videocc" }, |
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{ } |
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}; |
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MODULE_DEVICE_TABLE(of, video_cc_sm8250_match_table); |
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static void video_cc_sm8250_pm_runtime_disable(void *data) |
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{ |
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pm_runtime_disable(data); |
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} |
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static int video_cc_sm8250_probe(struct platform_device *pdev) |
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{ |
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struct regmap *regmap; |
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int ret; |
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pm_runtime_enable(&pdev->dev); |
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ret = devm_add_action_or_reset(&pdev->dev, video_cc_sm8250_pm_runtime_disable, &pdev->dev); |
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if (ret) |
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return ret; |
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ret = pm_runtime_resume_and_get(&pdev->dev); |
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if (ret) |
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return ret; |
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regmap = qcom_cc_map(pdev, &video_cc_sm8250_desc); |
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if (IS_ERR(regmap)) { |
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pm_runtime_put(&pdev->dev); |
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return PTR_ERR(regmap); |
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} |
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clk_lucid_pll_configure(&video_pll0, regmap, &video_pll0_config); |
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clk_lucid_pll_configure(&video_pll1, regmap, &video_pll1_config); |
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/* Keep VIDEO_CC_AHB_CLK and VIDEO_CC_XO_CLK ALWAYS-ON */ |
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regmap_update_bits(regmap, 0xe58, BIT(0), BIT(0)); |
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regmap_update_bits(regmap, 0xeec, BIT(0), BIT(0)); |
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ret = qcom_cc_really_probe(pdev, &video_cc_sm8250_desc, regmap); |
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pm_runtime_put(&pdev->dev); |
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return ret; |
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} |
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static struct platform_driver video_cc_sm8250_driver = { |
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.probe = video_cc_sm8250_probe, |
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.driver = { |
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.name = "sm8250-videocc", |
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.of_match_table = video_cc_sm8250_match_table, |
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}, |
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}; |
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static int __init video_cc_sm8250_init(void) |
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{ |
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return platform_driver_register(&video_cc_sm8250_driver); |
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} |
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subsys_initcall(video_cc_sm8250_init); |
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static void __exit video_cc_sm8250_exit(void) |
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{ |
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platform_driver_unregister(&video_cc_sm8250_driver); |
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} |
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module_exit(video_cc_sm8250_exit); |
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MODULE_LICENSE("GPL v2"); |
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MODULE_DESCRIPTION("QTI VIDEOCC SM8250 Driver");
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