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797 lines
21 KiB
797 lines
21 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* Copyright (c) 2021, The Linux Foundation. All rights reserved. |
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* Copyright (c) 2021, Konrad Dybcio <[email protected]> |
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*/ |
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#include <linux/clk-provider.h> |
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#include <linux/module.h> |
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#include <linux/platform_device.h> |
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#include <linux/regmap.h> |
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#include <dt-bindings/clock/qcom,dispcc-sm6350.h> |
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#include "clk-alpha-pll.h" |
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#include "clk-branch.h" |
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#include "clk-rcg.h" |
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#include "clk-regmap.h" |
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#include "clk-regmap-divider.h" |
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#include "common.h" |
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#include "gdsc.h" |
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#include "reset.h" |
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enum { |
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P_BI_TCXO, |
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P_DISP_CC_PLL0_OUT_EVEN, |
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P_DISP_CC_PLL0_OUT_MAIN, |
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P_DP_PHY_PLL_LINK_CLK, |
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P_DP_PHY_PLL_VCO_DIV_CLK, |
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P_DSI0_PHY_PLL_OUT_BYTECLK, |
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P_DSI0_PHY_PLL_OUT_DSICLK, |
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P_GCC_DISP_GPLL0_CLK, |
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}; |
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static struct pll_vco fabia_vco[] = { |
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{ 249600000, 2000000000, 0 }, |
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}; |
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static const struct alpha_pll_config disp_cc_pll0_config = { |
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.l = 0x3a, |
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.alpha = 0x5555, |
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.config_ctl_val = 0x20485699, |
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.config_ctl_hi_val = 0x00002067, |
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.test_ctl_val = 0x40000000, |
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.test_ctl_hi_val = 0x00000002, |
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.user_ctl_val = 0x00000000, |
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.user_ctl_hi_val = 0x00004805, |
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}; |
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static struct clk_alpha_pll disp_cc_pll0 = { |
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.offset = 0x0, |
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.vco_table = fabia_vco, |
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.num_vco = ARRAY_SIZE(fabia_vco), |
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.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], |
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.clkr = { |
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.hw.init = &(struct clk_init_data){ |
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.name = "disp_cc_pll0", |
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.parent_data = &(const struct clk_parent_data){ |
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.fw_name = "bi_tcxo", |
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}, |
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.num_parents = 1, |
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.ops = &clk_alpha_pll_fabia_ops, |
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}, |
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}, |
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}; |
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static const struct parent_map disp_cc_parent_map_0[] = { |
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{ P_BI_TCXO, 0 }, |
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{ P_DP_PHY_PLL_LINK_CLK, 1 }, |
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{ P_DP_PHY_PLL_VCO_DIV_CLK, 2 }, |
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}; |
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static const struct clk_parent_data disp_cc_parent_data_0[] = { |
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{ .fw_name = "bi_tcxo" }, |
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{ .fw_name = "dp_phy_pll_link_clk" }, |
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{ .fw_name = "dp_phy_pll_vco_div_clk" }, |
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}; |
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static const struct parent_map disp_cc_parent_map_1[] = { |
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{ P_BI_TCXO, 0 }, |
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{ P_DSI0_PHY_PLL_OUT_BYTECLK, 1 }, |
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}; |
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static const struct clk_parent_data disp_cc_parent_data_1[] = { |
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{ .fw_name = "bi_tcxo" }, |
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{ .fw_name = "dsi0_phy_pll_out_byteclk" }, |
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}; |
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static const struct parent_map disp_cc_parent_map_3[] = { |
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{ P_BI_TCXO, 0 }, |
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{ P_DISP_CC_PLL0_OUT_MAIN, 1 }, |
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{ P_GCC_DISP_GPLL0_CLK, 4 }, |
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{ P_DISP_CC_PLL0_OUT_EVEN, 5 }, |
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}; |
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static const struct clk_parent_data disp_cc_parent_data_3[] = { |
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{ .fw_name = "bi_tcxo" }, |
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{ .hw = &disp_cc_pll0.clkr.hw }, |
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{ .fw_name = "gcc_disp_gpll0_clk" }, |
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{ .hw = &disp_cc_pll0.clkr.hw }, |
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}; |
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static const struct parent_map disp_cc_parent_map_4[] = { |
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{ P_BI_TCXO, 0 }, |
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{ P_GCC_DISP_GPLL0_CLK, 4 }, |
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}; |
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static const struct clk_parent_data disp_cc_parent_data_4[] = { |
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{ .fw_name = "bi_tcxo" }, |
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{ .fw_name = "gcc_disp_gpll0_clk" }, |
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}; |
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static const struct parent_map disp_cc_parent_map_5[] = { |
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{ P_BI_TCXO, 0 }, |
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{ P_DSI0_PHY_PLL_OUT_DSICLK, 1 }, |
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}; |
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static const struct clk_parent_data disp_cc_parent_data_5[] = { |
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{ .fw_name = "bi_tcxo" }, |
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{ .fw_name = "dsi0_phy_pll_out_dsiclk" }, |
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}; |
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static const struct parent_map disp_cc_parent_map_6[] = { |
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{ P_BI_TCXO, 0 }, |
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}; |
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static const struct clk_parent_data disp_cc_parent_data_6[] = { |
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{ .fw_name = "bi_tcxo" }, |
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}; |
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static const struct freq_tbl ftbl_disp_cc_mdss_ahb_clk_src[] = { |
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F(19200000, P_BI_TCXO, 1, 0, 0), |
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F(37500000, P_GCC_DISP_GPLL0_CLK, 16, 0, 0), |
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F(75000000, P_GCC_DISP_GPLL0_CLK, 8, 0, 0), |
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{ } |
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}; |
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static struct clk_rcg2 disp_cc_mdss_ahb_clk_src = { |
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.cmd_rcgr = 0x115c, |
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.mnd_width = 0, |
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.hid_width = 5, |
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.parent_map = disp_cc_parent_map_4, |
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.freq_tbl = ftbl_disp_cc_mdss_ahb_clk_src, |
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.clkr.hw.init = &(struct clk_init_data){ |
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.name = "disp_cc_mdss_ahb_clk_src", |
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.parent_data = disp_cc_parent_data_4, |
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.num_parents = ARRAY_SIZE(disp_cc_parent_data_4), |
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.flags = CLK_SET_RATE_PARENT, |
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.ops = &clk_rcg2_ops, |
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}, |
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}; |
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static struct clk_rcg2 disp_cc_mdss_byte0_clk_src = { |
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.cmd_rcgr = 0x10c4, |
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.mnd_width = 0, |
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.hid_width = 5, |
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.parent_map = disp_cc_parent_map_1, |
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.clkr.hw.init = &(struct clk_init_data){ |
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.name = "disp_cc_mdss_byte0_clk_src", |
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.parent_data = disp_cc_parent_data_1, |
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.num_parents = ARRAY_SIZE(disp_cc_parent_data_1), |
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.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, |
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.ops = &clk_byte2_ops, |
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}, |
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}; |
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static struct clk_regmap_div disp_cc_mdss_byte0_div_clk_src = { |
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.reg = 0x10dc, |
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.shift = 0, |
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.width = 2, |
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.clkr.hw.init = &(struct clk_init_data) { |
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.name = "disp_cc_mdss_byte0_div_clk_src", |
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.parent_hws = (const struct clk_hw*[]){ |
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&disp_cc_mdss_byte0_clk_src.clkr.hw, |
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}, |
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.num_parents = 1, |
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.flags = CLK_GET_RATE_NOCACHE, |
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.ops = &clk_regmap_div_ro_ops, |
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}, |
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}; |
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static const struct freq_tbl ftbl_disp_cc_mdss_dp_aux_clk_src[] = { |
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F(19200000, P_BI_TCXO, 1, 0, 0), |
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{ } |
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}; |
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static struct clk_rcg2 disp_cc_mdss_dp_aux_clk_src = { |
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.cmd_rcgr = 0x1144, |
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.mnd_width = 0, |
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.hid_width = 5, |
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.freq_tbl = ftbl_disp_cc_mdss_dp_aux_clk_src, |
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.clkr.hw.init = &(struct clk_init_data){ |
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.name = "disp_cc_mdss_dp_aux_clk_src", |
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.parent_data = &(const struct clk_parent_data){ |
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.fw_name = "bi_tcxo", |
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}, |
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.num_parents = 1, |
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.ops = &clk_rcg2_ops, |
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}, |
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}; |
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static const struct freq_tbl ftbl_disp_cc_mdss_dp_crypto_clk_src[] = { |
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F(108000, P_DP_PHY_PLL_LINK_CLK, 3, 0, 0), |
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F(180000, P_DP_PHY_PLL_LINK_CLK, 3, 0, 0), |
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F(360000, P_DP_PHY_PLL_LINK_CLK, 1.5, 0, 0), |
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F(540000, P_DP_PHY_PLL_LINK_CLK, 1.5, 0, 0), |
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{ } |
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}; |
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static struct clk_rcg2 disp_cc_mdss_dp_crypto_clk_src = { |
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.cmd_rcgr = 0x1114, |
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.mnd_width = 0, |
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.hid_width = 5, |
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.parent_map = disp_cc_parent_map_0, |
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.freq_tbl = ftbl_disp_cc_mdss_dp_crypto_clk_src, |
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.clkr.hw.init = &(struct clk_init_data){ |
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.name = "disp_cc_mdss_dp_crypto_clk_src", |
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.parent_data = disp_cc_parent_data_0, |
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.num_parents = ARRAY_SIZE(disp_cc_parent_data_0), |
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.flags = CLK_GET_RATE_NOCACHE, |
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.ops = &clk_rcg2_ops, |
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}, |
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}; |
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static const struct freq_tbl ftbl_disp_cc_mdss_dp_link_clk_src[] = { |
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F(162000, P_DP_PHY_PLL_LINK_CLK, 1, 0, 0), |
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F(270000, P_DP_PHY_PLL_LINK_CLK, 1, 0, 0), |
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F(540000, P_DP_PHY_PLL_LINK_CLK, 1, 0, 0), |
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F(810000, P_DP_PHY_PLL_LINK_CLK, 1, 0, 0), |
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{ } |
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}; |
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static struct clk_rcg2 disp_cc_mdss_dp_link_clk_src = { |
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.cmd_rcgr = 0x10f8, |
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.mnd_width = 0, |
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.hid_width = 5, |
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.parent_map = disp_cc_parent_map_0, |
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.freq_tbl = ftbl_disp_cc_mdss_dp_link_clk_src, |
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.clkr.hw.init = &(struct clk_init_data){ |
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.name = "disp_cc_mdss_dp_link_clk_src", |
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.parent_data = disp_cc_parent_data_0, |
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.num_parents = ARRAY_SIZE(disp_cc_parent_data_0), |
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.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, |
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.ops = &clk_rcg2_ops, |
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}, |
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}; |
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static struct clk_rcg2 disp_cc_mdss_dp_pixel_clk_src = { |
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.cmd_rcgr = 0x112c, |
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.mnd_width = 16, |
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.hid_width = 5, |
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.parent_map = disp_cc_parent_map_0, |
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.clkr.hw.init = &(struct clk_init_data){ |
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.name = "disp_cc_mdss_dp_pixel_clk_src", |
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.parent_data = disp_cc_parent_data_0, |
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.num_parents = ARRAY_SIZE(disp_cc_parent_data_0), |
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.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, |
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.ops = &clk_dp_ops, |
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}, |
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}; |
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static struct clk_rcg2 disp_cc_mdss_esc0_clk_src = { |
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.cmd_rcgr = 0x10e0, |
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.mnd_width = 0, |
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.hid_width = 5, |
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.parent_map = disp_cc_parent_map_1, |
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.freq_tbl = ftbl_disp_cc_mdss_dp_aux_clk_src, |
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.clkr.hw.init = &(struct clk_init_data){ |
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.name = "disp_cc_mdss_esc0_clk_src", |
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.parent_data = disp_cc_parent_data_1, |
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.num_parents = ARRAY_SIZE(disp_cc_parent_data_1), |
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.ops = &clk_rcg2_ops, |
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}, |
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}; |
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static const struct freq_tbl ftbl_disp_cc_mdss_mdp_clk_src[] = { |
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F(19200000, P_BI_TCXO, 1, 0, 0), |
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F(200000000, P_GCC_DISP_GPLL0_CLK, 3, 0, 0), |
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F(300000000, P_GCC_DISP_GPLL0_CLK, 2, 0, 0), |
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F(373333333, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), |
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F(448000000, P_DISP_CC_PLL0_OUT_MAIN, 2.5, 0, 0), |
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F(560000000, P_DISP_CC_PLL0_OUT_MAIN, 2, 0, 0), |
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{ } |
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}; |
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static struct clk_rcg2 disp_cc_mdss_mdp_clk_src = { |
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.cmd_rcgr = 0x107c, |
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.mnd_width = 0, |
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.hid_width = 5, |
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.parent_map = disp_cc_parent_map_3, |
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.freq_tbl = ftbl_disp_cc_mdss_mdp_clk_src, |
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.clkr.hw.init = &(struct clk_init_data){ |
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.name = "disp_cc_mdss_mdp_clk_src", |
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.parent_data = disp_cc_parent_data_3, |
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.num_parents = ARRAY_SIZE(disp_cc_parent_data_3), |
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.flags = CLK_SET_RATE_PARENT, |
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.ops = &clk_rcg2_ops, |
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}, |
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}; |
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static struct clk_rcg2 disp_cc_mdss_pclk0_clk_src = { |
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.cmd_rcgr = 0x1064, |
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.mnd_width = 8, |
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.hid_width = 5, |
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.parent_map = disp_cc_parent_map_5, |
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.clkr.hw.init = &(struct clk_init_data){ |
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.name = "disp_cc_mdss_pclk0_clk_src", |
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.parent_data = disp_cc_parent_data_5, |
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.num_parents = ARRAY_SIZE(disp_cc_parent_data_5), |
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.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, |
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.ops = &clk_pixel_ops, |
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}, |
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}; |
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static struct clk_rcg2 disp_cc_mdss_rot_clk_src = { |
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.cmd_rcgr = 0x1094, |
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.mnd_width = 0, |
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.hid_width = 5, |
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.parent_map = disp_cc_parent_map_3, |
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.freq_tbl = ftbl_disp_cc_mdss_mdp_clk_src, |
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.clkr.hw.init = &(struct clk_init_data){ |
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.name = "disp_cc_mdss_rot_clk_src", |
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.parent_data = disp_cc_parent_data_3, |
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.num_parents = ARRAY_SIZE(disp_cc_parent_data_3), |
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.flags = CLK_SET_RATE_PARENT, |
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.ops = &clk_rcg2_ops, |
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}, |
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}; |
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static struct clk_rcg2 disp_cc_mdss_vsync_clk_src = { |
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.cmd_rcgr = 0x10ac, |
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.mnd_width = 0, |
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.hid_width = 5, |
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.parent_map = disp_cc_parent_map_6, |
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.freq_tbl = ftbl_disp_cc_mdss_dp_aux_clk_src, |
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.clkr.hw.init = &(struct clk_init_data){ |
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.name = "disp_cc_mdss_vsync_clk_src", |
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.parent_data = disp_cc_parent_data_6, |
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.num_parents = ARRAY_SIZE(disp_cc_parent_data_6), |
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.ops = &clk_rcg2_ops, |
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}, |
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}; |
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static struct clk_regmap_div disp_cc_mdss_dp_link_div_clk_src = { |
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.reg = 0x1110, |
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.shift = 0, |
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.width = 2, |
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.clkr.hw.init = &(struct clk_init_data) { |
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.name = "disp_cc_mdss_dp_link_div_clk_src", |
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.parent_hws = (const struct clk_hw*[]){ |
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&disp_cc_mdss_dp_link_clk_src.clkr.hw, |
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}, |
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.num_parents = 1, |
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.flags = CLK_GET_RATE_NOCACHE, |
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.ops = &clk_regmap_div_ro_ops, |
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}, |
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}; |
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static struct clk_branch disp_cc_mdss_ahb_clk = { |
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.halt_reg = 0x104c, |
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.halt_check = BRANCH_HALT, |
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.clkr = { |
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.enable_reg = 0x104c, |
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.enable_mask = BIT(0), |
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.hw.init = &(struct clk_init_data){ |
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.name = "disp_cc_mdss_ahb_clk", |
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.parent_hws = (const struct clk_hw*[]){ |
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&disp_cc_mdss_ahb_clk_src.clkr.hw, |
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}, |
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.num_parents = 1, |
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.flags = CLK_SET_RATE_PARENT, |
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.ops = &clk_branch2_ops, |
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}, |
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}, |
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}; |
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static struct clk_branch disp_cc_mdss_byte0_clk = { |
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.halt_reg = 0x102c, |
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.halt_check = BRANCH_HALT, |
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.clkr = { |
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.enable_reg = 0x102c, |
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.enable_mask = BIT(0), |
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.hw.init = &(struct clk_init_data){ |
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.name = "disp_cc_mdss_byte0_clk", |
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.parent_hws = (const struct clk_hw*[]){ |
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&disp_cc_mdss_byte0_clk_src.clkr.hw, |
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}, |
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.num_parents = 1, |
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.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, |
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.ops = &clk_branch2_ops, |
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}, |
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}, |
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}; |
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static struct clk_branch disp_cc_mdss_byte0_intf_clk = { |
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.halt_reg = 0x1030, |
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.halt_check = BRANCH_HALT, |
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.clkr = { |
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.enable_reg = 0x1030, |
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.enable_mask = BIT(0), |
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.hw.init = &(struct clk_init_data){ |
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.name = "disp_cc_mdss_byte0_intf_clk", |
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.parent_hws = (const struct clk_hw*[]){ |
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&disp_cc_mdss_byte0_div_clk_src.clkr.hw, |
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}, |
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.num_parents = 1, |
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.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, |
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.ops = &clk_branch2_ops, |
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}, |
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}, |
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}; |
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static struct clk_branch disp_cc_mdss_dp_aux_clk = { |
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.halt_reg = 0x1048, |
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.halt_check = BRANCH_HALT, |
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.clkr = { |
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.enable_reg = 0x1048, |
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.enable_mask = BIT(0), |
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.hw.init = &(struct clk_init_data){ |
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.name = "disp_cc_mdss_dp_aux_clk", |
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.parent_hws = (const struct clk_hw*[]){ |
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&disp_cc_mdss_dp_aux_clk_src.clkr.hw, |
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}, |
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.num_parents = 1, |
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.flags = CLK_SET_RATE_PARENT, |
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.ops = &clk_branch2_ops, |
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}, |
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}, |
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}; |
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static struct clk_branch disp_cc_mdss_dp_crypto_clk = { |
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.halt_reg = 0x1040, |
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.halt_check = BRANCH_HALT, |
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.clkr = { |
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.enable_reg = 0x1040, |
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.enable_mask = BIT(0), |
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.hw.init = &(struct clk_init_data){ |
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.name = "disp_cc_mdss_dp_crypto_clk", |
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.parent_hws = (const struct clk_hw*[]){ |
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&disp_cc_mdss_dp_crypto_clk_src.clkr.hw, |
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}, |
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.num_parents = 1, |
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.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, |
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.ops = &clk_branch2_ops, |
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}, |
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}, |
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}; |
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static struct clk_branch disp_cc_mdss_dp_link_clk = { |
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.halt_reg = 0x1038, |
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.halt_check = BRANCH_HALT, |
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.clkr = { |
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.enable_reg = 0x1038, |
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.enable_mask = BIT(0), |
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.hw.init = &(struct clk_init_data){ |
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.name = "disp_cc_mdss_dp_link_clk", |
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.parent_hws = (const struct clk_hw*[]){ |
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&disp_cc_mdss_dp_link_clk_src.clkr.hw, |
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}, |
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.num_parents = 1, |
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.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, |
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.ops = &clk_branch2_ops, |
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}, |
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}, |
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}; |
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static struct clk_branch disp_cc_mdss_dp_link_intf_clk = { |
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.halt_reg = 0x103c, |
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.halt_check = BRANCH_HALT, |
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.clkr = { |
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.enable_reg = 0x103c, |
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.enable_mask = BIT(0), |
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.hw.init = &(struct clk_init_data){ |
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.name = "disp_cc_mdss_dp_link_intf_clk", |
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.parent_hws = (const struct clk_hw*[]){ |
|
&disp_cc_mdss_dp_link_div_clk_src.clkr.hw, |
|
}, |
|
.num_parents = 1, |
|
.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, |
|
.ops = &clk_branch2_ops, |
|
}, |
|
}, |
|
}; |
|
|
|
static struct clk_branch disp_cc_mdss_dp_pixel_clk = { |
|
.halt_reg = 0x1044, |
|
.halt_check = BRANCH_HALT, |
|
.clkr = { |
|
.enable_reg = 0x1044, |
|
.enable_mask = BIT(0), |
|
.hw.init = &(struct clk_init_data){ |
|
.name = "disp_cc_mdss_dp_pixel_clk", |
|
.parent_hws = (const struct clk_hw*[]){ |
|
&disp_cc_mdss_dp_pixel_clk_src.clkr.hw, |
|
}, |
|
.num_parents = 1, |
|
.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, |
|
.ops = &clk_branch2_ops, |
|
}, |
|
}, |
|
}; |
|
|
|
static struct clk_branch disp_cc_mdss_esc0_clk = { |
|
.halt_reg = 0x1034, |
|
.halt_check = BRANCH_HALT, |
|
.clkr = { |
|
.enable_reg = 0x1034, |
|
.enable_mask = BIT(0), |
|
.hw.init = &(struct clk_init_data){ |
|
.name = "disp_cc_mdss_esc0_clk", |
|
.parent_hws = (const struct clk_hw*[]){ |
|
&disp_cc_mdss_esc0_clk_src.clkr.hw, |
|
}, |
|
.num_parents = 1, |
|
.flags = CLK_SET_RATE_PARENT, |
|
.ops = &clk_branch2_ops, |
|
}, |
|
}, |
|
}; |
|
|
|
static struct clk_branch disp_cc_mdss_mdp_clk = { |
|
.halt_reg = 0x1010, |
|
.halt_check = BRANCH_HALT, |
|
.clkr = { |
|
.enable_reg = 0x1010, |
|
.enable_mask = BIT(0), |
|
.hw.init = &(struct clk_init_data){ |
|
.name = "disp_cc_mdss_mdp_clk", |
|
.parent_hws = (const struct clk_hw*[]){ |
|
&disp_cc_mdss_mdp_clk_src.clkr.hw, |
|
}, |
|
.num_parents = 1, |
|
.flags = CLK_SET_RATE_PARENT, |
|
.ops = &clk_branch2_ops, |
|
}, |
|
}, |
|
}; |
|
|
|
static struct clk_branch disp_cc_mdss_mdp_lut_clk = { |
|
.halt_reg = 0x1020, |
|
.halt_check = BRANCH_HALT_VOTED, |
|
.clkr = { |
|
.enable_reg = 0x1020, |
|
.enable_mask = BIT(0), |
|
.hw.init = &(struct clk_init_data){ |
|
.name = "disp_cc_mdss_mdp_lut_clk", |
|
.parent_hws = (const struct clk_hw*[]){ |
|
&disp_cc_mdss_mdp_clk_src.clkr.hw, |
|
}, |
|
.num_parents = 1, |
|
.flags = CLK_SET_RATE_PARENT, |
|
.ops = &clk_branch2_ops, |
|
}, |
|
}, |
|
}; |
|
|
|
static struct clk_branch disp_cc_mdss_non_gdsc_ahb_clk = { |
|
.halt_reg = 0x2004, |
|
.halt_check = BRANCH_HALT_VOTED, |
|
.clkr = { |
|
.enable_reg = 0x2004, |
|
.enable_mask = BIT(0), |
|
.hw.init = &(struct clk_init_data){ |
|
.name = "disp_cc_mdss_non_gdsc_ahb_clk", |
|
.parent_hws = (const struct clk_hw*[]){ |
|
&disp_cc_mdss_ahb_clk_src.clkr.hw, |
|
}, |
|
.num_parents = 1, |
|
.flags = CLK_SET_RATE_PARENT, |
|
.ops = &clk_branch2_ops, |
|
}, |
|
}, |
|
}; |
|
|
|
static struct clk_branch disp_cc_mdss_pclk0_clk = { |
|
.halt_reg = 0x100c, |
|
.halt_check = BRANCH_HALT, |
|
.clkr = { |
|
.enable_reg = 0x100c, |
|
.enable_mask = BIT(0), |
|
.hw.init = &(struct clk_init_data){ |
|
.name = "disp_cc_mdss_pclk0_clk", |
|
.parent_hws = (const struct clk_hw*[]){ |
|
&disp_cc_mdss_pclk0_clk_src.clkr.hw, |
|
}, |
|
.num_parents = 1, |
|
.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, |
|
.ops = &clk_branch2_ops, |
|
}, |
|
}, |
|
}; |
|
|
|
static struct clk_branch disp_cc_mdss_rot_clk = { |
|
.halt_reg = 0x1018, |
|
.halt_check = BRANCH_HALT, |
|
.clkr = { |
|
.enable_reg = 0x1018, |
|
.enable_mask = BIT(0), |
|
.hw.init = &(struct clk_init_data){ |
|
.name = "disp_cc_mdss_rot_clk", |
|
.parent_hws = (const struct clk_hw*[]){ |
|
&disp_cc_mdss_rot_clk_src.clkr.hw, |
|
}, |
|
.num_parents = 1, |
|
.flags = CLK_SET_RATE_PARENT, |
|
.ops = &clk_branch2_ops, |
|
}, |
|
}, |
|
}; |
|
|
|
static struct clk_branch disp_cc_mdss_rscc_ahb_clk = { |
|
.halt_reg = 0x200c, |
|
.halt_check = BRANCH_HALT, |
|
.clkr = { |
|
.enable_reg = 0x200c, |
|
.enable_mask = BIT(0), |
|
.hw.init = &(struct clk_init_data){ |
|
.name = "disp_cc_mdss_rscc_ahb_clk", |
|
.parent_hws = (const struct clk_hw*[]){ |
|
&disp_cc_mdss_ahb_clk_src.clkr.hw, |
|
}, |
|
.num_parents = 1, |
|
.flags = CLK_SET_RATE_PARENT, |
|
.ops = &clk_branch2_ops, |
|
}, |
|
}, |
|
}; |
|
|
|
static struct clk_branch disp_cc_mdss_rscc_vsync_clk = { |
|
.halt_reg = 0x2008, |
|
.halt_check = BRANCH_HALT, |
|
.clkr = { |
|
.enable_reg = 0x2008, |
|
.enable_mask = BIT(0), |
|
.hw.init = &(struct clk_init_data){ |
|
.name = "disp_cc_mdss_rscc_vsync_clk", |
|
.parent_hws = (const struct clk_hw*[]){ |
|
&disp_cc_mdss_vsync_clk_src.clkr.hw, |
|
}, |
|
.num_parents = 1, |
|
.flags = CLK_SET_RATE_PARENT, |
|
.ops = &clk_branch2_ops, |
|
}, |
|
}, |
|
}; |
|
|
|
static struct clk_branch disp_cc_mdss_vsync_clk = { |
|
.halt_reg = 0x1028, |
|
.halt_check = BRANCH_HALT, |
|
.clkr = { |
|
.enable_reg = 0x1028, |
|
.enable_mask = BIT(0), |
|
.hw.init = &(struct clk_init_data){ |
|
.name = "disp_cc_mdss_vsync_clk", |
|
.parent_hws = (const struct clk_hw*[]){ |
|
&disp_cc_mdss_vsync_clk_src.clkr.hw, |
|
}, |
|
.num_parents = 1, |
|
.flags = CLK_SET_RATE_PARENT, |
|
.ops = &clk_branch2_ops, |
|
}, |
|
}, |
|
}; |
|
|
|
static struct clk_branch disp_cc_sleep_clk = { |
|
.halt_reg = 0x5004, |
|
.halt_check = BRANCH_HALT, |
|
.clkr = { |
|
.enable_reg = 0x5004, |
|
.enable_mask = BIT(0), |
|
.hw.init = &(struct clk_init_data){ |
|
.name = "disp_cc_sleep_clk", |
|
.ops = &clk_branch2_ops, |
|
}, |
|
}, |
|
}; |
|
|
|
static struct clk_branch disp_cc_xo_clk = { |
|
.halt_reg = 0x5008, |
|
.halt_check = BRANCH_HALT, |
|
.clkr = { |
|
.enable_reg = 0x5008, |
|
.enable_mask = BIT(0), |
|
.hw.init = &(struct clk_init_data){ |
|
.name = "disp_cc_xo_clk", |
|
.flags = CLK_IS_CRITICAL, |
|
.ops = &clk_branch2_ops, |
|
}, |
|
}, |
|
}; |
|
|
|
static struct gdsc mdss_gdsc = { |
|
.gdscr = 0x1004, |
|
.pd = { |
|
.name = "mdss_gdsc", |
|
}, |
|
.pwrsts = PWRSTS_OFF_ON, |
|
.flags = RETAIN_FF_ENABLE, |
|
}; |
|
|
|
static struct clk_regmap *disp_cc_sm6350_clocks[] = { |
|
[DISP_CC_MDSS_AHB_CLK] = &disp_cc_mdss_ahb_clk.clkr, |
|
[DISP_CC_MDSS_AHB_CLK_SRC] = &disp_cc_mdss_ahb_clk_src.clkr, |
|
[DISP_CC_MDSS_BYTE0_CLK] = &disp_cc_mdss_byte0_clk.clkr, |
|
[DISP_CC_MDSS_BYTE0_CLK_SRC] = &disp_cc_mdss_byte0_clk_src.clkr, |
|
[DISP_CC_MDSS_BYTE0_DIV_CLK_SRC] = &disp_cc_mdss_byte0_div_clk_src.clkr, |
|
[DISP_CC_MDSS_BYTE0_INTF_CLK] = &disp_cc_mdss_byte0_intf_clk.clkr, |
|
[DISP_CC_MDSS_DP_AUX_CLK] = &disp_cc_mdss_dp_aux_clk.clkr, |
|
[DISP_CC_MDSS_DP_AUX_CLK_SRC] = &disp_cc_mdss_dp_aux_clk_src.clkr, |
|
[DISP_CC_MDSS_DP_CRYPTO_CLK] = &disp_cc_mdss_dp_crypto_clk.clkr, |
|
[DISP_CC_MDSS_DP_CRYPTO_CLK_SRC] = &disp_cc_mdss_dp_crypto_clk_src.clkr, |
|
[DISP_CC_MDSS_DP_LINK_CLK] = &disp_cc_mdss_dp_link_clk.clkr, |
|
[DISP_CC_MDSS_DP_LINK_CLK_SRC] = &disp_cc_mdss_dp_link_clk_src.clkr, |
|
[DISP_CC_MDSS_DP_LINK_DIV_CLK_SRC] = |
|
&disp_cc_mdss_dp_link_div_clk_src.clkr, |
|
[DISP_CC_MDSS_DP_LINK_INTF_CLK] = &disp_cc_mdss_dp_link_intf_clk.clkr, |
|
[DISP_CC_MDSS_DP_PIXEL_CLK] = &disp_cc_mdss_dp_pixel_clk.clkr, |
|
[DISP_CC_MDSS_DP_PIXEL_CLK_SRC] = &disp_cc_mdss_dp_pixel_clk_src.clkr, |
|
[DISP_CC_MDSS_ESC0_CLK] = &disp_cc_mdss_esc0_clk.clkr, |
|
[DISP_CC_MDSS_ESC0_CLK_SRC] = &disp_cc_mdss_esc0_clk_src.clkr, |
|
[DISP_CC_MDSS_MDP_CLK] = &disp_cc_mdss_mdp_clk.clkr, |
|
[DISP_CC_MDSS_MDP_CLK_SRC] = &disp_cc_mdss_mdp_clk_src.clkr, |
|
[DISP_CC_MDSS_MDP_LUT_CLK] = &disp_cc_mdss_mdp_lut_clk.clkr, |
|
[DISP_CC_MDSS_NON_GDSC_AHB_CLK] = &disp_cc_mdss_non_gdsc_ahb_clk.clkr, |
|
[DISP_CC_MDSS_PCLK0_CLK] = &disp_cc_mdss_pclk0_clk.clkr, |
|
[DISP_CC_MDSS_PCLK0_CLK_SRC] = &disp_cc_mdss_pclk0_clk_src.clkr, |
|
[DISP_CC_MDSS_ROT_CLK] = &disp_cc_mdss_rot_clk.clkr, |
|
[DISP_CC_MDSS_ROT_CLK_SRC] = &disp_cc_mdss_rot_clk_src.clkr, |
|
[DISP_CC_MDSS_RSCC_AHB_CLK] = &disp_cc_mdss_rscc_ahb_clk.clkr, |
|
[DISP_CC_MDSS_RSCC_VSYNC_CLK] = &disp_cc_mdss_rscc_vsync_clk.clkr, |
|
[DISP_CC_MDSS_VSYNC_CLK] = &disp_cc_mdss_vsync_clk.clkr, |
|
[DISP_CC_MDSS_VSYNC_CLK_SRC] = &disp_cc_mdss_vsync_clk_src.clkr, |
|
[DISP_CC_PLL0] = &disp_cc_pll0.clkr, |
|
[DISP_CC_SLEEP_CLK] = &disp_cc_sleep_clk.clkr, |
|
[DISP_CC_XO_CLK] = &disp_cc_xo_clk.clkr, |
|
}; |
|
|
|
static struct gdsc *disp_cc_sm6350_gdscs[] = { |
|
[MDSS_GDSC] = &mdss_gdsc, |
|
}; |
|
|
|
static const struct regmap_config disp_cc_sm6350_regmap_config = { |
|
.reg_bits = 32, |
|
.reg_stride = 4, |
|
.val_bits = 32, |
|
.max_register = 0x10000, |
|
.fast_io = true, |
|
}; |
|
|
|
static const struct qcom_cc_desc disp_cc_sm6350_desc = { |
|
.config = &disp_cc_sm6350_regmap_config, |
|
.clks = disp_cc_sm6350_clocks, |
|
.num_clks = ARRAY_SIZE(disp_cc_sm6350_clocks), |
|
.gdscs = disp_cc_sm6350_gdscs, |
|
.num_gdscs = ARRAY_SIZE(disp_cc_sm6350_gdscs), |
|
}; |
|
|
|
static const struct of_device_id disp_cc_sm6350_match_table[] = { |
|
{ .compatible = "qcom,sm6350-dispcc" }, |
|
{ } |
|
}; |
|
MODULE_DEVICE_TABLE(of, disp_cc_sm6350_match_table); |
|
|
|
static int disp_cc_sm6350_probe(struct platform_device *pdev) |
|
{ |
|
struct regmap *regmap; |
|
|
|
regmap = qcom_cc_map(pdev, &disp_cc_sm6350_desc); |
|
if (IS_ERR(regmap)) |
|
return PTR_ERR(regmap); |
|
|
|
clk_fabia_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll0_config); |
|
|
|
return qcom_cc_really_probe(pdev, &disp_cc_sm6350_desc, regmap); |
|
} |
|
|
|
static struct platform_driver disp_cc_sm6350_driver = { |
|
.probe = disp_cc_sm6350_probe, |
|
.driver = { |
|
.name = "disp_cc-sm6350", |
|
.of_match_table = disp_cc_sm6350_match_table, |
|
}, |
|
}; |
|
|
|
static int __init disp_cc_sm6350_init(void) |
|
{ |
|
return platform_driver_register(&disp_cc_sm6350_driver); |
|
} |
|
subsys_initcall(disp_cc_sm6350_init); |
|
|
|
static void __exit disp_cc_sm6350_exit(void) |
|
{ |
|
platform_driver_unregister(&disp_cc_sm6350_driver); |
|
} |
|
module_exit(disp_cc_sm6350_exit); |
|
|
|
MODULE_DESCRIPTION("QTI DISP_CC SM6350 Driver"); |
|
MODULE_LICENSE("GPL v2");
|
|
|