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46 lines
1.3 KiB
46 lines
1.3 KiB
/* |
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* Xtensa MX interrupt distributor |
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* |
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* This file is subject to the terms and conditions of the GNU General Public |
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* License. See the file "COPYING" in the main directory of this archive |
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* for more details. |
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* |
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* Copyright (C) 2008 - 2013 Tensilica Inc. |
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*/ |
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#ifndef _XTENSA_MXREGS_H |
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#define _XTENSA_MXREGS_H |
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/* |
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* RER/WER at, as Read/write external register |
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* at: value |
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* as: address |
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* |
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* Address Value |
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* 00nn 0...0p..p Interrupt Routing, route IRQ n to processor p |
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* 01pp 0...0d..d 16 bits (d) 'ored' as single IPI to processor p |
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* 0180 0...0m..m Clear enable specified by mask (m) |
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* 0184 0...0m..m Set enable specified by mask (m) |
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* 0190 0...0x..x 8-bit IPI partition register |
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* VVVVVVVVPPPPUUUUUUUUUUUUUUUUU |
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* V (10-bit) Release/Version |
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* P ( 4-bit) Number of cores - 1 |
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* U (18-bit) ID |
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* 01a0 i.......i 32-bit ConfigID |
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* 0200 0...0m..m RunStall core 'n' |
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* 0220 c Cache coherency enabled |
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*/ |
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#define MIROUT(irq) (0x000 + (irq)) |
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#define MIPICAUSE(cpu) (0x100 + (cpu)) |
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#define MIPISET(cause) (0x140 + (cause)) |
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#define MIENG 0x180 |
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#define MIENGSET 0x184 |
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#define MIASG 0x188 /* Read Global Assert Register */ |
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#define MIASGSET 0x18c /* Set Global Addert Regiter */ |
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#define MIPIPART 0x190 |
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#define SYSCFGID 0x1a0 |
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#define MPSCORE 0x200 |
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#define CCON 0x220 |
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#endif /* _XTENSA_MXREGS_H */
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