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245 lines
5.1 KiB
245 lines
5.1 KiB
/* |
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* arch/xtensa/include/asm/initialize_mmu.h |
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* |
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* Initializes MMU: |
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* |
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* For the new V3 MMU we remap the TLB from virtual == physical |
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* to the standard Linux mapping used in earlier MMU's. |
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* |
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* For the MMU we also support a new configuration register that |
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* specifies how the S32C1I instruction operates with the cache |
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* controller. |
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* |
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* This file is subject to the terms and conditions of the GNU General |
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* Public License. See the file "COPYING" in the main directory of |
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* this archive for more details. |
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* |
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* Copyright (C) 2008 - 2012 Tensilica, Inc. |
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* |
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* Marc Gauthier <[email protected]> |
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* Pete Delaney <[email protected]> |
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*/ |
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#ifndef _XTENSA_INITIALIZE_MMU_H |
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#define _XTENSA_INITIALIZE_MMU_H |
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#include <linux/init.h> |
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#include <linux/pgtable.h> |
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#include <asm/vectors.h> |
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#if XCHAL_HAVE_PTP_MMU |
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#define CA_BYPASS (_PAGE_CA_BYPASS | _PAGE_HW_WRITE | _PAGE_HW_EXEC) |
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#define CA_WRITEBACK (_PAGE_CA_WB | _PAGE_HW_WRITE | _PAGE_HW_EXEC) |
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#else |
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#define CA_WRITEBACK (0x4) |
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#endif |
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#ifdef __ASSEMBLY__ |
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#define XTENSA_HWVERSION_RC_2009_0 230000 |
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.macro initialize_mmu |
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#if XCHAL_HAVE_S32C1I && (XCHAL_HW_MIN_VERSION >= XTENSA_HWVERSION_RC_2009_0) |
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/* |
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* We Have Atomic Operation Control (ATOMCTL) Register; Initialize it. |
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* For details see Documentation/xtensa/atomctl.rst |
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*/ |
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#if XCHAL_DCACHE_IS_COHERENT |
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movi a3, 0x25 /* For SMP/MX -- internal for writeback, |
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* RCW otherwise |
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*/ |
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#else |
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movi a3, 0x29 /* non-MX -- Most cores use Std Memory |
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* Controlers which usually can't use RCW |
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*/ |
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#endif |
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wsr a3, atomctl |
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#endif /* XCHAL_HAVE_S32C1I && |
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* (XCHAL_HW_MIN_VERSION >= XTENSA_HWVERSION_RC_2009_0) |
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*/ |
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#if defined(CONFIG_MMU) && XCHAL_HAVE_PTP_MMU && XCHAL_HAVE_SPANNING_WAY |
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/* |
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* Have MMU v3 |
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*/ |
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#if !XCHAL_HAVE_VECBASE |
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# error "MMU v3 requires reloc vectors" |
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#endif |
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movi a1, 0 |
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_call0 1f |
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_j 2f |
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.align 4 |
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1: |
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#if CONFIG_KERNEL_LOAD_ADDRESS < 0x40000000ul |
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#define TEMP_MAPPING_VADDR 0x40000000 |
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#else |
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#define TEMP_MAPPING_VADDR 0x00000000 |
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#endif |
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/* Step 1: invalidate mapping at 0x40000000..0x5FFFFFFF. */ |
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movi a2, TEMP_MAPPING_VADDR | XCHAL_SPANNING_WAY |
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idtlb a2 |
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iitlb a2 |
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isync |
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/* Step 2: map 0x40000000..0x47FFFFFF to paddr containing this code |
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* and jump to the new mapping. |
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*/ |
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srli a3, a0, 27 |
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slli a3, a3, 27 |
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addi a3, a3, CA_BYPASS |
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addi a7, a2, 5 - XCHAL_SPANNING_WAY |
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wdtlb a3, a7 |
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witlb a3, a7 |
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isync |
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slli a4, a0, 5 |
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srli a4, a4, 5 |
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addi a5, a2, -XCHAL_SPANNING_WAY |
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add a4, a4, a5 |
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jx a4 |
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/* Step 3: unmap everything other than current area. |
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* Start at 0x60000000, wrap around, and end with 0x20000000 |
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*/ |
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2: movi a4, 0x20000000 |
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add a5, a2, a4 |
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3: idtlb a5 |
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iitlb a5 |
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add a5, a5, a4 |
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bne a5, a2, 3b |
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/* Step 4: Setup MMU with the requested static mappings. */ |
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movi a6, 0x01000000 |
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wsr a6, ITLBCFG |
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wsr a6, DTLBCFG |
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isync |
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movi a5, XCHAL_KSEG_CACHED_VADDR + XCHAL_KSEG_TLB_WAY |
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movi a4, XCHAL_KSEG_PADDR + CA_WRITEBACK |
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wdtlb a4, a5 |
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witlb a4, a5 |
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movi a5, XCHAL_KSEG_BYPASS_VADDR + XCHAL_KSEG_TLB_WAY |
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movi a4, XCHAL_KSEG_PADDR + CA_BYPASS |
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wdtlb a4, a5 |
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witlb a4, a5 |
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#ifdef CONFIG_XTENSA_KSEG_512M |
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movi a5, XCHAL_KSEG_CACHED_VADDR + 0x10000000 + XCHAL_KSEG_TLB_WAY |
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movi a4, XCHAL_KSEG_PADDR + 0x10000000 + CA_WRITEBACK |
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wdtlb a4, a5 |
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witlb a4, a5 |
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movi a5, XCHAL_KSEG_BYPASS_VADDR + 0x10000000 + XCHAL_KSEG_TLB_WAY |
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movi a4, XCHAL_KSEG_PADDR + 0x10000000 + CA_BYPASS |
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wdtlb a4, a5 |
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witlb a4, a5 |
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#endif |
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movi a5, XCHAL_KIO_CACHED_VADDR + XCHAL_KIO_TLB_WAY |
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movi a4, XCHAL_KIO_DEFAULT_PADDR + CA_WRITEBACK |
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wdtlb a4, a5 |
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witlb a4, a5 |
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movi a5, XCHAL_KIO_BYPASS_VADDR + XCHAL_KIO_TLB_WAY |
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movi a4, XCHAL_KIO_DEFAULT_PADDR + CA_BYPASS |
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wdtlb a4, a5 |
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witlb a4, a5 |
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isync |
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/* Jump to self, using final mappings. */ |
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movi a4, 1f |
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jx a4 |
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1: |
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/* Step 5: remove temporary mapping. */ |
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idtlb a7 |
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iitlb a7 |
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isync |
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movi a0, 0 |
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wsr a0, ptevaddr |
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rsync |
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#endif /* defined(CONFIG_MMU) && XCHAL_HAVE_PTP_MMU && |
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XCHAL_HAVE_SPANNING_WAY */ |
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.endm |
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.macro initialize_cacheattr |
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#if !defined(CONFIG_MMU) && (XCHAL_HAVE_TLBS || XCHAL_HAVE_MPU) |
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#if CONFIG_MEMMAP_CACHEATTR == 0x22222222 && XCHAL_HAVE_PTP_MMU |
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#error Default MEMMAP_CACHEATTR of 0x22222222 does not work with full MMU. |
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#endif |
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#if XCHAL_HAVE_MPU |
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__REFCONST |
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.align 4 |
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.Lattribute_table: |
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.long 0x000000, 0x1fff00, 0x1ddf00, 0x1eef00 |
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.long 0x006600, 0x000000, 0x000000, 0x000000 |
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.long 0x000000, 0x000000, 0x000000, 0x000000 |
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.long 0x000000, 0x000000, 0x000000, 0x000000 |
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.previous |
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movi a3, .Lattribute_table |
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movi a4, CONFIG_MEMMAP_CACHEATTR |
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movi a5, 1 |
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movi a6, XCHAL_MPU_ENTRIES |
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movi a10, 0x20000000 |
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movi a11, -1 |
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1: |
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sub a5, a5, a10 |
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extui a8, a4, 28, 4 |
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beq a8, a11, 2f |
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addi a6, a6, -1 |
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mov a11, a8 |
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2: |
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addx4 a9, a8, a3 |
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l32i a9, a9, 0 |
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or a9, a9, a6 |
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wptlb a9, a5 |
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slli a4, a4, 4 |
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bgeu a5, a10, 1b |
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#else |
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movi a5, XCHAL_SPANNING_WAY |
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movi a6, ~_PAGE_ATTRIB_MASK |
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movi a4, CONFIG_MEMMAP_CACHEATTR |
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movi a8, 0x20000000 |
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1: |
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rdtlb1 a3, a5 |
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xor a3, a3, a4 |
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and a3, a3, a6 |
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xor a3, a3, a4 |
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wdtlb a3, a5 |
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ritlb1 a3, a5 |
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xor a3, a3, a4 |
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and a3, a3, a6 |
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xor a3, a3, a4 |
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witlb a3, a5 |
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add a5, a5, a8 |
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srli a4, a4, 4 |
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bgeu a5, a8, 1b |
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isync |
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#endif |
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#endif |
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.endm |
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#endif /*__ASSEMBLY__*/ |
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#endif /* _XTENSA_INITIALIZE_MMU_H */
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