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428 lines
7.6 KiB
428 lines
7.6 KiB
// SPDX-License-Identifier: GPL-2.0+ |
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/* |
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* dts file for Xilinx ZynqMP zc1751-xm015-dc1 |
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* |
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* (C) Copyright 2015 - 2021, Xilinx, Inc. |
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* |
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* Michal Simek <[email protected]> |
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*/ |
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/dts-v1/; |
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#include "zynqmp.dtsi" |
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#include "zynqmp-clk-ccf.dtsi" |
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#include <dt-bindings/phy/phy.h> |
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#include <dt-bindings/gpio/gpio.h> |
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#include <dt-bindings/pinctrl/pinctrl-zynqmp.h> |
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/ { |
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model = "ZynqMP zc1751-xm015-dc1 RevA"; |
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compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp"; |
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aliases { |
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ethernet0 = &gem3; |
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i2c0 = &i2c1; |
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mmc0 = &sdhci0; |
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mmc1 = &sdhci1; |
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rtc0 = &rtc; |
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serial0 = &uart0; |
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spi0 = &qspi; |
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usb0 = &usb0; |
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}; |
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chosen { |
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bootargs = "earlycon"; |
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stdout-path = "serial0:115200n8"; |
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}; |
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memory@0 { |
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device_type = "memory"; |
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reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>; |
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}; |
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clock_si5338_0: clk27 { /* u55 SI5338-GM */ |
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compatible = "fixed-clock"; |
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#clock-cells = <0>; |
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clock-frequency = <27000000>; |
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}; |
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clock_si5338_2: clk26 { |
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compatible = "fixed-clock"; |
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#clock-cells = <0>; |
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clock-frequency = <26000000>; |
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}; |
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clock_si5338_3: clk150 { |
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compatible = "fixed-clock"; |
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#clock-cells = <0>; |
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clock-frequency = <150000000>; |
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}; |
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}; |
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&fpd_dma_chan1 { |
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status = "okay"; |
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}; |
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&fpd_dma_chan2 { |
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status = "okay"; |
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}; |
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&fpd_dma_chan3 { |
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status = "okay"; |
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}; |
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&fpd_dma_chan4 { |
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status = "okay"; |
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}; |
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&fpd_dma_chan5 { |
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status = "okay"; |
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}; |
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&fpd_dma_chan6 { |
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status = "okay"; |
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}; |
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&fpd_dma_chan7 { |
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status = "okay"; |
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}; |
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&fpd_dma_chan8 { |
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status = "okay"; |
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}; |
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&gem3 { |
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status = "okay"; |
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phy-handle = <&phy0>; |
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phy-mode = "rgmii-id"; |
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pinctrl-names = "default"; |
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pinctrl-0 = <&pinctrl_gem3_default>; |
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phy0: ethernet-phy@0 { |
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reg = <0>; |
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}; |
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}; |
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&gpio { |
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status = "okay"; |
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pinctrl-names = "default"; |
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pinctrl-0 = <&pinctrl_gpio_default>; |
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}; |
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&i2c1 { |
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status = "okay"; |
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clock-frequency = <400000>; |
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pinctrl-names = "default", "gpio"; |
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pinctrl-0 = <&pinctrl_i2c1_default>; |
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pinctrl-1 = <&pinctrl_i2c1_gpio>; |
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scl-gpios = <&gpio 36 GPIO_ACTIVE_HIGH>; |
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sda-gpios = <&gpio 37 GPIO_ACTIVE_HIGH>; |
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eeprom: eeprom@55 { |
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compatible = "atmel,24c64"; /* 24AA64 */ |
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reg = <0x55>; |
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}; |
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}; |
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&pinctrl0 { |
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status = "okay"; |
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pinctrl_i2c1_default: i2c1-default { |
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mux { |
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groups = "i2c1_9_grp"; |
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function = "i2c1"; |
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}; |
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conf { |
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groups = "i2c1_9_grp"; |
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bias-pull-up; |
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slew-rate = <SLEW_RATE_SLOW>; |
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power-source = <IO_STANDARD_LVCMOS18>; |
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}; |
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}; |
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pinctrl_i2c1_gpio: i2c1-gpio { |
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mux { |
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groups = "gpio0_36_grp", "gpio0_37_grp"; |
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function = "gpio0"; |
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}; |
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conf { |
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groups = "gpio0_36_grp", "gpio0_37_grp"; |
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slew-rate = <SLEW_RATE_SLOW>; |
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power-source = <IO_STANDARD_LVCMOS18>; |
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}; |
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}; |
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pinctrl_uart0_default: uart0-default { |
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mux { |
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groups = "uart0_8_grp"; |
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function = "uart0"; |
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}; |
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conf { |
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groups = "uart0_8_grp"; |
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slew-rate = <SLEW_RATE_SLOW>; |
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power-source = <IO_STANDARD_LVCMOS18>; |
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}; |
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conf-rx { |
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pins = "MIO34"; |
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bias-high-impedance; |
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}; |
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conf-tx { |
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pins = "MIO35"; |
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bias-disable; |
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}; |
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}; |
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pinctrl_usb0_default: usb0-default { |
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mux { |
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groups = "usb0_0_grp"; |
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function = "usb0"; |
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}; |
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conf { |
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groups = "usb0_0_grp"; |
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slew-rate = <SLEW_RATE_SLOW>; |
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power-source = <IO_STANDARD_LVCMOS18>; |
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}; |
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conf-rx { |
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pins = "MIO52", "MIO53", "MIO55"; |
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bias-high-impedance; |
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}; |
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conf-tx { |
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pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", |
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"MIO60", "MIO61", "MIO62", "MIO63"; |
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bias-disable; |
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}; |
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}; |
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pinctrl_gem3_default: gem3-default { |
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mux { |
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function = "ethernet3"; |
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groups = "ethernet3_0_grp"; |
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}; |
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conf { |
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groups = "ethernet3_0_grp"; |
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slew-rate = <SLEW_RATE_SLOW>; |
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power-source = <IO_STANDARD_LVCMOS18>; |
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}; |
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conf-rx { |
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pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74", |
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"MIO75"; |
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bias-high-impedance; |
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low-power-disable; |
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}; |
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conf-tx { |
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pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68", |
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"MIO69"; |
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bias-disable; |
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low-power-enable; |
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}; |
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mux-mdio { |
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function = "mdio3"; |
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groups = "mdio3_0_grp"; |
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}; |
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conf-mdio { |
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groups = "mdio3_0_grp"; |
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slew-rate = <SLEW_RATE_SLOW>; |
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power-source = <IO_STANDARD_LVCMOS18>; |
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bias-disable; |
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}; |
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}; |
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pinctrl_sdhci0_default: sdhci0-default { |
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mux { |
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groups = "sdio0_0_grp"; |
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function = "sdio0"; |
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}; |
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conf { |
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groups = "sdio0_0_grp"; |
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slew-rate = <SLEW_RATE_SLOW>; |
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power-source = <IO_STANDARD_LVCMOS18>; |
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bias-disable; |
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}; |
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mux-cd { |
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groups = "sdio0_cd_0_grp"; |
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function = "sdio0_cd"; |
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}; |
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conf-cd { |
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groups = "sdio0_cd_0_grp"; |
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bias-high-impedance; |
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bias-pull-up; |
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slew-rate = <SLEW_RATE_SLOW>; |
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power-source = <IO_STANDARD_LVCMOS18>; |
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}; |
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mux-wp { |
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groups = "sdio0_wp_0_grp"; |
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function = "sdio0_wp"; |
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}; |
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conf-wp { |
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groups = "sdio0_wp_0_grp"; |
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bias-high-impedance; |
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bias-pull-up; |
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slew-rate = <SLEW_RATE_SLOW>; |
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power-source = <IO_STANDARD_LVCMOS18>; |
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}; |
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}; |
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pinctrl_sdhci1_default: sdhci1-default { |
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mux { |
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groups = "sdio1_0_grp"; |
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function = "sdio1"; |
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}; |
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conf { |
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groups = "sdio1_0_grp"; |
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slew-rate = <SLEW_RATE_SLOW>; |
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power-source = <IO_STANDARD_LVCMOS18>; |
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bias-disable; |
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}; |
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mux-cd { |
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groups = "sdio1_cd_0_grp"; |
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function = "sdio1_cd"; |
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}; |
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conf-cd { |
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groups = "sdio1_cd_0_grp"; |
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bias-high-impedance; |
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bias-pull-up; |
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slew-rate = <SLEW_RATE_SLOW>; |
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power-source = <IO_STANDARD_LVCMOS18>; |
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}; |
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mux-wp { |
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groups = "sdio1_wp_0_grp"; |
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function = "sdio1_wp"; |
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}; |
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conf-wp { |
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groups = "sdio1_wp_0_grp"; |
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bias-high-impedance; |
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bias-pull-up; |
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slew-rate = <SLEW_RATE_SLOW>; |
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power-source = <IO_STANDARD_LVCMOS18>; |
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}; |
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}; |
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pinctrl_gpio_default: gpio-default { |
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mux { |
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function = "gpio0"; |
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groups = "gpio0_38_grp"; |
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}; |
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conf { |
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groups = "gpio0_38_grp"; |
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bias-disable; |
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slew-rate = <SLEW_RATE_SLOW>; |
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power-source = <IO_STANDARD_LVCMOS18>; |
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}; |
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}; |
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}; |
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&psgtr { |
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status = "okay"; |
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/* dp, usb3, sata */ |
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clocks = <&clock_si5338_0>, <&clock_si5338_2>, <&clock_si5338_3>; |
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clock-names = "ref1", "ref2", "ref3"; |
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}; |
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&qspi { |
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status = "okay"; |
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flash@0 { |
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compatible = "m25p80", "jedec,spi-nor"; /* Micron MT25QU512ABB8ESF */ |
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#address-cells = <1>; |
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#size-cells = <1>; |
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reg = <0x0>; |
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spi-tx-bus-width = <1>; |
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spi-rx-bus-width = <4>; |
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spi-max-frequency = <108000000>; /* Based on DC1 spec */ |
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}; |
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}; |
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&rtc { |
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status = "okay"; |
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}; |
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&sata { |
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status = "okay"; |
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/* SATA phy OOB timing settings */ |
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ceva,p0-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>; |
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ceva,p0-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>; |
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ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; |
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ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; |
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ceva,p1-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>; |
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ceva,p1-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>; |
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ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; |
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ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; |
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phy-names = "sata-phy"; |
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phys = <&psgtr 3 PHY_TYPE_SATA 1 3>; |
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}; |
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/* eMMC */ |
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&sdhci0 { |
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status = "okay"; |
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pinctrl-names = "default"; |
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pinctrl-0 = <&pinctrl_sdhci0_default>; |
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bus-width = <8>; |
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xlnx,mio-bank = <0>; |
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}; |
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/* SD1 with level shifter */ |
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&sdhci1 { |
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status = "okay"; |
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/* |
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* This property should be removed for supporting UHS mode |
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*/ |
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no-1-8-v; |
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pinctrl-names = "default"; |
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pinctrl-0 = <&pinctrl_sdhci1_default>; |
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xlnx,mio-bank = <1>; |
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}; |
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&uart0 { |
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status = "okay"; |
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pinctrl-names = "default"; |
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pinctrl-0 = <&pinctrl_uart0_default>; |
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}; |
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/* ULPI SMSC USB3320 */ |
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&usb0 { |
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status = "okay"; |
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pinctrl-names = "default"; |
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pinctrl-0 = <&pinctrl_usb0_default>; |
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phy-names = "usb3-phy"; |
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phys = <&psgtr 2 PHY_TYPE_USB3 0 2>; |
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}; |
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&dwc3_0 { |
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status = "okay"; |
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dr_mode = "host"; |
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snps,usb3_lpm_capable; |
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maximum-speed = "super-speed"; |
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}; |
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&zynqmp_dpdma { |
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status = "okay"; |
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}; |
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&zynqmp_dpsub { |
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status = "okay"; |
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phy-names = "dp-phy0", "dp-phy1"; |
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phys = <&psgtr 1 PHY_TYPE_DP 0 0>, |
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<&psgtr 0 PHY_TYPE_DP 1 1>; |
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};
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