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56 lines
1003 B
56 lines
1003 B
// SPDX-License-Identifier: GPL-2.0+ |
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/* |
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* dts file for Xilinx ZynqMP ZC1254 |
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* |
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* (C) Copyright 2015 - 2021, Xilinx, Inc. |
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* |
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* Michal Simek <[email protected]> |
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* Siva Durga Prasad Paladugu <[email protected]> |
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*/ |
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/dts-v1/; |
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#include "zynqmp.dtsi" |
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#include "zynqmp-clk-ccf.dtsi" |
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/ { |
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model = "ZynqMP ZC1254 RevA"; |
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compatible = "xlnx,zynqmp-zc1254-revA", "xlnx,zynqmp-zc1254", "xlnx,zynqmp"; |
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aliases { |
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serial0 = &uart0; |
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serial1 = &dcc; |
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spi0 = &qspi; |
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}; |
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chosen { |
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bootargs = "earlycon"; |
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stdout-path = "serial0:115200n8"; |
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}; |
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memory@0 { |
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device_type = "memory"; |
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reg = <0x0 0x0 0x0 0x80000000>; |
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}; |
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}; |
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&dcc { |
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status = "okay"; |
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}; |
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&qspi { |
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status = "okay"; |
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flash@0 { |
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compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ |
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#address-cells = <1>; |
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#size-cells = <1>; |
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reg = <0x0>; |
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spi-tx-bus-width = <1>; |
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spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ |
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spi-max-frequency = <108000000>; /* Based on DC1 spec */ |
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}; |
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}; |
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&uart0 { |
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status = "okay"; |
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};
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