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434 lines
12 KiB
434 lines
12 KiB
// SPDX-License-Identifier: (GPL-2.0+ OR MIT) |
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/* |
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* Copyright 2021 NXP |
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*/ |
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#include <dt-bindings/clock/imx8ulp-clock.h> |
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#include <dt-bindings/gpio/gpio.h> |
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#include <dt-bindings/interrupt-controller/arm-gic.h> |
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#include <dt-bindings/power/imx8ulp-power.h> |
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#include "imx8ulp-pinfunc.h" |
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/ { |
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interrupt-parent = <&gic>; |
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#address-cells = <2>; |
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#size-cells = <2>; |
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aliases { |
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gpio0 = &gpiod; |
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gpio1 = &gpioe; |
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gpio2 = &gpiof; |
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mmc0 = &usdhc0; |
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mmc1 = &usdhc1; |
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mmc2 = &usdhc2; |
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serial0 = &lpuart4; |
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serial1 = &lpuart5; |
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serial2 = &lpuart6; |
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serial3 = &lpuart7; |
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}; |
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cpus { |
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#address-cells = <2>; |
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#size-cells = <0>; |
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A35_0: cpu@0 { |
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device_type = "cpu"; |
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compatible = "arm,cortex-a35"; |
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reg = <0x0 0x0>; |
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enable-method = "psci"; |
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next-level-cache = <&A35_L2>; |
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}; |
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A35_1: cpu@1 { |
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device_type = "cpu"; |
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compatible = "arm,cortex-a35"; |
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reg = <0x0 0x1>; |
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enable-method = "psci"; |
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next-level-cache = <&A35_L2>; |
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}; |
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A35_L2: l2-cache0 { |
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compatible = "cache"; |
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}; |
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}; |
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gic: interrupt-controller@2d400000 { |
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compatible = "arm,gic-v3"; |
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reg = <0x0 0x2d400000 0 0x10000>, /* GIC Dist */ |
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<0x0 0x2d440000 0 0xc0000>; /* GICR (RD_base + SGI_base) */ |
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#interrupt-cells = <3>; |
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interrupt-controller; |
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interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; |
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}; |
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psci { |
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compatible = "arm,psci-1.0"; |
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method = "smc"; |
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}; |
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timer { |
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compatible = "arm,armv8-timer"; |
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interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* Physical Secure */ |
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<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* Physical Non-Secure */ |
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<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* Virtual */ |
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<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* Hypervisor */ |
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}; |
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frosc: clock-frosc { |
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compatible = "fixed-clock"; |
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clock-frequency = <192000000>; |
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clock-output-names = "frosc"; |
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#clock-cells = <0>; |
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}; |
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lposc: clock-lposc { |
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compatible = "fixed-clock"; |
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clock-frequency = <1000000>; |
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clock-output-names = "lposc"; |
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#clock-cells = <0>; |
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}; |
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rosc: clock-rosc { |
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compatible = "fixed-clock"; |
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clock-frequency = <32768>; |
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clock-output-names = "rosc"; |
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#clock-cells = <0>; |
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}; |
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sosc: clock-sosc { |
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compatible = "fixed-clock"; |
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clock-frequency = <24000000>; |
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clock-output-names = "sosc"; |
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#clock-cells = <0>; |
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}; |
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sram@2201f000 { |
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compatible = "mmio-sram"; |
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reg = <0x0 0x2201f000 0x0 0x1000>; |
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#address-cells = <1>; |
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#size-cells = <1>; |
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ranges = <0 0x0 0x2201f000 0x1000>; |
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scmi_buf: scmi-buf@0 { |
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compatible = "arm,scmi-shmem"; |
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reg = <0x0 0x400>; |
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}; |
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}; |
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firmware { |
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scmi { |
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compatible = "arm,scmi-smc"; |
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arm,smc-id = <0xc20000fe>; |
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#address-cells = <1>; |
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#size-cells = <0>; |
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shmem = <&scmi_buf>; |
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scmi_devpd: protocol@11 { |
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reg = <0x11>; |
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#power-domain-cells = <1>; |
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}; |
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scmi_sensor: protocol@15 { |
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reg = <0x15>; |
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#thermal-sensor-cells = <1>; |
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}; |
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}; |
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}; |
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soc@0 { |
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compatible = "simple-bus"; |
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#address-cells = <1>; |
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#size-cells = <1>; |
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ranges = <0x0 0x0 0x0 0x40000000>; |
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per_bridge3: bus@29000000 { |
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compatible = "simple-bus"; |
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reg = <0x29000000 0x800000>; |
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#address-cells = <1>; |
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#size-cells = <1>; |
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ranges; |
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wdog3: watchdog@292a0000 { |
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compatible = "fsl,imx8ulp-wdt", "fsl,imx7ulp-wdt"; |
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reg = <0x292a0000 0x10000>; |
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interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; |
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clocks = <&pcc3 IMX8ULP_CLK_WDOG3>; |
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assigned-clocks = <&pcc3 IMX8ULP_CLK_WDOG3>; |
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assigned-clock-parents = <&cgc1 IMX8ULP_CLK_SOSC_DIV2>; |
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timeout-sec = <40>; |
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}; |
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cgc1: clock-controller@292c0000 { |
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compatible = "fsl,imx8ulp-cgc1"; |
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reg = <0x292c0000 0x10000>; |
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clocks = <&rosc>, <&sosc>, <&frosc>, <&lposc>; |
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clock-names = "rosc", "sosc", "frosc", "lposc"; |
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#clock-cells = <1>; |
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}; |
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pcc3: clock-controller@292d0000 { |
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compatible = "fsl,imx8ulp-pcc3"; |
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reg = <0x292d0000 0x10000>; |
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#clock-cells = <1>; |
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}; |
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tpm5: tpm@29340000 { |
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compatible = "fsl,imx8ulp-tpm", "fsl,imx7ulp-tpm"; |
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reg = <0x29340000 0x1000>; |
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interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; |
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clocks = <&pcc3 IMX8ULP_CLK_TPM5>, |
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<&pcc3 IMX8ULP_CLK_TPM5>; |
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clock-names = "ipg", "per"; |
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status = "disabled"; |
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}; |
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lpi2c4: i2c@29370000 { |
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compatible = "fsl,imx8ulp-lpi2c", "fsl,imx7ulp-lpi2c"; |
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reg = <0x29370000 0x10000>; |
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interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; |
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clocks = <&pcc3 IMX8ULP_CLK_LPI2C4>, |
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<&pcc3 IMX8ULP_CLK_LPI2C4>; |
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clock-names = "per", "ipg"; |
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assigned-clocks = <&pcc3 IMX8ULP_CLK_LPI2C4>; |
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assigned-clock-parents = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>; |
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assigned-clock-rates = <48000000>; |
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status = "disabled"; |
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}; |
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lpi2c5: i2c@29380000 { |
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compatible = "fsl,imx8ulp-lpi2c", "fsl,imx7ulp-lpi2c"; |
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reg = <0x29380000 0x10000>; |
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interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; |
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clocks = <&pcc3 IMX8ULP_CLK_LPI2C5>, |
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<&pcc3 IMX8ULP_CLK_LPI2C5>; |
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clock-names = "per", "ipg"; |
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assigned-clocks = <&pcc3 IMX8ULP_CLK_LPI2C5>; |
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assigned-clock-parents = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>; |
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assigned-clock-rates = <48000000>; |
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status = "disabled"; |
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}; |
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lpuart4: serial@29390000 { |
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compatible = "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart"; |
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reg = <0x29390000 0x1000>; |
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interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; |
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clocks = <&pcc3 IMX8ULP_CLK_LPUART4>; |
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clock-names = "ipg"; |
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status = "disabled"; |
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}; |
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lpuart5: serial@293a0000 { |
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compatible = "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart"; |
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reg = <0x293a0000 0x1000>; |
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interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; |
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clocks = <&pcc3 IMX8ULP_CLK_LPUART5>; |
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clock-names = "ipg"; |
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status = "disabled"; |
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}; |
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lpspi4: spi@293b0000 { |
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#address-cells = <1>; |
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#size-cells = <0>; |
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compatible = "fsl,imx8ulp-spi", "fsl,imx7ulp-spi"; |
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reg = <0x293b0000 0x10000>; |
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interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; |
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clocks = <&pcc3 IMX8ULP_CLK_LPSPI4>, |
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<&pcc3 IMX8ULP_CLK_LPSPI4>; |
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clock-names = "per", "ipg"; |
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assigned-clocks = <&pcc3 IMX8ULP_CLK_LPSPI4>; |
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assigned-clock-parents = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>; |
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assigned-clock-rates = <16000000>; |
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status = "disabled"; |
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}; |
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lpspi5: spi@293c0000 { |
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#address-cells = <1>; |
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#size-cells = <0>; |
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compatible = "fsl,imx8ulp-spi", "fsl,imx7ulp-spi"; |
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reg = <0x293c0000 0x10000>; |
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interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; |
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clocks = <&pcc3 IMX8ULP_CLK_LPSPI5>, |
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<&pcc3 IMX8ULP_CLK_LPSPI5>; |
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clock-names = "per", "ipg"; |
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assigned-clocks = <&pcc3 IMX8ULP_CLK_LPSPI5>; |
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assigned-clock-parents = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>; |
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assigned-clock-rates = <16000000>; |
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status = "disabled"; |
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}; |
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}; |
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per_bridge4: bus@29800000 { |
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compatible = "simple-bus"; |
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reg = <0x29800000 0x800000>; |
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#address-cells = <1>; |
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#size-cells = <1>; |
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ranges; |
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pcc4: clock-controller@29800000 { |
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compatible = "fsl,imx8ulp-pcc4"; |
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reg = <0x29800000 0x10000>; |
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#clock-cells = <1>; |
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}; |
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lpi2c6: i2c@29840000 { |
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compatible = "fsl,imx8ulp-lpi2c", "fsl,imx7ulp-lpi2c"; |
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reg = <0x29840000 0x10000>; |
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interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; |
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clocks = <&pcc4 IMX8ULP_CLK_LPI2C6>, |
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<&pcc4 IMX8ULP_CLK_LPI2C6>; |
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clock-names = "per", "ipg"; |
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assigned-clocks = <&pcc4 IMX8ULP_CLK_LPI2C6>; |
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assigned-clock-parents = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>; |
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assigned-clock-rates = <48000000>; |
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status = "disabled"; |
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}; |
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lpi2c7: i2c@29850000 { |
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compatible = "fsl,imx8ulp-lpi2c", "fsl,imx7ulp-lpi2c"; |
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reg = <0x29850000 0x10000>; |
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interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; |
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clocks = <&pcc4 IMX8ULP_CLK_LPI2C7>, |
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<&pcc4 IMX8ULP_CLK_LPI2C7>; |
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clock-names = "per", "ipg"; |
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assigned-clocks = <&pcc4 IMX8ULP_CLK_LPI2C7>; |
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assigned-clock-parents = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>; |
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assigned-clock-rates = <48000000>; |
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status = "disabled"; |
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}; |
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lpuart6: serial@29860000 { |
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compatible = "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart"; |
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reg = <0x29860000 0x1000>; |
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interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; |
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clocks = <&pcc4 IMX8ULP_CLK_LPUART6>; |
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clock-names = "ipg"; |
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status = "disabled"; |
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}; |
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lpuart7: serial@29870000 { |
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compatible = "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart"; |
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reg = <0x29870000 0x1000>; |
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interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; |
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clocks = <&pcc4 IMX8ULP_CLK_LPUART7>; |
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clock-names = "ipg"; |
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status = "disabled"; |
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}; |
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iomuxc1: pinctrl@298c0000 { |
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compatible = "fsl,imx8ulp-iomuxc1"; |
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reg = <0x298c0000 0x10000>; |
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}; |
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usdhc0: mmc@298d0000 { |
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compatible = "fsl,imx8ulp-usdhc", "fsl,imx8mm-usdhc"; |
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reg = <0x298d0000 0x10000>; |
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interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; |
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clocks = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>, |
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<&cgc1 IMX8ULP_CLK_XBAR_AD_DIVPLAT>, |
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<&pcc4 IMX8ULP_CLK_USDHC0>; |
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clock-names = "ipg", "ahb", "per"; |
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power-domains = <&scmi_devpd IMX8ULP_PD_USDHC0>; |
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fsl,tuning-start-tap = <20>; |
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fsl,tuning-step= <2>; |
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bus-width = <4>; |
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status = "disabled"; |
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}; |
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usdhc1: mmc@298e0000 { |
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compatible = "fsl,imx8ulp-usdhc", "fsl,imx8mm-usdhc"; |
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reg = <0x298e0000 0x10000>; |
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interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; |
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clocks = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>, |
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<&cgc1 IMX8ULP_CLK_NIC_PER_DIVPLAT>, |
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<&pcc4 IMX8ULP_CLK_USDHC1>; |
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clock-names = "ipg", "ahb", "per"; |
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power-domains = <&scmi_devpd IMX8ULP_PD_USDHC1>; |
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fsl,tuning-start-tap = <20>; |
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fsl,tuning-step= <2>; |
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bus-width = <4>; |
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status = "disabled"; |
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}; |
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usdhc2: mmc@298f0000 { |
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compatible = "fsl,imx8ulp-usdhc", "fsl,imx8mm-usdhc"; |
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reg = <0x298f0000 0x10000>; |
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interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; |
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clocks = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>, |
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<&cgc1 IMX8ULP_CLK_NIC_PER_DIVPLAT>, |
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<&pcc4 IMX8ULP_CLK_USDHC2>; |
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clock-names = "ipg", "ahb", "per"; |
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power-domains = <&scmi_devpd IMX8ULP_PD_USDHC2_USB1>; |
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fsl,tuning-start-tap = <20>; |
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fsl,tuning-step= <2>; |
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bus-width = <4>; |
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status = "disabled"; |
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}; |
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}; |
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gpioe: gpio@2d000000 { |
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compatible = "fsl,imx8ulp-gpio", "fsl,imx7ulp-gpio"; |
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reg = <0x2d000080 0x1000>, <0x2d000040 0x40>; |
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gpio-controller; |
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#gpio-cells = <2>; |
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interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>; |
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interrupt-controller; |
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#interrupt-cells = <2>; |
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clocks = <&pcc4 IMX8ULP_CLK_RGPIOE>, |
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<&pcc4 IMX8ULP_CLK_PCTLE>; |
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clock-names = "gpio", "port"; |
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gpio-ranges = <&iomuxc1 0 32 24>; |
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}; |
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gpiof: gpio@2d010000 { |
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compatible = "fsl,imx8ulp-gpio", "fsl,imx7ulp-gpio"; |
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reg = <0x2d010080 0x1000>, <0x2d010040 0x40>; |
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gpio-controller; |
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#gpio-cells = <2>; |
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interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; |
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interrupt-controller; |
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#interrupt-cells = <2>; |
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clocks = <&pcc4 IMX8ULP_CLK_RGPIOF>, |
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<&pcc4 IMX8ULP_CLK_PCTLF>; |
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clock-names = "gpio", "port"; |
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gpio-ranges = <&iomuxc1 0 64 32>; |
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}; |
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per_bridge5: bus@2d800000 { |
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compatible = "simple-bus"; |
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reg = <0x2d800000 0x800000>; |
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#address-cells = <1>; |
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#size-cells = <1>; |
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ranges; |
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cgc2: clock-controller@2da60000 { |
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compatible = "fsl,imx8ulp-cgc2"; |
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reg = <0x2da60000 0x10000>; |
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clocks = <&sosc>, <&frosc>; |
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clock-names = "sosc", "frosc"; |
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#clock-cells = <1>; |
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}; |
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pcc5: clock-controller@2da70000 { |
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compatible = "fsl,imx8ulp-pcc5"; |
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reg = <0x2da70000 0x10000>; |
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#clock-cells = <1>; |
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}; |
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}; |
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gpiod: gpio@2e200000 { |
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compatible = "fsl,imx8ulp-gpio", "fsl,imx7ulp-gpio"; |
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reg = <0x2e200080 0x1000>, <0x2e200040 0x40>; |
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gpio-controller; |
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#gpio-cells = <2>; |
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interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; |
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interrupt-controller; |
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#interrupt-cells = <2>; |
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clocks = <&pcc5 IMX8ULP_CLK_RGPIOD>, |
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<&pcc5 IMX8ULP_CLK_RGPIOD>; |
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clock-names = "gpio", "port"; |
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gpio-ranges = <&iomuxc1 0 0 24>; |
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}; |
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}; |
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};
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