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306 lines
7.1 KiB
306 lines
7.1 KiB
/* |
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* arch/arm/mm/cache-tauros2.c - Tauros2 L2 cache controller support |
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* |
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* Copyright (C) 2008 Marvell Semiconductor |
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* |
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* This file is licensed under the terms of the GNU General Public |
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* License version 2. This program is licensed "as is" without any |
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* warranty of any kind, whether express or implied. |
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* |
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* References: |
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* - PJ1 CPU Core Datasheet, |
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* Document ID MV-S104837-01, Rev 0.7, January 24 2008. |
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* - PJ4 CPU Core Datasheet, |
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* Document ID MV-S105190-00, Rev 0.7, March 14 2008. |
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*/ |
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#include <linux/init.h> |
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#include <linux/of.h> |
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#include <linux/of_address.h> |
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#include <asm/cacheflush.h> |
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#include <asm/cp15.h> |
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#include <asm/cputype.h> |
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#include <asm/hardware/cache-tauros2.h> |
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/* CP15 PJ4 Control configuration register */ |
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#define CCR_L2C_PREFETCH_DISABLE BIT(24) |
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#define CCR_L2C_ECC_ENABLE BIT(23) |
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#define CCR_L2C_WAY7_4_DISABLE BIT(21) |
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#define CCR_L2C_BURST8_ENABLE BIT(20) |
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/* |
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* When Tauros2 is used on a CPU that supports the v7 hierarchical |
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* cache operations, the cache handling code in proc-v7.S takes care |
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* of everything, including handling DMA coherency. |
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* |
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* So, we only need to register outer cache operations here if we're |
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* being used on a pre-v7 CPU, and we only need to build support for |
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* outer cache operations into the kernel image if the kernel has been |
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* configured to support a pre-v7 CPU. |
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*/ |
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#ifdef CONFIG_CPU_32v5 |
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/* |
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* Low-level cache maintenance operations. |
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*/ |
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static inline void tauros2_clean_pa(unsigned long addr) |
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{ |
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__asm__("mcr p15, 1, %0, c7, c11, 3" : : "r" (addr)); |
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} |
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static inline void tauros2_clean_inv_pa(unsigned long addr) |
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{ |
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__asm__("mcr p15, 1, %0, c7, c15, 3" : : "r" (addr)); |
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} |
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static inline void tauros2_inv_pa(unsigned long addr) |
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{ |
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__asm__("mcr p15, 1, %0, c7, c7, 3" : : "r" (addr)); |
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} |
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/* |
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* Linux primitives. |
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* |
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* Note that the end addresses passed to Linux primitives are |
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* noninclusive. |
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*/ |
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#define CACHE_LINE_SIZE 32 |
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static void tauros2_inv_range(unsigned long start, unsigned long end) |
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{ |
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/* |
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* Clean and invalidate partial first cache line. |
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*/ |
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if (start & (CACHE_LINE_SIZE - 1)) { |
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tauros2_clean_inv_pa(start & ~(CACHE_LINE_SIZE - 1)); |
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start = (start | (CACHE_LINE_SIZE - 1)) + 1; |
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} |
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/* |
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* Clean and invalidate partial last cache line. |
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*/ |
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if (end & (CACHE_LINE_SIZE - 1)) { |
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tauros2_clean_inv_pa(end & ~(CACHE_LINE_SIZE - 1)); |
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end &= ~(CACHE_LINE_SIZE - 1); |
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} |
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/* |
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* Invalidate all full cache lines between 'start' and 'end'. |
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*/ |
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while (start < end) { |
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tauros2_inv_pa(start); |
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start += CACHE_LINE_SIZE; |
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} |
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dsb(); |
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} |
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static void tauros2_clean_range(unsigned long start, unsigned long end) |
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{ |
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start &= ~(CACHE_LINE_SIZE - 1); |
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while (start < end) { |
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tauros2_clean_pa(start); |
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start += CACHE_LINE_SIZE; |
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} |
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dsb(); |
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} |
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static void tauros2_flush_range(unsigned long start, unsigned long end) |
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{ |
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start &= ~(CACHE_LINE_SIZE - 1); |
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while (start < end) { |
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tauros2_clean_inv_pa(start); |
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start += CACHE_LINE_SIZE; |
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} |
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dsb(); |
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} |
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static void tauros2_disable(void) |
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{ |
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__asm__ __volatile__ ( |
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"mcr p15, 1, %0, c7, c11, 0 @L2 Cache Clean All\n\t" |
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"mrc p15, 0, %0, c1, c0, 0\n\t" |
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"bic %0, %0, #(1 << 26)\n\t" |
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"mcr p15, 0, %0, c1, c0, 0 @Disable L2 Cache\n\t" |
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: : "r" (0x0)); |
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} |
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static void tauros2_resume(void) |
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{ |
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__asm__ __volatile__ ( |
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"mcr p15, 1, %0, c7, c7, 0 @L2 Cache Invalidate All\n\t" |
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"mrc p15, 0, %0, c1, c0, 0\n\t" |
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"orr %0, %0, #(1 << 26)\n\t" |
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"mcr p15, 0, %0, c1, c0, 0 @Enable L2 Cache\n\t" |
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: : "r" (0x0)); |
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} |
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#endif |
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static inline u32 __init read_extra_features(void) |
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{ |
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u32 u; |
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__asm__("mrc p15, 1, %0, c15, c1, 0" : "=r" (u)); |
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return u; |
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} |
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static inline void __init write_extra_features(u32 u) |
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{ |
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__asm__("mcr p15, 1, %0, c15, c1, 0" : : "r" (u)); |
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} |
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static inline int __init cpuid_scheme(void) |
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{ |
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return !!((processor_id & 0x000f0000) == 0x000f0000); |
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} |
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static inline u32 __init read_mmfr3(void) |
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{ |
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u32 mmfr3; |
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__asm__("mrc p15, 0, %0, c0, c1, 7\n" : "=r" (mmfr3)); |
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return mmfr3; |
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} |
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static inline u32 __init read_actlr(void) |
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{ |
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u32 actlr; |
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__asm__("mrc p15, 0, %0, c1, c0, 1\n" : "=r" (actlr)); |
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return actlr; |
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} |
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static inline void __init write_actlr(u32 actlr) |
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{ |
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__asm__("mcr p15, 0, %0, c1, c0, 1\n" : : "r" (actlr)); |
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} |
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static void enable_extra_feature(unsigned int features) |
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{ |
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u32 u; |
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u = read_extra_features(); |
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if (features & CACHE_TAUROS2_PREFETCH_ON) |
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u &= ~CCR_L2C_PREFETCH_DISABLE; |
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else |
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u |= CCR_L2C_PREFETCH_DISABLE; |
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pr_info("Tauros2: %s L2 prefetch.\n", |
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(features & CACHE_TAUROS2_PREFETCH_ON) |
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? "Enabling" : "Disabling"); |
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if (features & CACHE_TAUROS2_LINEFILL_BURST8) |
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u |= CCR_L2C_BURST8_ENABLE; |
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else |
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u &= ~CCR_L2C_BURST8_ENABLE; |
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pr_info("Tauros2: %s burst8 line fill.\n", |
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(features & CACHE_TAUROS2_LINEFILL_BURST8) |
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? "Enabling" : "Disabling"); |
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write_extra_features(u); |
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} |
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static void __init tauros2_internal_init(unsigned int features) |
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{ |
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char *mode = NULL; |
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enable_extra_feature(features); |
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#ifdef CONFIG_CPU_32v5 |
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if ((processor_id & 0xff0f0000) == 0x56050000) { |
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u32 feat; |
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/* |
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* v5 CPUs with Tauros2 have the L2 cache enable bit |
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* located in the CPU Extra Features register. |
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*/ |
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feat = read_extra_features(); |
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if (!(feat & 0x00400000)) { |
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pr_info("Tauros2: Enabling L2 cache.\n"); |
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write_extra_features(feat | 0x00400000); |
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} |
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mode = "ARMv5"; |
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outer_cache.inv_range = tauros2_inv_range; |
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outer_cache.clean_range = tauros2_clean_range; |
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outer_cache.flush_range = tauros2_flush_range; |
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outer_cache.disable = tauros2_disable; |
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outer_cache.resume = tauros2_resume; |
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} |
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#endif |
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#ifdef CONFIG_CPU_32v7 |
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/* |
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* Check whether this CPU has support for the v7 hierarchical |
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* cache ops. (PJ4 is in its v7 personality mode if the MMFR3 |
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* register indicates support for the v7 hierarchical cache |
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* ops.) |
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* |
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* (Although strictly speaking there may exist CPUs that |
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* implement the v7 cache ops but are only ARMv6 CPUs (due to |
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* not complying with all of the other ARMv7 requirements), |
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* there are no real-life examples of Tauros2 being used on |
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* such CPUs as of yet.) |
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*/ |
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if (cpuid_scheme() && (read_mmfr3() & 0xf) == 1) { |
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u32 actlr; |
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/* |
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* When Tauros2 is used in an ARMv7 system, the L2 |
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* enable bit is located in the Auxiliary System Control |
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* Register (which is the only register allowed by the |
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* ARMv7 spec to contain fine-grained cache control bits). |
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*/ |
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actlr = read_actlr(); |
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if (!(actlr & 0x00000002)) { |
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pr_info("Tauros2: Enabling L2 cache.\n"); |
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write_actlr(actlr | 0x00000002); |
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} |
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mode = "ARMv7"; |
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} |
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#endif |
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if (mode == NULL) { |
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pr_crit("Tauros2: Unable to detect CPU mode.\n"); |
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return; |
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} |
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pr_info("Tauros2: L2 cache support initialised " |
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"in %s mode.\n", mode); |
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} |
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#ifdef CONFIG_OF |
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static const struct of_device_id tauros2_ids[] __initconst = { |
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{ .compatible = "marvell,tauros2-cache"}, |
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{} |
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}; |
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#endif |
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void __init tauros2_init(unsigned int features) |
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{ |
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#ifdef CONFIG_OF |
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struct device_node *node; |
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int ret; |
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unsigned int f; |
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node = of_find_matching_node(NULL, tauros2_ids); |
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if (!node) { |
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pr_info("Not found marvell,tauros2-cache, disable it\n"); |
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} else { |
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ret = of_property_read_u32(node, "marvell,tauros2-cache-features", &f); |
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if (ret) { |
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pr_info("Not found marvell,tauros-cache-features property, " |
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"disable extra features\n"); |
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features = 0; |
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} else |
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features = f; |
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} |
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#endif |
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tauros2_internal_init(features); |
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}
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