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Changes included (and more): 1. Dynamic RAM merge 2. Real-time page scan and allocation 3. Cache compression 4. Real-time IRQ checks 5. Dynamic I/O allocation for Java heap 6. Java page migration 7. Contiguous memory allocation 8. Idle pages tracking 9. Per CPU RAM usage tracking 10. ARM NEON scalar multiplication library 11. NEON/ARMv8 crypto extensions 12. NEON SHA, Blake, RIPEMD crypto extensions 13. Parallel NEON crypto engine for multi-algo based CPU stress reduction
121 lines
3.2 KiB
YAML
121 lines
3.2 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/display/samsung/samsung,exynos7-decon.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Samsung Exynos7 SoC Display and Enhancement Controller (DECON)
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maintainers:
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- Inki Dae <inki.dae@samsung.com>
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- Joonyoung Shim <jy0922.shim@samsung.com>
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- Seung-Woo Kim <sw0312.kim@samsung.com>
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- Kyungmin Park <kyungmin.park@samsung.com>
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- Krzysztof Kozlowski <krzk@kernel.org>
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description: |
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DECON (Display and Enhancement Controller) is the Display Controller for the
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Exynos7 series of SoCs which transfers the image data from a video memory
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buffer to an external LCD interface.
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properties:
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compatible:
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const: samsung,exynos7-decon
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clocks:
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minItems: 4
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maxItems: 4
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clock-names:
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items:
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- const: pclk_decon0
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- const: aclk_decon0
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- const: decon0_eclk
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- const: decon0_vclk
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display-timings:
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$ref: ../panel/display-timings.yaml#
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i80-if-timings:
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type: object
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description: timing configuration for lcd i80 interface support
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properties:
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cs-setup:
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$ref: /schemas/types.yaml#/definitions/uint32
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description:
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Clock cycles for the active period of address signal is enabled until
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chip select is enabled.
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default: 0
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wr-active:
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$ref: /schemas/types.yaml#/definitions/uint32
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description:
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Clock cycles for the active period of CS is enabled.
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default: 1
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wr-hold:
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$ref: /schemas/types.yaml#/definitions/uint32
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description:
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Clock cycles for the active period of CS is disabled until write
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signal is disabled.
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default: 0
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wr-setup:
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$ref: /schemas/types.yaml#/definitions/uint32
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description:
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Clock cycles for the active period of CS signal is enabled until
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write signal is enabled.
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default: 0
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interrupts:
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items:
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- description: FIFO level
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- description: VSYNC
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- description: LCD system
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interrupt-names:
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items:
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- const: fifo
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- const: vsync
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- const: lcd_sys
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power-domains:
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maxItems: 1
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reg:
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maxItems: 1
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required:
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- compatible
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- clocks
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- clock-names
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- interrupts
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- interrupt-names
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- reg
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/exynos7-clk.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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display-controller@13930000 {
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compatible = "samsung,exynos7-decon";
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reg = <0x13930000 0x1000>;
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interrupt-names = "fifo", "vsync", "lcd_sys";
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interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clock_disp 100>, /* PCLK_DECON_INT */
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<&clock_disp 101>, /* ACLK_DECON_INT */
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<&clock_disp 102>, /* SCLK_DECON_INT_ECLK */
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<&clock_disp 103>; /* SCLK_DECON_INT_EXTCLKPLL */
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clock-names = "pclk_decon0",
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"aclk_decon0",
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"decon0_eclk",
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"decon0_vclk";
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pinctrl-0 = <&lcd_clk &pwm1_out>;
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pinctrl-names = "default";
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};
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