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a94b3d14aa
Changes included (and more): 1. Dynamic RAM merge 2. Real-time page scan and allocation 3. Cache compression 4. Real-time IRQ checks 5. Dynamic I/O allocation for Java heap 6. Java page migration 7. Contiguous memory allocation 8. Idle pages tracking 9. Per CPU RAM usage tracking 10. ARM NEON scalar multiplication library 11. NEON/ARMv8 crypto extensions 12. NEON SHA, Blake, RIPEMD crypto extensions 13. Parallel NEON crypto engine for multi-algo based CPU stress reduction
167 lines
4.7 KiB
YAML
167 lines
4.7 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/cpufreq/qcom-cpufreq-nvmem.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Technologies, Inc. NVMEM CPUFreq bindings
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maintainers:
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- Ilia Lin <ilia.lin@kernel.org>
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description: |
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In certain Qualcomm Technologies, Inc. SoCs such as QCS404, The CPU supply
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voltage is dynamically configured by Core Power Reduction (CPR) depending on
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current CPU frequency and efuse values.
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CPR provides a power domain with multiple levels that are selected depending
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on the CPU OPP in use. The CPUFreq driver sets the CPR power domain level
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according to the required OPPs defined in the CPU OPP tables.
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select:
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properties:
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compatible:
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contains:
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enum:
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- qcom,qcs404
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required:
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- compatible
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properties:
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cpus:
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type: object
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patternProperties:
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'cpu@[0-9a-f]+':
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type: object
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properties:
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power-domains:
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maxItems: 1
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power-domain-names:
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items:
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- const: cpr
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required:
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- power-domains
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- power-domain-names
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patternProperties:
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'^opp-table(-[a-z0-9]+)?$':
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if:
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properties:
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compatible:
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const: operating-points-v2-kryo-cpu
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then:
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patternProperties:
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'^opp-?[0-9]+$':
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required:
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- required-opps
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additionalProperties: true
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examples:
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- |
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/ {
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model = "Qualcomm Technologies, Inc. QCS404";
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compatible = "qcom,qcs404";
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#address-cells = <2>;
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#size-cells = <2>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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CPU0: cpu@100 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x100>;
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enable-method = "psci";
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cpu-idle-states = <&CPU_SLEEP_0>;
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next-level-cache = <&L2_0>;
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#cooling-cells = <2>;
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clocks = <&apcs_glb>;
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operating-points-v2 = <&cpu_opp_table>;
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power-domains = <&cpr>;
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power-domain-names = "cpr";
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};
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CPU1: cpu@101 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x101>;
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enable-method = "psci";
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cpu-idle-states = <&CPU_SLEEP_0>;
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next-level-cache = <&L2_0>;
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#cooling-cells = <2>;
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clocks = <&apcs_glb>;
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operating-points-v2 = <&cpu_opp_table>;
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power-domains = <&cpr>;
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power-domain-names = "cpr";
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};
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CPU2: cpu@102 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x102>;
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enable-method = "psci";
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cpu-idle-states = <&CPU_SLEEP_0>;
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next-level-cache = <&L2_0>;
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#cooling-cells = <2>;
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clocks = <&apcs_glb>;
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operating-points-v2 = <&cpu_opp_table>;
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power-domains = <&cpr>;
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power-domain-names = "cpr";
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};
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CPU3: cpu@103 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x103>;
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enable-method = "psci";
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cpu-idle-states = <&CPU_SLEEP_0>;
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next-level-cache = <&L2_0>;
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#cooling-cells = <2>;
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clocks = <&apcs_glb>;
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operating-points-v2 = <&cpu_opp_table>;
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power-domains = <&cpr>;
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power-domain-names = "cpr";
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};
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};
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cpu_opp_table: opp-table-cpu {
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compatible = "operating-points-v2-kryo-cpu";
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opp-shared;
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opp-1094400000 {
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opp-hz = /bits/ 64 <1094400000>;
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required-opps = <&cpr_opp1>;
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};
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opp-1248000000 {
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opp-hz = /bits/ 64 <1248000000>;
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required-opps = <&cpr_opp2>;
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};
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opp-1401600000 {
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opp-hz = /bits/ 64 <1401600000>;
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required-opps = <&cpr_opp3>;
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};
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};
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cpr_opp_table: opp-table-cpr {
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compatible = "operating-points-v2-qcom-level";
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cpr_opp1: opp1 {
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opp-level = <1>;
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qcom,opp-fuse-level = <1>;
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};
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cpr_opp2: opp2 {
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opp-level = <2>;
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qcom,opp-fuse-level = <2>;
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};
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cpr_opp3: opp3 {
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opp-level = <3>;
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qcom,opp-fuse-level = <3>;
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};
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};
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};
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