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1094 lines
24 KiB
1094 lines
24 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* linux/sound/arm/aaci.c - ARM PrimeCell AACI PL041 driver |
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* |
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* Copyright (C) 2003 Deep Blue Solutions Ltd, All Rights Reserved. |
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* |
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* Documentation: ARM DDI 0173B |
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*/ |
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#include <linux/module.h> |
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#include <linux/delay.h> |
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#include <linux/init.h> |
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#include <linux/ioport.h> |
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#include <linux/device.h> |
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#include <linux/spinlock.h> |
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#include <linux/interrupt.h> |
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#include <linux/err.h> |
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#include <linux/amba/bus.h> |
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#include <linux/io.h> |
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|
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#include <sound/core.h> |
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#include <sound/initval.h> |
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#include <sound/ac97_codec.h> |
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#include <sound/pcm.h> |
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#include <sound/pcm_params.h> |
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|
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#include "aaci.h" |
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|
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#define DRIVER_NAME "aaci-pl041" |
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|
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#define FRAME_PERIOD_US 21 |
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|
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/* |
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* PM support is not complete. Turn it off. |
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*/ |
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#undef CONFIG_PM |
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|
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static void aaci_ac97_select_codec(struct aaci *aaci, struct snd_ac97 *ac97) |
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{ |
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u32 v, maincr = aaci->maincr | MAINCR_SCRA(ac97->num); |
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|
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/* |
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* Ensure that the slot 1/2 RX registers are empty. |
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*/ |
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v = readl(aaci->base + AACI_SLFR); |
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if (v & SLFR_2RXV) |
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readl(aaci->base + AACI_SL2RX); |
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if (v & SLFR_1RXV) |
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readl(aaci->base + AACI_SL1RX); |
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|
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if (maincr != readl(aaci->base + AACI_MAINCR)) { |
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writel(maincr, aaci->base + AACI_MAINCR); |
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readl(aaci->base + AACI_MAINCR); |
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udelay(1); |
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} |
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} |
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|
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/* |
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* P29: |
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* The recommended use of programming the external codec through slot 1 |
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* and slot 2 data is to use the channels during setup routines and the |
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* slot register at any other time. The data written into slot 1, slot 2 |
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* and slot 12 registers is transmitted only when their corresponding |
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* SI1TxEn, SI2TxEn and SI12TxEn bits are set in the AACI_MAINCR |
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* register. |
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*/ |
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static void aaci_ac97_write(struct snd_ac97 *ac97, unsigned short reg, |
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unsigned short val) |
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{ |
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struct aaci *aaci = ac97->private_data; |
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int timeout; |
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u32 v; |
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|
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if (ac97->num >= 4) |
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return; |
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|
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mutex_lock(&aaci->ac97_sem); |
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|
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aaci_ac97_select_codec(aaci, ac97); |
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|
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/* |
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* P54: You must ensure that AACI_SL2TX is always written |
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* to, if required, before data is written to AACI_SL1TX. |
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*/ |
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writel(val << 4, aaci->base + AACI_SL2TX); |
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writel(reg << 12, aaci->base + AACI_SL1TX); |
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|
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/* Initially, wait one frame period */ |
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udelay(FRAME_PERIOD_US); |
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|
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/* And then wait an additional eight frame periods for it to be sent */ |
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timeout = FRAME_PERIOD_US * 8; |
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do { |
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udelay(1); |
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v = readl(aaci->base + AACI_SLFR); |
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} while ((v & (SLFR_1TXB|SLFR_2TXB)) && --timeout); |
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if (v & (SLFR_1TXB|SLFR_2TXB)) |
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dev_err(&aaci->dev->dev, |
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"timeout waiting for write to complete\n"); |
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|
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mutex_unlock(&aaci->ac97_sem); |
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} |
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|
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/* |
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* Read an AC'97 register. |
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*/ |
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static unsigned short aaci_ac97_read(struct snd_ac97 *ac97, unsigned short reg) |
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{ |
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struct aaci *aaci = ac97->private_data; |
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int timeout, retries = 10; |
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u32 v; |
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|
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if (ac97->num >= 4) |
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return ~0; |
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mutex_lock(&aaci->ac97_sem); |
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|
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aaci_ac97_select_codec(aaci, ac97); |
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|
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/* |
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* Write the register address to slot 1. |
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*/ |
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writel((reg << 12) | (1 << 19), aaci->base + AACI_SL1TX); |
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|
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/* Initially, wait one frame period */ |
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udelay(FRAME_PERIOD_US); |
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|
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/* And then wait an additional eight frame periods for it to be sent */ |
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timeout = FRAME_PERIOD_US * 8; |
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do { |
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udelay(1); |
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v = readl(aaci->base + AACI_SLFR); |
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} while ((v & SLFR_1TXB) && --timeout); |
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|
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if (v & SLFR_1TXB) { |
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dev_err(&aaci->dev->dev, "timeout on slot 1 TX busy\n"); |
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v = ~0; |
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goto out; |
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} |
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|
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/* Now wait for the response frame */ |
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udelay(FRAME_PERIOD_US); |
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|
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/* And then wait an additional eight frame periods for data */ |
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timeout = FRAME_PERIOD_US * 8; |
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do { |
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udelay(1); |
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cond_resched(); |
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v = readl(aaci->base + AACI_SLFR) & (SLFR_1RXV|SLFR_2RXV); |
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} while ((v != (SLFR_1RXV|SLFR_2RXV)) && --timeout); |
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|
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if (v != (SLFR_1RXV|SLFR_2RXV)) { |
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dev_err(&aaci->dev->dev, "timeout on RX valid\n"); |
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v = ~0; |
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goto out; |
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} |
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|
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do { |
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v = readl(aaci->base + AACI_SL1RX) >> 12; |
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if (v == reg) { |
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v = readl(aaci->base + AACI_SL2RX) >> 4; |
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break; |
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} else if (--retries) { |
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dev_warn(&aaci->dev->dev, |
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"ac97 read back fail. retry\n"); |
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continue; |
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} else { |
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dev_warn(&aaci->dev->dev, |
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"wrong ac97 register read back (%x != %x)\n", |
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v, reg); |
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v = ~0; |
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} |
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} while (retries); |
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out: |
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mutex_unlock(&aaci->ac97_sem); |
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return v; |
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} |
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|
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static inline void |
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aaci_chan_wait_ready(struct aaci_runtime *aacirun, unsigned long mask) |
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{ |
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u32 val; |
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int timeout = 5000; |
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|
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do { |
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udelay(1); |
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val = readl(aacirun->base + AACI_SR); |
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} while (val & mask && timeout--); |
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} |
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/* |
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* Interrupt support. |
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*/ |
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static void aaci_fifo_irq(struct aaci *aaci, int channel, u32 mask) |
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{ |
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if (mask & ISR_ORINTR) { |
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dev_warn(&aaci->dev->dev, "RX overrun on chan %d\n", channel); |
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writel(ICLR_RXOEC1 << channel, aaci->base + AACI_INTCLR); |
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} |
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|
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if (mask & ISR_RXTOINTR) { |
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dev_warn(&aaci->dev->dev, "RX timeout on chan %d\n", channel); |
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writel(ICLR_RXTOFEC1 << channel, aaci->base + AACI_INTCLR); |
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} |
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|
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if (mask & ISR_RXINTR) { |
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struct aaci_runtime *aacirun = &aaci->capture; |
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bool period_elapsed = false; |
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void *ptr; |
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|
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if (!aacirun->substream || !aacirun->start) { |
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dev_warn(&aaci->dev->dev, "RX interrupt???\n"); |
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writel(0, aacirun->base + AACI_IE); |
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return; |
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} |
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spin_lock(&aacirun->lock); |
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ptr = aacirun->ptr; |
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do { |
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unsigned int len = aacirun->fifo_bytes; |
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u32 val; |
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|
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if (aacirun->bytes <= 0) { |
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aacirun->bytes += aacirun->period; |
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period_elapsed = true; |
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} |
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if (!(aacirun->cr & CR_EN)) |
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break; |
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|
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val = readl(aacirun->base + AACI_SR); |
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if (!(val & SR_RXHF)) |
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break; |
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if (!(val & SR_RXFF)) |
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len >>= 1; |
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|
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aacirun->bytes -= len; |
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|
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/* reading 16 bytes at a time */ |
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for( ; len > 0; len -= 16) { |
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asm( |
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"ldmia %1, {r0, r1, r2, r3}\n\t" |
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"stmia %0!, {r0, r1, r2, r3}" |
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: "+r" (ptr) |
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: "r" (aacirun->fifo) |
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: "r0", "r1", "r2", "r3", "cc"); |
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|
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if (ptr >= aacirun->end) |
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ptr = aacirun->start; |
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} |
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} while(1); |
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aacirun->ptr = ptr; |
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spin_unlock(&aacirun->lock); |
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|
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if (period_elapsed) |
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snd_pcm_period_elapsed(aacirun->substream); |
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} |
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if (mask & ISR_URINTR) { |
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dev_dbg(&aaci->dev->dev, "TX underrun on chan %d\n", channel); |
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writel(ICLR_TXUEC1 << channel, aaci->base + AACI_INTCLR); |
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} |
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if (mask & ISR_TXINTR) { |
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struct aaci_runtime *aacirun = &aaci->playback; |
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bool period_elapsed = false; |
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void *ptr; |
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|
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if (!aacirun->substream || !aacirun->start) { |
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dev_warn(&aaci->dev->dev, "TX interrupt???\n"); |
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writel(0, aacirun->base + AACI_IE); |
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return; |
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} |
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spin_lock(&aacirun->lock); |
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ptr = aacirun->ptr; |
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do { |
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unsigned int len = aacirun->fifo_bytes; |
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u32 val; |
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if (aacirun->bytes <= 0) { |
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aacirun->bytes += aacirun->period; |
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period_elapsed = true; |
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} |
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if (!(aacirun->cr & CR_EN)) |
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break; |
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|
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val = readl(aacirun->base + AACI_SR); |
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if (!(val & SR_TXHE)) |
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break; |
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if (!(val & SR_TXFE)) |
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len >>= 1; |
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aacirun->bytes -= len; |
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|
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/* writing 16 bytes at a time */ |
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for ( ; len > 0; len -= 16) { |
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asm( |
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"ldmia %0!, {r0, r1, r2, r3}\n\t" |
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"stmia %1, {r0, r1, r2, r3}" |
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: "+r" (ptr) |
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: "r" (aacirun->fifo) |
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: "r0", "r1", "r2", "r3", "cc"); |
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|
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if (ptr >= aacirun->end) |
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ptr = aacirun->start; |
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} |
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} while (1); |
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aacirun->ptr = ptr; |
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spin_unlock(&aacirun->lock); |
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|
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if (period_elapsed) |
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snd_pcm_period_elapsed(aacirun->substream); |
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} |
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} |
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|
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static irqreturn_t aaci_irq(int irq, void *devid) |
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{ |
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struct aaci *aaci = devid; |
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u32 mask; |
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int i; |
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|
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mask = readl(aaci->base + AACI_ALLINTS); |
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if (mask) { |
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u32 m = mask; |
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for (i = 0; i < 4; i++, m >>= 7) { |
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if (m & 0x7f) { |
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aaci_fifo_irq(aaci, i, m); |
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} |
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} |
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} |
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|
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return mask ? IRQ_HANDLED : IRQ_NONE; |
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} |
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/* |
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* ALSA support. |
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*/ |
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static const struct snd_pcm_hardware aaci_hw_info = { |
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.info = SNDRV_PCM_INFO_MMAP | |
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SNDRV_PCM_INFO_MMAP_VALID | |
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SNDRV_PCM_INFO_INTERLEAVED | |
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SNDRV_PCM_INFO_BLOCK_TRANSFER | |
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SNDRV_PCM_INFO_RESUME, |
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|
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/* |
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* ALSA doesn't support 18-bit or 20-bit packed into 32-bit |
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* words. It also doesn't support 12-bit at all. |
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*/ |
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.formats = SNDRV_PCM_FMTBIT_S16_LE, |
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|
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/* rates are setup from the AC'97 codec */ |
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.channels_min = 2, |
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.channels_max = 2, |
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.buffer_bytes_max = 64 * 1024, |
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.period_bytes_min = 256, |
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.period_bytes_max = PAGE_SIZE, |
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.periods_min = 4, |
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.periods_max = PAGE_SIZE / 16, |
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}; |
|
|
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/* |
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* We can support two and four channel audio. Unfortunately |
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* six channel audio requires a non-standard channel ordering: |
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* 2 -> FL(3), FR(4) |
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* 4 -> FL(3), FR(4), SL(7), SR(8) |
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* 6 -> FL(3), FR(4), SL(7), SR(8), C(6), LFE(9) (required) |
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* FL(3), FR(4), C(6), SL(7), SR(8), LFE(9) (actual) |
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* This requires an ALSA configuration file to correct. |
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*/ |
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static int aaci_rule_channels(struct snd_pcm_hw_params *p, |
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struct snd_pcm_hw_rule *rule) |
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{ |
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static const unsigned int channel_list[] = { 2, 4, 6 }; |
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struct aaci *aaci = rule->private; |
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unsigned int mask = 1 << 0, slots; |
|
|
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/* pcms[0] is the our 5.1 PCM instance. */ |
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slots = aaci->ac97_bus->pcms[0].r[0].slots; |
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if (slots & (1 << AC97_SLOT_PCM_SLEFT)) { |
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mask |= 1 << 1; |
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if (slots & (1 << AC97_SLOT_LFE)) |
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mask |= 1 << 2; |
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} |
|
|
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return snd_interval_list(hw_param_interval(p, rule->var), |
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ARRAY_SIZE(channel_list), channel_list, mask); |
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} |
|
|
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static int aaci_pcm_open(struct snd_pcm_substream *substream) |
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{ |
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struct snd_pcm_runtime *runtime = substream->runtime; |
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struct aaci *aaci = substream->private_data; |
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struct aaci_runtime *aacirun; |
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int ret = 0; |
|
|
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if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { |
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aacirun = &aaci->playback; |
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} else { |
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aacirun = &aaci->capture; |
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} |
|
|
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aacirun->substream = substream; |
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runtime->private_data = aacirun; |
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runtime->hw = aaci_hw_info; |
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runtime->hw.rates = aacirun->pcm->rates; |
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snd_pcm_limit_hw_rates(runtime); |
|
|
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if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { |
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runtime->hw.channels_max = 6; |
|
|
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/* Add rule describing channel dependency. */ |
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ret = snd_pcm_hw_rule_add(substream->runtime, 0, |
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SNDRV_PCM_HW_PARAM_CHANNELS, |
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aaci_rule_channels, aaci, |
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SNDRV_PCM_HW_PARAM_CHANNELS, -1); |
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if (ret) |
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return ret; |
|
|
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if (aacirun->pcm->r[1].slots) |
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snd_ac97_pcm_double_rate_rules(runtime); |
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} |
|
|
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/* |
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* ALSA wants the byte-size of the FIFOs. As we only support |
|
* 16-bit samples, this is twice the FIFO depth irrespective |
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* of whether it's in compact mode or not. |
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*/ |
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runtime->hw.fifo_size = aaci->fifo_depth * 2; |
|
|
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mutex_lock(&aaci->irq_lock); |
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if (!aaci->users++) { |
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ret = request_irq(aaci->dev->irq[0], aaci_irq, |
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IRQF_SHARED, DRIVER_NAME, aaci); |
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if (ret != 0) |
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aaci->users--; |
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} |
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mutex_unlock(&aaci->irq_lock); |
|
|
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return ret; |
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} |
|
|
|
|
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/* |
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* Common ALSA stuff |
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*/ |
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static int aaci_pcm_close(struct snd_pcm_substream *substream) |
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{ |
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struct aaci *aaci = substream->private_data; |
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struct aaci_runtime *aacirun = substream->runtime->private_data; |
|
|
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WARN_ON(aacirun->cr & CR_EN); |
|
|
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aacirun->substream = NULL; |
|
|
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mutex_lock(&aaci->irq_lock); |
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if (!--aaci->users) |
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free_irq(aaci->dev->irq[0], aaci); |
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mutex_unlock(&aaci->irq_lock); |
|
|
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return 0; |
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} |
|
|
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static int aaci_pcm_hw_free(struct snd_pcm_substream *substream) |
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{ |
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struct aaci_runtime *aacirun = substream->runtime->private_data; |
|
|
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/* |
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* This must not be called with the device enabled. |
|
*/ |
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WARN_ON(aacirun->cr & CR_EN); |
|
|
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if (aacirun->pcm_open) |
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snd_ac97_pcm_close(aacirun->pcm); |
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aacirun->pcm_open = 0; |
|
|
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return 0; |
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} |
|
|
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/* Channel to slot mask */ |
|
static const u32 channels_to_slotmask[] = { |
|
[2] = CR_SL3 | CR_SL4, |
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[4] = CR_SL3 | CR_SL4 | CR_SL7 | CR_SL8, |
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[6] = CR_SL3 | CR_SL4 | CR_SL7 | CR_SL8 | CR_SL6 | CR_SL9, |
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}; |
|
|
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static int aaci_pcm_hw_params(struct snd_pcm_substream *substream, |
|
struct snd_pcm_hw_params *params) |
|
{ |
|
struct aaci_runtime *aacirun = substream->runtime->private_data; |
|
struct aaci *aaci = substream->private_data; |
|
unsigned int channels = params_channels(params); |
|
unsigned int rate = params_rate(params); |
|
int dbl = rate > 48000; |
|
int err; |
|
|
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aaci_pcm_hw_free(substream); |
|
if (aacirun->pcm_open) { |
|
snd_ac97_pcm_close(aacirun->pcm); |
|
aacirun->pcm_open = 0; |
|
} |
|
|
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/* channels is already limited to 2, 4, or 6 by aaci_rule_channels */ |
|
if (dbl && channels != 2) |
|
return -EINVAL; |
|
|
|
err = snd_ac97_pcm_open(aacirun->pcm, rate, channels, |
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aacirun->pcm->r[dbl].slots); |
|
|
|
aacirun->pcm_open = err == 0; |
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aacirun->cr = CR_FEN | CR_COMPACT | CR_SZ16; |
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aacirun->cr |= channels_to_slotmask[channels + dbl * 2]; |
|
|
|
/* |
|
* fifo_bytes is the number of bytes we transfer to/from |
|
* the FIFO, including padding. So that's x4. As we're |
|
* in compact mode, the FIFO is half the size. |
|
*/ |
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aacirun->fifo_bytes = aaci->fifo_depth * 4 / 2; |
|
|
|
return err; |
|
} |
|
|
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static int aaci_pcm_prepare(struct snd_pcm_substream *substream) |
|
{ |
|
struct snd_pcm_runtime *runtime = substream->runtime; |
|
struct aaci_runtime *aacirun = runtime->private_data; |
|
|
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aacirun->period = snd_pcm_lib_period_bytes(substream); |
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aacirun->start = runtime->dma_area; |
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aacirun->end = aacirun->start + snd_pcm_lib_buffer_bytes(substream); |
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aacirun->ptr = aacirun->start; |
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aacirun->bytes = aacirun->period; |
|
|
|
return 0; |
|
} |
|
|
|
static snd_pcm_uframes_t aaci_pcm_pointer(struct snd_pcm_substream *substream) |
|
{ |
|
struct snd_pcm_runtime *runtime = substream->runtime; |
|
struct aaci_runtime *aacirun = runtime->private_data; |
|
ssize_t bytes = aacirun->ptr - aacirun->start; |
|
|
|
return bytes_to_frames(runtime, bytes); |
|
} |
|
|
|
|
|
/* |
|
* Playback specific ALSA stuff |
|
*/ |
|
static void aaci_pcm_playback_stop(struct aaci_runtime *aacirun) |
|
{ |
|
u32 ie; |
|
|
|
ie = readl(aacirun->base + AACI_IE); |
|
ie &= ~(IE_URIE|IE_TXIE); |
|
writel(ie, aacirun->base + AACI_IE); |
|
aacirun->cr &= ~CR_EN; |
|
aaci_chan_wait_ready(aacirun, SR_TXB); |
|
writel(aacirun->cr, aacirun->base + AACI_TXCR); |
|
} |
|
|
|
static void aaci_pcm_playback_start(struct aaci_runtime *aacirun) |
|
{ |
|
u32 ie; |
|
|
|
aaci_chan_wait_ready(aacirun, SR_TXB); |
|
aacirun->cr |= CR_EN; |
|
|
|
ie = readl(aacirun->base + AACI_IE); |
|
ie |= IE_URIE | IE_TXIE; |
|
writel(ie, aacirun->base + AACI_IE); |
|
writel(aacirun->cr, aacirun->base + AACI_TXCR); |
|
} |
|
|
|
static int aaci_pcm_playback_trigger(struct snd_pcm_substream *substream, int cmd) |
|
{ |
|
struct aaci_runtime *aacirun = substream->runtime->private_data; |
|
unsigned long flags; |
|
int ret = 0; |
|
|
|
spin_lock_irqsave(&aacirun->lock, flags); |
|
|
|
switch (cmd) { |
|
case SNDRV_PCM_TRIGGER_START: |
|
aaci_pcm_playback_start(aacirun); |
|
break; |
|
|
|
case SNDRV_PCM_TRIGGER_RESUME: |
|
aaci_pcm_playback_start(aacirun); |
|
break; |
|
|
|
case SNDRV_PCM_TRIGGER_STOP: |
|
aaci_pcm_playback_stop(aacirun); |
|
break; |
|
|
|
case SNDRV_PCM_TRIGGER_SUSPEND: |
|
aaci_pcm_playback_stop(aacirun); |
|
break; |
|
|
|
case SNDRV_PCM_TRIGGER_PAUSE_PUSH: |
|
break; |
|
|
|
case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: |
|
break; |
|
|
|
default: |
|
ret = -EINVAL; |
|
} |
|
|
|
spin_unlock_irqrestore(&aacirun->lock, flags); |
|
|
|
return ret; |
|
} |
|
|
|
static const struct snd_pcm_ops aaci_playback_ops = { |
|
.open = aaci_pcm_open, |
|
.close = aaci_pcm_close, |
|
.hw_params = aaci_pcm_hw_params, |
|
.hw_free = aaci_pcm_hw_free, |
|
.prepare = aaci_pcm_prepare, |
|
.trigger = aaci_pcm_playback_trigger, |
|
.pointer = aaci_pcm_pointer, |
|
}; |
|
|
|
static void aaci_pcm_capture_stop(struct aaci_runtime *aacirun) |
|
{ |
|
u32 ie; |
|
|
|
aaci_chan_wait_ready(aacirun, SR_RXB); |
|
|
|
ie = readl(aacirun->base + AACI_IE); |
|
ie &= ~(IE_ORIE | IE_RXIE); |
|
writel(ie, aacirun->base+AACI_IE); |
|
|
|
aacirun->cr &= ~CR_EN; |
|
|
|
writel(aacirun->cr, aacirun->base + AACI_RXCR); |
|
} |
|
|
|
static void aaci_pcm_capture_start(struct aaci_runtime *aacirun) |
|
{ |
|
u32 ie; |
|
|
|
aaci_chan_wait_ready(aacirun, SR_RXB); |
|
|
|
#ifdef DEBUG |
|
/* RX Timeout value: bits 28:17 in RXCR */ |
|
aacirun->cr |= 0xf << 17; |
|
#endif |
|
|
|
aacirun->cr |= CR_EN; |
|
writel(aacirun->cr, aacirun->base + AACI_RXCR); |
|
|
|
ie = readl(aacirun->base + AACI_IE); |
|
ie |= IE_ORIE |IE_RXIE; // overrun and rx interrupt -- half full |
|
writel(ie, aacirun->base + AACI_IE); |
|
} |
|
|
|
static int aaci_pcm_capture_trigger(struct snd_pcm_substream *substream, int cmd) |
|
{ |
|
struct aaci_runtime *aacirun = substream->runtime->private_data; |
|
unsigned long flags; |
|
int ret = 0; |
|
|
|
spin_lock_irqsave(&aacirun->lock, flags); |
|
|
|
switch (cmd) { |
|
case SNDRV_PCM_TRIGGER_START: |
|
aaci_pcm_capture_start(aacirun); |
|
break; |
|
|
|
case SNDRV_PCM_TRIGGER_RESUME: |
|
aaci_pcm_capture_start(aacirun); |
|
break; |
|
|
|
case SNDRV_PCM_TRIGGER_STOP: |
|
aaci_pcm_capture_stop(aacirun); |
|
break; |
|
|
|
case SNDRV_PCM_TRIGGER_SUSPEND: |
|
aaci_pcm_capture_stop(aacirun); |
|
break; |
|
|
|
case SNDRV_PCM_TRIGGER_PAUSE_PUSH: |
|
break; |
|
|
|
case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: |
|
break; |
|
|
|
default: |
|
ret = -EINVAL; |
|
} |
|
|
|
spin_unlock_irqrestore(&aacirun->lock, flags); |
|
|
|
return ret; |
|
} |
|
|
|
static int aaci_pcm_capture_prepare(struct snd_pcm_substream *substream) |
|
{ |
|
struct snd_pcm_runtime *runtime = substream->runtime; |
|
struct aaci *aaci = substream->private_data; |
|
|
|
aaci_pcm_prepare(substream); |
|
|
|
/* allow changing of sample rate */ |
|
aaci_ac97_write(aaci->ac97, AC97_EXTENDED_STATUS, 0x0001); /* VRA */ |
|
aaci_ac97_write(aaci->ac97, AC97_PCM_LR_ADC_RATE, runtime->rate); |
|
aaci_ac97_write(aaci->ac97, AC97_PCM_MIC_ADC_RATE, runtime->rate); |
|
|
|
/* Record select: Mic: 0, Aux: 3, Line: 4 */ |
|
aaci_ac97_write(aaci->ac97, AC97_REC_SEL, 0x0404); |
|
|
|
return 0; |
|
} |
|
|
|
static const struct snd_pcm_ops aaci_capture_ops = { |
|
.open = aaci_pcm_open, |
|
.close = aaci_pcm_close, |
|
.hw_params = aaci_pcm_hw_params, |
|
.hw_free = aaci_pcm_hw_free, |
|
.prepare = aaci_pcm_capture_prepare, |
|
.trigger = aaci_pcm_capture_trigger, |
|
.pointer = aaci_pcm_pointer, |
|
}; |
|
|
|
/* |
|
* Power Management. |
|
*/ |
|
#ifdef CONFIG_PM |
|
static int aaci_do_suspend(struct snd_card *card) |
|
{ |
|
struct aaci *aaci = card->private_data; |
|
snd_power_change_state(card, SNDRV_CTL_POWER_D3cold); |
|
return 0; |
|
} |
|
|
|
static int aaci_do_resume(struct snd_card *card) |
|
{ |
|
snd_power_change_state(card, SNDRV_CTL_POWER_D0); |
|
return 0; |
|
} |
|
|
|
static int aaci_suspend(struct device *dev) |
|
{ |
|
struct snd_card *card = dev_get_drvdata(dev); |
|
return card ? aaci_do_suspend(card) : 0; |
|
} |
|
|
|
static int aaci_resume(struct device *dev) |
|
{ |
|
struct snd_card *card = dev_get_drvdata(dev); |
|
return card ? aaci_do_resume(card) : 0; |
|
} |
|
|
|
static SIMPLE_DEV_PM_OPS(aaci_dev_pm_ops, aaci_suspend, aaci_resume); |
|
#define AACI_DEV_PM_OPS (&aaci_dev_pm_ops) |
|
#else |
|
#define AACI_DEV_PM_OPS NULL |
|
#endif |
|
|
|
|
|
static const struct ac97_pcm ac97_defs[] = { |
|
[0] = { /* Front PCM */ |
|
.exclusive = 1, |
|
.r = { |
|
[0] = { |
|
.slots = (1 << AC97_SLOT_PCM_LEFT) | |
|
(1 << AC97_SLOT_PCM_RIGHT) | |
|
(1 << AC97_SLOT_PCM_CENTER) | |
|
(1 << AC97_SLOT_PCM_SLEFT) | |
|
(1 << AC97_SLOT_PCM_SRIGHT) | |
|
(1 << AC97_SLOT_LFE), |
|
}, |
|
[1] = { |
|
.slots = (1 << AC97_SLOT_PCM_LEFT) | |
|
(1 << AC97_SLOT_PCM_RIGHT) | |
|
(1 << AC97_SLOT_PCM_LEFT_0) | |
|
(1 << AC97_SLOT_PCM_RIGHT_0), |
|
}, |
|
}, |
|
}, |
|
[1] = { /* PCM in */ |
|
.stream = 1, |
|
.exclusive = 1, |
|
.r = { |
|
[0] = { |
|
.slots = (1 << AC97_SLOT_PCM_LEFT) | |
|
(1 << AC97_SLOT_PCM_RIGHT), |
|
}, |
|
}, |
|
}, |
|
[2] = { /* Mic in */ |
|
.stream = 1, |
|
.exclusive = 1, |
|
.r = { |
|
[0] = { |
|
.slots = (1 << AC97_SLOT_MIC), |
|
}, |
|
}, |
|
} |
|
}; |
|
|
|
static const struct snd_ac97_bus_ops aaci_bus_ops = { |
|
.write = aaci_ac97_write, |
|
.read = aaci_ac97_read, |
|
}; |
|
|
|
static int aaci_probe_ac97(struct aaci *aaci) |
|
{ |
|
struct snd_ac97_template ac97_template; |
|
struct snd_ac97_bus *ac97_bus; |
|
struct snd_ac97 *ac97; |
|
int ret; |
|
|
|
/* |
|
* Assert AACIRESET for 2us |
|
*/ |
|
writel(0, aaci->base + AACI_RESET); |
|
udelay(2); |
|
writel(RESET_NRST, aaci->base + AACI_RESET); |
|
|
|
/* |
|
* Give the AC'97 codec more than enough time |
|
* to wake up. (42us = ~2 frames at 48kHz.) |
|
*/ |
|
udelay(FRAME_PERIOD_US * 2); |
|
|
|
ret = snd_ac97_bus(aaci->card, 0, &aaci_bus_ops, aaci, &ac97_bus); |
|
if (ret) |
|
goto out; |
|
|
|
ac97_bus->clock = 48000; |
|
aaci->ac97_bus = ac97_bus; |
|
|
|
memset(&ac97_template, 0, sizeof(struct snd_ac97_template)); |
|
ac97_template.private_data = aaci; |
|
ac97_template.num = 0; |
|
ac97_template.scaps = AC97_SCAP_SKIP_MODEM; |
|
|
|
ret = snd_ac97_mixer(ac97_bus, &ac97_template, &ac97); |
|
if (ret) |
|
goto out; |
|
aaci->ac97 = ac97; |
|
|
|
/* |
|
* Disable AC97 PC Beep input on audio codecs. |
|
*/ |
|
if (ac97_is_audio(ac97)) |
|
snd_ac97_write_cache(ac97, AC97_PC_BEEP, 0x801e); |
|
|
|
ret = snd_ac97_pcm_assign(ac97_bus, ARRAY_SIZE(ac97_defs), ac97_defs); |
|
if (ret) |
|
goto out; |
|
|
|
aaci->playback.pcm = &ac97_bus->pcms[0]; |
|
aaci->capture.pcm = &ac97_bus->pcms[1]; |
|
|
|
out: |
|
return ret; |
|
} |
|
|
|
static void aaci_free_card(struct snd_card *card) |
|
{ |
|
struct aaci *aaci = card->private_data; |
|
|
|
iounmap(aaci->base); |
|
} |
|
|
|
static struct aaci *aaci_init_card(struct amba_device *dev) |
|
{ |
|
struct aaci *aaci; |
|
struct snd_card *card; |
|
int err; |
|
|
|
err = snd_card_new(&dev->dev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1, |
|
THIS_MODULE, sizeof(struct aaci), &card); |
|
if (err < 0) |
|
return NULL; |
|
|
|
card->private_free = aaci_free_card; |
|
|
|
strscpy(card->driver, DRIVER_NAME, sizeof(card->driver)); |
|
strscpy(card->shortname, "ARM AC'97 Interface", sizeof(card->shortname)); |
|
snprintf(card->longname, sizeof(card->longname), |
|
"%s PL%03x rev%u at 0x%08llx, irq %d", |
|
card->shortname, amba_part(dev), amba_rev(dev), |
|
(unsigned long long)dev->res.start, dev->irq[0]); |
|
|
|
aaci = card->private_data; |
|
mutex_init(&aaci->ac97_sem); |
|
mutex_init(&aaci->irq_lock); |
|
aaci->card = card; |
|
aaci->dev = dev; |
|
|
|
/* Set MAINCR to allow slot 1 and 2 data IO */ |
|
aaci->maincr = MAINCR_IE | MAINCR_SL1RXEN | MAINCR_SL1TXEN | |
|
MAINCR_SL2RXEN | MAINCR_SL2TXEN; |
|
|
|
return aaci; |
|
} |
|
|
|
static int aaci_init_pcm(struct aaci *aaci) |
|
{ |
|
struct snd_pcm *pcm; |
|
int ret; |
|
|
|
ret = snd_pcm_new(aaci->card, "AACI AC'97", 0, 1, 1, &pcm); |
|
if (ret == 0) { |
|
aaci->pcm = pcm; |
|
pcm->private_data = aaci; |
|
pcm->info_flags = 0; |
|
|
|
strscpy(pcm->name, DRIVER_NAME, sizeof(pcm->name)); |
|
|
|
snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &aaci_playback_ops); |
|
snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &aaci_capture_ops); |
|
snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV, |
|
aaci->card->dev, |
|
0, 64 * 1024); |
|
} |
|
|
|
return ret; |
|
} |
|
|
|
static unsigned int aaci_size_fifo(struct aaci *aaci) |
|
{ |
|
struct aaci_runtime *aacirun = &aaci->playback; |
|
int i; |
|
|
|
/* |
|
* Enable the channel, but don't assign it to any slots, so |
|
* it won't empty onto the AC'97 link. |
|
*/ |
|
writel(CR_FEN | CR_SZ16 | CR_EN, aacirun->base + AACI_TXCR); |
|
|
|
for (i = 0; !(readl(aacirun->base + AACI_SR) & SR_TXFF) && i < 4096; i++) |
|
writel(0, aacirun->fifo); |
|
|
|
writel(0, aacirun->base + AACI_TXCR); |
|
|
|
/* |
|
* Re-initialise the AACI after the FIFO depth test, to |
|
* ensure that the FIFOs are empty. Unfortunately, merely |
|
* disabling the channel doesn't clear the FIFO. |
|
*/ |
|
writel(aaci->maincr & ~MAINCR_IE, aaci->base + AACI_MAINCR); |
|
readl(aaci->base + AACI_MAINCR); |
|
udelay(1); |
|
writel(aaci->maincr, aaci->base + AACI_MAINCR); |
|
|
|
/* |
|
* If we hit 4096 entries, we failed. Go back to the specified |
|
* fifo depth. |
|
*/ |
|
if (i == 4096) |
|
i = 8; |
|
|
|
return i; |
|
} |
|
|
|
static int aaci_probe(struct amba_device *dev, |
|
const struct amba_id *id) |
|
{ |
|
struct aaci *aaci; |
|
int ret, i; |
|
|
|
ret = amba_request_regions(dev, NULL); |
|
if (ret) |
|
return ret; |
|
|
|
aaci = aaci_init_card(dev); |
|
if (!aaci) { |
|
ret = -ENOMEM; |
|
goto out; |
|
} |
|
|
|
aaci->base = ioremap(dev->res.start, resource_size(&dev->res)); |
|
if (!aaci->base) { |
|
ret = -ENOMEM; |
|
goto out; |
|
} |
|
|
|
/* |
|
* Playback uses AACI channel 0 |
|
*/ |
|
spin_lock_init(&aaci->playback.lock); |
|
aaci->playback.base = aaci->base + AACI_CSCH1; |
|
aaci->playback.fifo = aaci->base + AACI_DR1; |
|
|
|
/* |
|
* Capture uses AACI channel 0 |
|
*/ |
|
spin_lock_init(&aaci->capture.lock); |
|
aaci->capture.base = aaci->base + AACI_CSCH1; |
|
aaci->capture.fifo = aaci->base + AACI_DR1; |
|
|
|
for (i = 0; i < 4; i++) { |
|
void __iomem *base = aaci->base + i * 0x14; |
|
|
|
writel(0, base + AACI_IE); |
|
writel(0, base + AACI_TXCR); |
|
writel(0, base + AACI_RXCR); |
|
} |
|
|
|
writel(0x1fff, aaci->base + AACI_INTCLR); |
|
writel(aaci->maincr, aaci->base + AACI_MAINCR); |
|
/* |
|
* Fix: ac97 read back fail errors by reading |
|
* from any arbitrary aaci register. |
|
*/ |
|
readl(aaci->base + AACI_CSCH1); |
|
ret = aaci_probe_ac97(aaci); |
|
if (ret) |
|
goto out; |
|
|
|
/* |
|
* Size the FIFOs (must be multiple of 16). |
|
* This is the number of entries in the FIFO. |
|
*/ |
|
aaci->fifo_depth = aaci_size_fifo(aaci); |
|
if (aaci->fifo_depth & 15) { |
|
printk(KERN_WARNING "AACI: FIFO depth %d not supported\n", |
|
aaci->fifo_depth); |
|
ret = -ENODEV; |
|
goto out; |
|
} |
|
|
|
ret = aaci_init_pcm(aaci); |
|
if (ret) |
|
goto out; |
|
|
|
ret = snd_card_register(aaci->card); |
|
if (ret == 0) { |
|
dev_info(&dev->dev, "%s\n", aaci->card->longname); |
|
dev_info(&dev->dev, "FIFO %u entries\n", aaci->fifo_depth); |
|
amba_set_drvdata(dev, aaci->card); |
|
return ret; |
|
} |
|
|
|
out: |
|
if (aaci) |
|
snd_card_free(aaci->card); |
|
amba_release_regions(dev); |
|
return ret; |
|
} |
|
|
|
static void aaci_remove(struct amba_device *dev) |
|
{ |
|
struct snd_card *card = amba_get_drvdata(dev); |
|
|
|
if (card) { |
|
struct aaci *aaci = card->private_data; |
|
writel(0, aaci->base + AACI_MAINCR); |
|
|
|
snd_card_free(card); |
|
amba_release_regions(dev); |
|
} |
|
} |
|
|
|
static struct amba_id aaci_ids[] = { |
|
{ |
|
.id = 0x00041041, |
|
.mask = 0x000fffff, |
|
}, |
|
{ 0, 0 }, |
|
}; |
|
|
|
MODULE_DEVICE_TABLE(amba, aaci_ids); |
|
|
|
static struct amba_driver aaci_driver = { |
|
.drv = { |
|
.name = DRIVER_NAME, |
|
.pm = AACI_DEV_PM_OPS, |
|
}, |
|
.probe = aaci_probe, |
|
.remove = aaci_remove, |
|
.id_table = aaci_ids, |
|
}; |
|
|
|
module_amba_driver(aaci_driver); |
|
|
|
MODULE_LICENSE("GPL"); |
|
MODULE_DESCRIPTION("ARM PrimeCell PL041 Advanced Audio CODEC Interface driver");
|
|
|