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202 lines
5.8 KiB
202 lines
5.8 KiB
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) |
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// |
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// Copyright(c) 2020 Intel Corporation. All rights reserved. |
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// |
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// Authors: Ranjani Sridharan <[email protected]> |
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// |
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/* |
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* Hardware interface for audio DSP on Tigerlake. |
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*/ |
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#include <sound/sof/ext_manifest4.h> |
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#include "../ipc4-priv.h" |
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#include "../ops.h" |
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#include "hda.h" |
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#include "hda-ipc.h" |
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#include "../sof-audio.h" |
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static const struct snd_sof_debugfs_map tgl_dsp_debugfs[] = { |
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{"hda", HDA_DSP_HDA_BAR, 0, 0x4000, SOF_DEBUGFS_ACCESS_ALWAYS}, |
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{"pp", HDA_DSP_PP_BAR, 0, 0x1000, SOF_DEBUGFS_ACCESS_ALWAYS}, |
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{"dsp", HDA_DSP_BAR, 0, 0x10000, SOF_DEBUGFS_ACCESS_ALWAYS}, |
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}; |
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static int tgl_dsp_core_get(struct snd_sof_dev *sdev, int core) |
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{ |
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const struct sof_ipc_pm_ops *pm_ops = sdev->ipc->ops->pm; |
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/* power up primary core if not already powered up and return */ |
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if (core == SOF_DSP_PRIMARY_CORE) |
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return hda_dsp_enable_core(sdev, BIT(core)); |
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if (pm_ops->set_core_state) |
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return pm_ops->set_core_state(sdev, core, true); |
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return 0; |
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} |
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static int tgl_dsp_core_put(struct snd_sof_dev *sdev, int core) |
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{ |
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const struct sof_ipc_pm_ops *pm_ops = sdev->ipc->ops->pm; |
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/* power down primary core and return */ |
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if (core == SOF_DSP_PRIMARY_CORE) |
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return hda_dsp_core_reset_power_down(sdev, BIT(core)); |
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if (pm_ops->set_core_state) |
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return pm_ops->set_core_state(sdev, core, false); |
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return 0; |
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} |
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/* Tigerlake ops */ |
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struct snd_sof_dsp_ops sof_tgl_ops; |
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EXPORT_SYMBOL_NS(sof_tgl_ops, SND_SOC_SOF_INTEL_HDA_COMMON); |
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int sof_tgl_ops_init(struct snd_sof_dev *sdev) |
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{ |
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/* common defaults */ |
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memcpy(&sof_tgl_ops, &sof_hda_common_ops, sizeof(struct snd_sof_dsp_ops)); |
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/* probe/remove/shutdown */ |
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sof_tgl_ops.shutdown = hda_dsp_shutdown; |
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if (sdev->pdata->ipc_type == SOF_IPC) { |
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/* doorbell */ |
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sof_tgl_ops.irq_thread = cnl_ipc_irq_thread; |
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/* ipc */ |
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sof_tgl_ops.send_msg = cnl_ipc_send_msg; |
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} |
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if (sdev->pdata->ipc_type == SOF_INTEL_IPC4) { |
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struct sof_ipc4_fw_data *ipc4_data; |
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sdev->private = devm_kzalloc(sdev->dev, sizeof(*ipc4_data), GFP_KERNEL); |
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if (!sdev->private) |
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return -ENOMEM; |
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ipc4_data = sdev->private; |
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ipc4_data->manifest_fw_hdr_offset = SOF_MAN4_FW_HDR_OFFSET; |
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/* doorbell */ |
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sof_tgl_ops.irq_thread = cnl_ipc4_irq_thread; |
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/* ipc */ |
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sof_tgl_ops.send_msg = cnl_ipc4_send_msg; |
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} |
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/* set DAI driver ops */ |
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hda_set_dai_drv_ops(sdev, &sof_tgl_ops); |
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/* debug */ |
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sof_tgl_ops.debug_map = tgl_dsp_debugfs; |
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sof_tgl_ops.debug_map_count = ARRAY_SIZE(tgl_dsp_debugfs); |
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sof_tgl_ops.ipc_dump = cnl_ipc_dump; |
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/* pre/post fw run */ |
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sof_tgl_ops.post_fw_run = hda_dsp_post_fw_run; |
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/* firmware run */ |
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sof_tgl_ops.run = hda_dsp_cl_boot_firmware_iccmax; |
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/* dsp core get/put */ |
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sof_tgl_ops.core_get = tgl_dsp_core_get; |
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sof_tgl_ops.core_put = tgl_dsp_core_put; |
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return 0; |
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}; |
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EXPORT_SYMBOL_NS(sof_tgl_ops_init, SND_SOC_SOF_INTEL_HDA_COMMON); |
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const struct sof_intel_dsp_desc tgl_chip_info = { |
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/* Tigerlake , Alderlake */ |
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.cores_num = 4, |
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.init_core_mask = 1, |
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.host_managed_cores_mask = BIT(0), |
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.ipc_req = CNL_DSP_REG_HIPCIDR, |
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.ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY, |
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.ipc_ack = CNL_DSP_REG_HIPCIDA, |
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.ipc_ack_mask = CNL_DSP_REG_HIPCIDA_DONE, |
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.ipc_ctl = CNL_DSP_REG_HIPCCTL, |
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.rom_status_reg = HDA_DSP_SRAM_REG_ROM_STATUS, |
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.rom_init_timeout = 300, |
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.ssp_count = ICL_SSP_COUNT, |
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.ssp_base_offset = CNL_SSP_BASE_OFFSET, |
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.sdw_shim_base = SDW_SHIM_BASE, |
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.sdw_alh_base = SDW_ALH_BASE, |
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.check_sdw_irq = hda_common_check_sdw_irq, |
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.check_ipc_irq = hda_dsp_check_ipc_irq, |
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.cl_init = cl_dsp_init, |
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.hw_ip_version = SOF_INTEL_CAVS_2_5, |
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}; |
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EXPORT_SYMBOL_NS(tgl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON); |
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const struct sof_intel_dsp_desc tglh_chip_info = { |
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/* Tigerlake-H */ |
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.cores_num = 2, |
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.init_core_mask = 1, |
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.host_managed_cores_mask = BIT(0), |
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.ipc_req = CNL_DSP_REG_HIPCIDR, |
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.ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY, |
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.ipc_ack = CNL_DSP_REG_HIPCIDA, |
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.ipc_ack_mask = CNL_DSP_REG_HIPCIDA_DONE, |
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.ipc_ctl = CNL_DSP_REG_HIPCCTL, |
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.rom_status_reg = HDA_DSP_SRAM_REG_ROM_STATUS, |
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.rom_init_timeout = 300, |
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.ssp_count = ICL_SSP_COUNT, |
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.ssp_base_offset = CNL_SSP_BASE_OFFSET, |
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.sdw_shim_base = SDW_SHIM_BASE, |
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.sdw_alh_base = SDW_ALH_BASE, |
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.check_sdw_irq = hda_common_check_sdw_irq, |
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.check_ipc_irq = hda_dsp_check_ipc_irq, |
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.cl_init = cl_dsp_init, |
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.hw_ip_version = SOF_INTEL_CAVS_2_5, |
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}; |
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EXPORT_SYMBOL_NS(tglh_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON); |
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const struct sof_intel_dsp_desc ehl_chip_info = { |
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/* Elkhartlake */ |
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.cores_num = 4, |
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.init_core_mask = 1, |
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.host_managed_cores_mask = BIT(0), |
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.ipc_req = CNL_DSP_REG_HIPCIDR, |
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.ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY, |
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.ipc_ack = CNL_DSP_REG_HIPCIDA, |
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.ipc_ack_mask = CNL_DSP_REG_HIPCIDA_DONE, |
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.ipc_ctl = CNL_DSP_REG_HIPCCTL, |
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.rom_status_reg = HDA_DSP_SRAM_REG_ROM_STATUS, |
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.rom_init_timeout = 300, |
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.ssp_count = ICL_SSP_COUNT, |
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.ssp_base_offset = CNL_SSP_BASE_OFFSET, |
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.sdw_shim_base = SDW_SHIM_BASE, |
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.sdw_alh_base = SDW_ALH_BASE, |
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.check_sdw_irq = hda_common_check_sdw_irq, |
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.check_ipc_irq = hda_dsp_check_ipc_irq, |
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.cl_init = cl_dsp_init, |
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.hw_ip_version = SOF_INTEL_CAVS_2_5, |
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}; |
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EXPORT_SYMBOL_NS(ehl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON); |
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const struct sof_intel_dsp_desc adls_chip_info = { |
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/* Alderlake-S */ |
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.cores_num = 2, |
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.init_core_mask = BIT(0), |
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.host_managed_cores_mask = BIT(0), |
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.ipc_req = CNL_DSP_REG_HIPCIDR, |
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.ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY, |
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.ipc_ack = CNL_DSP_REG_HIPCIDA, |
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.ipc_ack_mask = CNL_DSP_REG_HIPCIDA_DONE, |
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.ipc_ctl = CNL_DSP_REG_HIPCCTL, |
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.rom_status_reg = HDA_DSP_SRAM_REG_ROM_STATUS, |
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.rom_init_timeout = 300, |
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.ssp_count = ICL_SSP_COUNT, |
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.ssp_base_offset = CNL_SSP_BASE_OFFSET, |
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.sdw_shim_base = SDW_SHIM_BASE, |
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.sdw_alh_base = SDW_ALH_BASE, |
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.check_sdw_irq = hda_common_check_sdw_irq, |
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.check_ipc_irq = hda_dsp_check_ipc_irq, |
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.cl_init = cl_dsp_init, |
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.hw_ip_version = SOF_INTEL_CAVS_2_5, |
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}; |
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EXPORT_SYMBOL_NS(adls_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);
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