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591 lines
17 KiB
591 lines
17 KiB
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) |
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// |
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// This file is provided under a dual BSD/GPLv2 license. When using or |
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// redistributing this file, you may do so under either license. |
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// |
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// Copyright(c) 2018 Intel Corporation. All rights reserved. |
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// |
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// Authors: Liam Girdwood <[email protected]> |
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// Ranjani Sridharan <[email protected]> |
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// Rander Wang <[email protected]> |
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// Keyon Jie <[email protected]> |
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// |
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|
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/* |
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* Hardware interface for HDA DSP code loader |
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*/ |
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|
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#include <linux/firmware.h> |
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#include <sound/hdaudio_ext.h> |
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#include <sound/hda_register.h> |
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#include <sound/sof.h> |
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#include "ext_manifest.h" |
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#include "../ops.h" |
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#include "../sof-priv.h" |
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#include "hda.h" |
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|
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static void hda_ssp_set_cbp_cfp(struct snd_sof_dev *sdev) |
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{ |
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struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata; |
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const struct sof_intel_dsp_desc *chip = hda->desc; |
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int i; |
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|
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/* DSP is powered up, set all SSPs to clock consumer/codec provider mode */ |
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for (i = 0; i < chip->ssp_count; i++) { |
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snd_sof_dsp_update_bits_unlocked(sdev, HDA_DSP_BAR, |
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chip->ssp_base_offset |
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+ i * SSP_DEV_MEM_SIZE |
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+ SSP_SSC1_OFFSET, |
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SSP_SET_CBP_CFP, |
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SSP_SET_CBP_CFP); |
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} |
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} |
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struct hdac_ext_stream *hda_cl_stream_prepare(struct snd_sof_dev *sdev, unsigned int format, |
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unsigned int size, struct snd_dma_buffer *dmab, |
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int direction) |
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{ |
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struct hdac_ext_stream *hext_stream; |
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struct hdac_stream *hstream; |
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struct pci_dev *pci = to_pci_dev(sdev->dev); |
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int ret; |
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hext_stream = hda_dsp_stream_get(sdev, direction, 0); |
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|
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if (!hext_stream) { |
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dev_err(sdev->dev, "error: no stream available\n"); |
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return ERR_PTR(-ENODEV); |
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} |
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hstream = &hext_stream->hstream; |
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hstream->substream = NULL; |
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|
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/* allocate DMA buffer */ |
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ret = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV_SG, &pci->dev, size, dmab); |
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if (ret < 0) { |
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dev_err(sdev->dev, "error: memory alloc failed: %d\n", ret); |
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goto out_put; |
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} |
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hstream->period_bytes = 0;/* initialize period_bytes */ |
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hstream->format_val = format; |
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hstream->bufsize = size; |
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|
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if (direction == SNDRV_PCM_STREAM_CAPTURE) { |
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ret = hda_dsp_iccmax_stream_hw_params(sdev, hext_stream, dmab, NULL); |
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if (ret < 0) { |
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dev_err(sdev->dev, "error: iccmax stream prepare failed: %d\n", ret); |
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goto out_free; |
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} |
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} else { |
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ret = hda_dsp_stream_hw_params(sdev, hext_stream, dmab, NULL); |
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if (ret < 0) { |
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dev_err(sdev->dev, "error: hdac prepare failed: %d\n", ret); |
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goto out_free; |
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} |
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hda_dsp_stream_spib_config(sdev, hext_stream, HDA_DSP_SPIB_ENABLE, size); |
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} |
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return hext_stream; |
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out_free: |
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snd_dma_free_pages(dmab); |
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out_put: |
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hda_dsp_stream_put(sdev, direction, hstream->stream_tag); |
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return ERR_PTR(ret); |
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} |
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/* |
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* first boot sequence has some extra steps. |
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* power on all host managed cores and only unstall/run the boot core to boot the |
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* DSP then turn off all non boot cores (if any) is powered on. |
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*/ |
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int cl_dsp_init(struct snd_sof_dev *sdev, int stream_tag, bool imr_boot) |
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{ |
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struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata; |
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const struct sof_intel_dsp_desc *chip = hda->desc; |
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unsigned int status, target_status; |
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u32 flags, ipc_hdr, j; |
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unsigned long mask; |
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char *dump_msg; |
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int ret; |
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/* step 1: power up corex */ |
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ret = hda_dsp_core_power_up(sdev, chip->host_managed_cores_mask); |
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if (ret < 0) { |
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if (hda->boot_iteration == HDA_FW_BOOT_ATTEMPTS) |
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dev_err(sdev->dev, "error: dsp core 0/1 power up failed\n"); |
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goto err; |
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} |
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hda_ssp_set_cbp_cfp(sdev); |
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/* step 2: Send ROM_CONTROL command (stream_tag is ignored for IMR boot) */ |
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ipc_hdr = chip->ipc_req_mask | HDA_DSP_ROM_IPC_CONTROL; |
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if (!imr_boot) |
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ipc_hdr |= HDA_DSP_ROM_IPC_PURGE_FW | ((stream_tag - 1) << 9); |
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snd_sof_dsp_write(sdev, HDA_DSP_BAR, chip->ipc_req, ipc_hdr); |
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/* step 3: unset core 0 reset state & unstall/run core 0 */ |
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ret = hda_dsp_core_run(sdev, chip->init_core_mask); |
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if (ret < 0) { |
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if (hda->boot_iteration == HDA_FW_BOOT_ATTEMPTS) |
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dev_err(sdev->dev, |
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"error: dsp core start failed %d\n", ret); |
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ret = -EIO; |
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goto err; |
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} |
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/* step 4: wait for IPC DONE bit from ROM */ |
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ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR, |
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chip->ipc_ack, status, |
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((status & chip->ipc_ack_mask) |
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== chip->ipc_ack_mask), |
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HDA_DSP_REG_POLL_INTERVAL_US, |
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HDA_DSP_INIT_TIMEOUT_US); |
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if (ret < 0) { |
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if (hda->boot_iteration == HDA_FW_BOOT_ATTEMPTS) |
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dev_err(sdev->dev, |
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"error: %s: timeout for HIPCIE done\n", |
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__func__); |
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goto err; |
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} |
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/* set DONE bit to clear the reply IPC message */ |
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snd_sof_dsp_update_bits_forced(sdev, HDA_DSP_BAR, |
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chip->ipc_ack, |
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chip->ipc_ack_mask, |
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chip->ipc_ack_mask); |
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|
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/* step 5: power down cores that are no longer needed */ |
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ret = hda_dsp_core_reset_power_down(sdev, chip->host_managed_cores_mask & |
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~(chip->init_core_mask)); |
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if (ret < 0) { |
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if (hda->boot_iteration == HDA_FW_BOOT_ATTEMPTS) |
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dev_err(sdev->dev, |
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"error: dsp core x power down failed\n"); |
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goto err; |
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} |
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/* step 6: enable IPC interrupts */ |
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hda_dsp_ipc_int_enable(sdev); |
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/* |
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* step 7: |
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* - Cold/Full boot: wait for ROM init to proceed to download the firmware |
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* - IMR boot: wait for ROM firmware entered (firmware booted up from IMR) |
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*/ |
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if (imr_boot) |
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target_status = HDA_DSP_ROM_FW_ENTERED; |
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else |
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target_status = HDA_DSP_ROM_INIT; |
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ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR, |
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chip->rom_status_reg, status, |
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((status & HDA_DSP_ROM_STS_MASK) |
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== target_status), |
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HDA_DSP_REG_POLL_INTERVAL_US, |
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chip->rom_init_timeout * |
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USEC_PER_MSEC); |
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if (!ret) { |
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/* set enabled cores mask and increment ref count for cores in init_core_mask */ |
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sdev->enabled_cores_mask |= chip->init_core_mask; |
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mask = sdev->enabled_cores_mask; |
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for_each_set_bit(j, &mask, SOF_MAX_DSP_NUM_CORES) |
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sdev->dsp_core_ref_count[j]++; |
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return 0; |
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} |
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if (hda->boot_iteration == HDA_FW_BOOT_ATTEMPTS) |
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dev_err(sdev->dev, |
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"%s: timeout with rom_status_reg (%#x) read\n", |
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__func__, chip->rom_status_reg); |
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err: |
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flags = SOF_DBG_DUMP_PCI | SOF_DBG_DUMP_MBOX | SOF_DBG_DUMP_OPTIONAL; |
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/* after max boot attempts make sure that the dump is printed */ |
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if (hda->boot_iteration == HDA_FW_BOOT_ATTEMPTS) |
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flags &= ~SOF_DBG_DUMP_OPTIONAL; |
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dump_msg = kasprintf(GFP_KERNEL, "Boot iteration failed: %d/%d", |
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hda->boot_iteration, HDA_FW_BOOT_ATTEMPTS); |
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snd_sof_dsp_dbg_dump(sdev, dump_msg, flags); |
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hda_dsp_core_reset_power_down(sdev, chip->host_managed_cores_mask); |
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kfree(dump_msg); |
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return ret; |
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} |
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static int cl_trigger(struct snd_sof_dev *sdev, |
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struct hdac_ext_stream *hext_stream, int cmd) |
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{ |
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struct hdac_stream *hstream = &hext_stream->hstream; |
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int sd_offset = SOF_STREAM_SD_OFFSET(hstream); |
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|
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/* code loader is special case that reuses stream ops */ |
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switch (cmd) { |
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case SNDRV_PCM_TRIGGER_START: |
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snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, SOF_HDA_INTCTL, |
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1 << hstream->index, |
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1 << hstream->index); |
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snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, |
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sd_offset, |
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SOF_HDA_SD_CTL_DMA_START | |
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SOF_HDA_CL_DMA_SD_INT_MASK, |
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SOF_HDA_SD_CTL_DMA_START | |
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SOF_HDA_CL_DMA_SD_INT_MASK); |
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hstream->running = true; |
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return 0; |
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default: |
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return hda_dsp_stream_trigger(sdev, hext_stream, cmd); |
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} |
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} |
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int hda_cl_cleanup(struct snd_sof_dev *sdev, struct snd_dma_buffer *dmab, |
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struct hdac_ext_stream *hext_stream) |
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{ |
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struct hdac_stream *hstream = &hext_stream->hstream; |
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int sd_offset = SOF_STREAM_SD_OFFSET(hstream); |
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int ret = 0; |
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if (hstream->direction == SNDRV_PCM_STREAM_PLAYBACK) |
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ret = hda_dsp_stream_spib_config(sdev, hext_stream, HDA_DSP_SPIB_DISABLE, 0); |
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else |
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snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, sd_offset, |
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SOF_HDA_SD_CTL_DMA_START, 0); |
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hda_dsp_stream_put(sdev, hstream->direction, hstream->stream_tag); |
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hstream->running = 0; |
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hstream->substream = NULL; |
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/* reset BDL address */ |
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snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR, |
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sd_offset + SOF_HDA_ADSP_REG_CL_SD_BDLPL, 0); |
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snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR, |
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sd_offset + SOF_HDA_ADSP_REG_CL_SD_BDLPU, 0); |
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snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR, sd_offset, 0); |
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snd_dma_free_pages(dmab); |
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dmab->area = NULL; |
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hstream->bufsize = 0; |
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hstream->format_val = 0; |
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return ret; |
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} |
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int hda_cl_copy_fw(struct snd_sof_dev *sdev, struct hdac_ext_stream *hext_stream) |
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{ |
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struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata; |
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const struct sof_intel_dsp_desc *chip = hda->desc; |
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unsigned int reg; |
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int ret, status; |
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ret = cl_trigger(sdev, hext_stream, SNDRV_PCM_TRIGGER_START); |
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if (ret < 0) { |
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dev_err(sdev->dev, "error: DMA trigger start failed\n"); |
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return ret; |
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} |
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status = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR, |
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chip->rom_status_reg, reg, |
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((reg & HDA_DSP_ROM_STS_MASK) |
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== HDA_DSP_ROM_FW_ENTERED), |
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HDA_DSP_REG_POLL_INTERVAL_US, |
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HDA_DSP_BASEFW_TIMEOUT_US); |
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/* |
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* even in case of errors we still need to stop the DMAs, |
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* but we return the initial error should the DMA stop also fail |
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*/ |
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if (status < 0) { |
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dev_err(sdev->dev, |
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"%s: timeout with rom_status_reg (%#x) read\n", |
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__func__, chip->rom_status_reg); |
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} |
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ret = cl_trigger(sdev, hext_stream, SNDRV_PCM_TRIGGER_STOP); |
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if (ret < 0) { |
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dev_err(sdev->dev, "error: DMA trigger stop failed\n"); |
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if (!status) |
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status = ret; |
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} |
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return status; |
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} |
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int hda_dsp_cl_boot_firmware_iccmax(struct snd_sof_dev *sdev) |
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{ |
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struct snd_sof_pdata *plat_data = sdev->pdata; |
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struct hdac_ext_stream *iccmax_stream; |
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struct hdac_bus *bus = sof_to_bus(sdev); |
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struct firmware stripped_firmware; |
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struct snd_dma_buffer dmab_bdl; |
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int ret, ret1; |
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u8 original_gb; |
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/* save the original LTRP guardband value */ |
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original_gb = snd_hdac_chip_readb(bus, VS_LTRP) & HDA_VS_INTEL_LTRP_GB_MASK; |
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if (plat_data->fw->size <= plat_data->fw_offset) { |
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dev_err(sdev->dev, "error: firmware size must be greater than firmware offset\n"); |
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return -EINVAL; |
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} |
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stripped_firmware.size = plat_data->fw->size - plat_data->fw_offset; |
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|
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/* prepare capture stream for ICCMAX */ |
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iccmax_stream = hda_cl_stream_prepare(sdev, HDA_CL_STREAM_FORMAT, stripped_firmware.size, |
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&dmab_bdl, SNDRV_PCM_STREAM_CAPTURE); |
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if (IS_ERR(iccmax_stream)) { |
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dev_err(sdev->dev, "error: dma prepare for ICCMAX stream failed\n"); |
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return PTR_ERR(iccmax_stream); |
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} |
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ret = hda_dsp_cl_boot_firmware(sdev); |
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/* |
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* Perform iccmax stream cleanup. This should be done even if firmware loading fails. |
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* If the cleanup also fails, we return the initial error |
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*/ |
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ret1 = hda_cl_cleanup(sdev, &dmab_bdl, iccmax_stream); |
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if (ret1 < 0) { |
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dev_err(sdev->dev, "error: ICCMAX stream cleanup failed\n"); |
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/* set return value to indicate cleanup failure */ |
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if (!ret) |
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ret = ret1; |
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} |
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/* restore the original guardband value after FW boot */ |
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snd_hdac_chip_updateb(bus, VS_LTRP, HDA_VS_INTEL_LTRP_GB_MASK, original_gb); |
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return ret; |
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} |
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static int hda_dsp_boot_imr(struct snd_sof_dev *sdev) |
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{ |
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const struct sof_intel_dsp_desc *chip_info; |
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int ret; |
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chip_info = get_chip_info(sdev->pdata); |
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if (chip_info->cl_init) |
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ret = chip_info->cl_init(sdev, 0, true); |
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else |
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ret = -EINVAL; |
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if (!ret) |
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hda_sdw_process_wakeen(sdev); |
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return ret; |
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} |
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int hda_dsp_cl_boot_firmware(struct snd_sof_dev *sdev) |
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{ |
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struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata; |
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struct snd_sof_pdata *plat_data = sdev->pdata; |
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const struct sof_dev_desc *desc = plat_data->desc; |
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const struct sof_intel_dsp_desc *chip_info; |
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struct hdac_ext_stream *hext_stream; |
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struct firmware stripped_firmware; |
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struct snd_dma_buffer dmab; |
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int ret, ret1, i; |
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if (hda->imrboot_supported && !sdev->first_boot && !hda->skip_imr_boot) { |
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dev_dbg(sdev->dev, "IMR restore supported, booting from IMR directly\n"); |
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hda->boot_iteration = 0; |
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ret = hda_dsp_boot_imr(sdev); |
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if (!ret) |
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return 0; |
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dev_warn(sdev->dev, "IMR restore failed, trying to cold boot\n"); |
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} |
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chip_info = desc->chip_info; |
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if (plat_data->fw->size <= plat_data->fw_offset) { |
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dev_err(sdev->dev, "error: firmware size must be greater than firmware offset\n"); |
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return -EINVAL; |
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} |
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stripped_firmware.data = plat_data->fw->data + plat_data->fw_offset; |
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stripped_firmware.size = plat_data->fw->size - plat_data->fw_offset; |
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|
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/* init for booting wait */ |
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init_waitqueue_head(&sdev->boot_wait); |
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|
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/* prepare DMA for code loader stream */ |
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hext_stream = hda_cl_stream_prepare(sdev, HDA_CL_STREAM_FORMAT, |
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stripped_firmware.size, |
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&dmab, SNDRV_PCM_STREAM_PLAYBACK); |
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if (IS_ERR(hext_stream)) { |
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dev_err(sdev->dev, "error: dma prepare for fw loading failed\n"); |
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return PTR_ERR(hext_stream); |
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} |
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|
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memcpy(dmab.area, stripped_firmware.data, |
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stripped_firmware.size); |
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|
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/* try ROM init a few times before giving up */ |
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for (i = 0; i < HDA_FW_BOOT_ATTEMPTS; i++) { |
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dev_dbg(sdev->dev, |
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"Attempting iteration %d of Core En/ROM load...\n", i); |
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|
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hda->boot_iteration = i + 1; |
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if (chip_info->cl_init) |
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ret = chip_info->cl_init(sdev, hext_stream->hstream.stream_tag, false); |
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else |
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ret = -EINVAL; |
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|
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/* don't retry anymore if successful */ |
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if (!ret) |
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break; |
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} |
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|
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if (i == HDA_FW_BOOT_ATTEMPTS) { |
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dev_err(sdev->dev, "error: dsp init failed after %d attempts with err: %d\n", |
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i, ret); |
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goto cleanup; |
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} |
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|
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/* |
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* When a SoundWire link is in clock stop state, a Slave |
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* device may trigger in-band wakes for events such as jack |
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* insertion or acoustic event detection. This event will lead |
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* to a WAKEEN interrupt, handled by the PCI device and routed |
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* to PME if the PCI device is in D3. The resume function in |
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* audio PCI driver will be invoked by ACPI for PME event and |
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* initialize the device and process WAKEEN interrupt. |
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* |
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* The WAKEEN interrupt should be processed ASAP to prevent an |
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* interrupt flood, otherwise other interrupts, such IPC, |
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* cannot work normally. The WAKEEN is handled after the ROM |
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* is initialized successfully, which ensures power rails are |
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* enabled before accessing the SoundWire SHIM registers |
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*/ |
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if (!sdev->first_boot) |
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hda_sdw_process_wakeen(sdev); |
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|
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/* |
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* Set the boot_iteration to the last attempt, indicating that the |
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* DSP ROM has been initialized and from this point there will be no |
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* retry done to boot. |
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* |
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* Continue with code loading and firmware boot |
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*/ |
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hda->boot_iteration = HDA_FW_BOOT_ATTEMPTS; |
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ret = hda_cl_copy_fw(sdev, hext_stream); |
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if (!ret) { |
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dev_dbg(sdev->dev, "Firmware download successful, booting...\n"); |
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hda->skip_imr_boot = false; |
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} else { |
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snd_sof_dsp_dbg_dump(sdev, "Firmware download failed", |
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SOF_DBG_DUMP_PCI | SOF_DBG_DUMP_MBOX); |
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hda->skip_imr_boot = true; |
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} |
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|
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cleanup: |
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/* |
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* Perform codeloader stream cleanup. |
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* This should be done even if firmware loading fails. |
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* If the cleanup also fails, we return the initial error |
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*/ |
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ret1 = hda_cl_cleanup(sdev, &dmab, hext_stream); |
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if (ret1 < 0) { |
|
dev_err(sdev->dev, "error: Code loader DSP cleanup failed\n"); |
|
|
|
/* set return value to indicate cleanup failure */ |
|
if (!ret) |
|
ret = ret1; |
|
} |
|
|
|
/* |
|
* return primary core id if both fw copy |
|
* and stream clean up are successful |
|
*/ |
|
if (!ret) |
|
return chip_info->init_core_mask; |
|
|
|
/* disable DSP */ |
|
snd_sof_dsp_update_bits(sdev, HDA_DSP_PP_BAR, |
|
SOF_HDA_REG_PP_PPCTL, |
|
SOF_HDA_PPCTL_GPROCEN, 0); |
|
return ret; |
|
} |
|
|
|
/* pre fw run operations */ |
|
int hda_dsp_pre_fw_run(struct snd_sof_dev *sdev) |
|
{ |
|
/* disable clock gating and power gating */ |
|
return hda_dsp_ctrl_clock_power_gating(sdev, false); |
|
} |
|
|
|
/* post fw run operations */ |
|
int hda_dsp_post_fw_run(struct snd_sof_dev *sdev) |
|
{ |
|
int ret; |
|
|
|
if (sdev->first_boot) { |
|
struct sof_intel_hda_dev *hdev = sdev->pdata->hw_pdata; |
|
|
|
ret = hda_sdw_startup(sdev); |
|
if (ret < 0) { |
|
dev_err(sdev->dev, |
|
"error: could not startup SoundWire links\n"); |
|
return ret; |
|
} |
|
|
|
/* Check if IMR boot is usable */ |
|
if (!sof_debug_check_flag(SOF_DBG_IGNORE_D3_PERSISTENT) && |
|
(sdev->fw_ready.flags & SOF_IPC_INFO_D3_PERSISTENT || |
|
sdev->pdata->ipc_type == SOF_INTEL_IPC4)) |
|
hdev->imrboot_supported = true; |
|
} |
|
|
|
hda_sdw_int_enable(sdev, true); |
|
|
|
/* re-enable clock gating and power gating */ |
|
return hda_dsp_ctrl_clock_power_gating(sdev, true); |
|
} |
|
|
|
int hda_dsp_ext_man_get_cavs_config_data(struct snd_sof_dev *sdev, |
|
const struct sof_ext_man_elem_header *hdr) |
|
{ |
|
const struct sof_ext_man_cavs_config_data *config_data = |
|
container_of(hdr, struct sof_ext_man_cavs_config_data, hdr); |
|
struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata; |
|
int i, elem_num; |
|
|
|
/* calculate total number of config data elements */ |
|
elem_num = (hdr->size - sizeof(struct sof_ext_man_elem_header)) |
|
/ sizeof(struct sof_config_elem); |
|
if (elem_num <= 0) { |
|
dev_err(sdev->dev, "cavs config data is inconsistent: %d\n", elem_num); |
|
return -EINVAL; |
|
} |
|
|
|
for (i = 0; i < elem_num; i++) |
|
switch (config_data->elems[i].token) { |
|
case SOF_EXT_MAN_CAVS_CONFIG_EMPTY: |
|
/* skip empty token */ |
|
break; |
|
case SOF_EXT_MAN_CAVS_CONFIG_CAVS_LPRO: |
|
hda->clk_config_lpro = config_data->elems[i].value; |
|
dev_dbg(sdev->dev, "FW clock config: %s\n", |
|
hda->clk_config_lpro ? "LPRO" : "HPRO"); |
|
break; |
|
case SOF_EXT_MAN_CAVS_CONFIG_OUTBOX_SIZE: |
|
case SOF_EXT_MAN_CAVS_CONFIG_INBOX_SIZE: |
|
/* These elements are defined but not being used yet. No warn is required */ |
|
break; |
|
default: |
|
dev_info(sdev->dev, "unsupported token type: %d\n", |
|
config_data->elems[i].token); |
|
} |
|
|
|
return 0; |
|
}
|
|
|