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508 lines
12 KiB
508 lines
12 KiB
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) |
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// |
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// Copyright 2020 NXP |
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// |
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// Author: Daniel Baluta <[email protected]> |
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// |
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// Hardware interface for audio DSP on i.MX8M |
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#include <linux/bits.h> |
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#include <linux/firmware.h> |
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#include <linux/mfd/syscon.h> |
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#include <linux/of_platform.h> |
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#include <linux/of_address.h> |
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#include <linux/of_irq.h> |
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#include <linux/regmap.h> |
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#include <linux/module.h> |
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#include <sound/sof.h> |
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#include <sound/sof/xtensa.h> |
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#include <linux/firmware/imx/dsp.h> |
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#include "../ops.h" |
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#include "../sof-of-dev.h" |
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#include "imx-common.h" |
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#define MBOX_OFFSET 0x800000 |
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#define MBOX_SIZE 0x1000 |
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static struct clk_bulk_data imx8m_dsp_clks[] = { |
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{ .id = "ipg" }, |
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{ .id = "ocram" }, |
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{ .id = "core" }, |
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}; |
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/* DAP registers */ |
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#define IMX8M_DAP_DEBUG 0x28800000 |
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#define IMX8M_DAP_DEBUG_SIZE (64 * 1024) |
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#define IMX8M_DAP_PWRCTL (0x4000 + 0x3020) |
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#define IMX8M_PWRCTL_CORERESET BIT(16) |
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/* DSP audio mix registers */ |
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#define AudioDSP_REG0 0x100 |
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#define AudioDSP_REG1 0x104 |
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#define AudioDSP_REG2 0x108 |
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#define AudioDSP_REG3 0x10c |
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#define AudioDSP_REG2_RUNSTALL BIT(5) |
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struct imx8m_priv { |
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struct device *dev; |
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struct snd_sof_dev *sdev; |
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/* DSP IPC handler */ |
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struct imx_dsp_ipc *dsp_ipc; |
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struct platform_device *ipc_dev; |
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struct imx_clocks *clks; |
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void __iomem *dap; |
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struct regmap *regmap; |
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}; |
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static int imx8m_get_mailbox_offset(struct snd_sof_dev *sdev) |
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{ |
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return MBOX_OFFSET; |
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} |
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static int imx8m_get_window_offset(struct snd_sof_dev *sdev, u32 id) |
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{ |
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return MBOX_OFFSET; |
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} |
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static void imx8m_dsp_handle_reply(struct imx_dsp_ipc *ipc) |
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{ |
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struct imx8m_priv *priv = imx_dsp_get_data(ipc); |
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unsigned long flags; |
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spin_lock_irqsave(&priv->sdev->ipc_lock, flags); |
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snd_sof_ipc_process_reply(priv->sdev, 0); |
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spin_unlock_irqrestore(&priv->sdev->ipc_lock, flags); |
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} |
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static void imx8m_dsp_handle_request(struct imx_dsp_ipc *ipc) |
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{ |
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struct imx8m_priv *priv = imx_dsp_get_data(ipc); |
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u32 p; /* Panic code */ |
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/* Read the message from the debug box. */ |
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sof_mailbox_read(priv->sdev, priv->sdev->debug_box.offset + 4, &p, sizeof(p)); |
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/* Check to see if the message is a panic code (0x0dead***) */ |
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if ((p & SOF_IPC_PANIC_MAGIC_MASK) == SOF_IPC_PANIC_MAGIC) |
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snd_sof_dsp_panic(priv->sdev, p, true); |
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else |
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snd_sof_ipc_msgs_rx(priv->sdev); |
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} |
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static struct imx_dsp_ops imx8m_dsp_ops = { |
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.handle_reply = imx8m_dsp_handle_reply, |
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.handle_request = imx8m_dsp_handle_request, |
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}; |
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static int imx8m_send_msg(struct snd_sof_dev *sdev, struct snd_sof_ipc_msg *msg) |
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{ |
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struct imx8m_priv *priv = sdev->pdata->hw_pdata; |
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sof_mailbox_write(sdev, sdev->host_box.offset, msg->msg_data, |
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msg->msg_size); |
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imx_dsp_ring_doorbell(priv->dsp_ipc, 0); |
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return 0; |
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} |
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/* |
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* DSP control. |
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*/ |
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static int imx8m_run(struct snd_sof_dev *sdev) |
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{ |
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struct imx8m_priv *priv = (struct imx8m_priv *)sdev->pdata->hw_pdata; |
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regmap_update_bits(priv->regmap, AudioDSP_REG2, AudioDSP_REG2_RUNSTALL, 0); |
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return 0; |
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} |
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static int imx8m_reset(struct snd_sof_dev *sdev) |
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{ |
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struct imx8m_priv *priv = (struct imx8m_priv *)sdev->pdata->hw_pdata; |
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u32 pwrctl; |
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/* put DSP into reset and stall */ |
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pwrctl = readl(priv->dap + IMX8M_DAP_PWRCTL); |
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pwrctl |= IMX8M_PWRCTL_CORERESET; |
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writel(pwrctl, priv->dap + IMX8M_DAP_PWRCTL); |
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/* keep reset asserted for 10 cycles */ |
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usleep_range(1, 2); |
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regmap_update_bits(priv->regmap, AudioDSP_REG2, |
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AudioDSP_REG2_RUNSTALL, AudioDSP_REG2_RUNSTALL); |
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/* take the DSP out of reset and keep stalled for FW loading */ |
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pwrctl = readl(priv->dap + IMX8M_DAP_PWRCTL); |
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pwrctl &= ~IMX8M_PWRCTL_CORERESET; |
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writel(pwrctl, priv->dap + IMX8M_DAP_PWRCTL); |
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return 0; |
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} |
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static int imx8m_probe(struct snd_sof_dev *sdev) |
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{ |
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struct platform_device *pdev = |
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container_of(sdev->dev, struct platform_device, dev); |
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struct device_node *np = pdev->dev.of_node; |
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struct device_node *res_node; |
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struct resource *mmio; |
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struct imx8m_priv *priv; |
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struct resource res; |
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u32 base, size; |
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int ret = 0; |
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priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); |
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if (!priv) |
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return -ENOMEM; |
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priv->clks = devm_kzalloc(&pdev->dev, sizeof(*priv->clks), GFP_KERNEL); |
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if (!priv->clks) |
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return -ENOMEM; |
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sdev->num_cores = 1; |
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sdev->pdata->hw_pdata = priv; |
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priv->dev = sdev->dev; |
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priv->sdev = sdev; |
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priv->ipc_dev = platform_device_register_data(sdev->dev, "imx-dsp", |
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PLATFORM_DEVID_NONE, |
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pdev, sizeof(*pdev)); |
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if (IS_ERR(priv->ipc_dev)) |
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return PTR_ERR(priv->ipc_dev); |
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priv->dsp_ipc = dev_get_drvdata(&priv->ipc_dev->dev); |
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if (!priv->dsp_ipc) { |
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/* DSP IPC driver not probed yet, try later */ |
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ret = -EPROBE_DEFER; |
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dev_err(sdev->dev, "Failed to get drvdata\n"); |
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goto exit_pdev_unregister; |
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} |
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imx_dsp_set_data(priv->dsp_ipc, priv); |
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priv->dsp_ipc->ops = &imx8m_dsp_ops; |
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/* DSP base */ |
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mmio = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
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if (mmio) { |
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base = mmio->start; |
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size = resource_size(mmio); |
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} else { |
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dev_err(sdev->dev, "error: failed to get DSP base at idx 0\n"); |
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ret = -EINVAL; |
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goto exit_pdev_unregister; |
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} |
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priv->dap = devm_ioremap(sdev->dev, IMX8M_DAP_DEBUG, IMX8M_DAP_DEBUG_SIZE); |
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if (!priv->dap) { |
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dev_err(sdev->dev, "error: failed to map DAP debug memory area"); |
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ret = -ENODEV; |
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goto exit_pdev_unregister; |
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} |
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sdev->bar[SOF_FW_BLK_TYPE_IRAM] = devm_ioremap(sdev->dev, base, size); |
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if (!sdev->bar[SOF_FW_BLK_TYPE_IRAM]) { |
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dev_err(sdev->dev, "failed to ioremap base 0x%x size 0x%x\n", |
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base, size); |
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ret = -ENODEV; |
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goto exit_pdev_unregister; |
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} |
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sdev->mmio_bar = SOF_FW_BLK_TYPE_IRAM; |
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res_node = of_parse_phandle(np, "memory-region", 0); |
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if (!res_node) { |
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dev_err(&pdev->dev, "failed to get memory region node\n"); |
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ret = -ENODEV; |
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goto exit_pdev_unregister; |
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} |
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ret = of_address_to_resource(res_node, 0, &res); |
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of_node_put(res_node); |
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if (ret) { |
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dev_err(&pdev->dev, "failed to get reserved region address\n"); |
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goto exit_pdev_unregister; |
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} |
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sdev->bar[SOF_FW_BLK_TYPE_SRAM] = devm_ioremap_wc(sdev->dev, res.start, |
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resource_size(&res)); |
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if (!sdev->bar[SOF_FW_BLK_TYPE_SRAM]) { |
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dev_err(sdev->dev, "failed to ioremap mem 0x%x size 0x%x\n", |
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base, size); |
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ret = -ENOMEM; |
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goto exit_pdev_unregister; |
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} |
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sdev->mailbox_bar = SOF_FW_BLK_TYPE_SRAM; |
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/* set default mailbox offset for FW ready message */ |
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sdev->dsp_box.offset = MBOX_OFFSET; |
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priv->regmap = syscon_regmap_lookup_by_compatible("fsl,dsp-ctrl"); |
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if (IS_ERR(priv->regmap)) { |
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dev_err(sdev->dev, "cannot find dsp-ctrl registers"); |
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ret = PTR_ERR(priv->regmap); |
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goto exit_pdev_unregister; |
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} |
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/* init clocks info */ |
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priv->clks->dsp_clks = imx8m_dsp_clks; |
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priv->clks->num_dsp_clks = ARRAY_SIZE(imx8m_dsp_clks); |
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ret = imx8_parse_clocks(sdev, priv->clks); |
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if (ret < 0) |
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goto exit_pdev_unregister; |
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ret = imx8_enable_clocks(sdev, priv->clks); |
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if (ret < 0) |
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goto exit_pdev_unregister; |
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return 0; |
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exit_pdev_unregister: |
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platform_device_unregister(priv->ipc_dev); |
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return ret; |
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} |
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static int imx8m_remove(struct snd_sof_dev *sdev) |
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{ |
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struct imx8m_priv *priv = sdev->pdata->hw_pdata; |
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imx8_disable_clocks(sdev, priv->clks); |
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platform_device_unregister(priv->ipc_dev); |
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return 0; |
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} |
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/* on i.MX8 there is 1 to 1 match between type and BAR idx */ |
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static int imx8m_get_bar_index(struct snd_sof_dev *sdev, u32 type) |
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{ |
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/* Only IRAM and SRAM bars are valid */ |
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switch (type) { |
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case SOF_FW_BLK_TYPE_IRAM: |
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case SOF_FW_BLK_TYPE_SRAM: |
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return type; |
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default: |
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return -EINVAL; |
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} |
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} |
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static struct snd_soc_dai_driver imx8m_dai[] = { |
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{ |
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.name = "sai1", |
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.playback = { |
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.channels_min = 1, |
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.channels_max = 32, |
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}, |
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.capture = { |
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.channels_min = 1, |
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.channels_max = 32, |
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}, |
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}, |
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{ |
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.name = "sai3", |
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.playback = { |
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.channels_min = 1, |
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.channels_max = 32, |
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}, |
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.capture = { |
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.channels_min = 1, |
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.channels_max = 32, |
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}, |
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}, |
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}; |
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static int imx8m_dsp_set_power_state(struct snd_sof_dev *sdev, |
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const struct sof_dsp_power_state *target_state) |
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{ |
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sdev->dsp_power_state = *target_state; |
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return 0; |
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} |
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static int imx8m_resume(struct snd_sof_dev *sdev) |
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{ |
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struct imx8m_priv *priv = (struct imx8m_priv *)sdev->pdata->hw_pdata; |
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int ret; |
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int i; |
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ret = imx8_enable_clocks(sdev, priv->clks); |
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if (ret < 0) |
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return ret; |
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for (i = 0; i < DSP_MU_CHAN_NUM; i++) |
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imx_dsp_request_channel(priv->dsp_ipc, i); |
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return 0; |
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} |
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static void imx8m_suspend(struct snd_sof_dev *sdev) |
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{ |
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struct imx8m_priv *priv = (struct imx8m_priv *)sdev->pdata->hw_pdata; |
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int i; |
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for (i = 0; i < DSP_MU_CHAN_NUM; i++) |
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imx_dsp_free_channel(priv->dsp_ipc, i); |
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imx8_disable_clocks(sdev, priv->clks); |
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} |
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static int imx8m_dsp_runtime_resume(struct snd_sof_dev *sdev) |
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{ |
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int ret; |
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const struct sof_dsp_power_state target_dsp_state = { |
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.state = SOF_DSP_PM_D0, |
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}; |
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ret = imx8m_resume(sdev); |
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if (ret < 0) |
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return ret; |
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return snd_sof_dsp_set_power_state(sdev, &target_dsp_state); |
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} |
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static int imx8m_dsp_runtime_suspend(struct snd_sof_dev *sdev) |
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{ |
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const struct sof_dsp_power_state target_dsp_state = { |
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.state = SOF_DSP_PM_D3, |
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}; |
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imx8m_suspend(sdev); |
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return snd_sof_dsp_set_power_state(sdev, &target_dsp_state); |
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} |
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static int imx8m_dsp_resume(struct snd_sof_dev *sdev) |
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{ |
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int ret; |
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const struct sof_dsp_power_state target_dsp_state = { |
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.state = SOF_DSP_PM_D0, |
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}; |
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ret = imx8m_resume(sdev); |
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if (ret < 0) |
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return ret; |
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if (pm_runtime_suspended(sdev->dev)) { |
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pm_runtime_disable(sdev->dev); |
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pm_runtime_set_active(sdev->dev); |
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pm_runtime_mark_last_busy(sdev->dev); |
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pm_runtime_enable(sdev->dev); |
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pm_runtime_idle(sdev->dev); |
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} |
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return snd_sof_dsp_set_power_state(sdev, &target_dsp_state); |
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} |
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static int imx8m_dsp_suspend(struct snd_sof_dev *sdev, unsigned int target_state) |
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{ |
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const struct sof_dsp_power_state target_dsp_state = { |
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.state = target_state, |
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}; |
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if (!pm_runtime_suspended(sdev->dev)) |
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imx8m_suspend(sdev); |
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return snd_sof_dsp_set_power_state(sdev, &target_dsp_state); |
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} |
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/* i.MX8 ops */ |
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static struct snd_sof_dsp_ops sof_imx8m_ops = { |
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/* probe and remove */ |
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.probe = imx8m_probe, |
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.remove = imx8m_remove, |
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/* DSP core boot */ |
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.run = imx8m_run, |
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.reset = imx8m_reset, |
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/* Block IO */ |
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.block_read = sof_block_read, |
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.block_write = sof_block_write, |
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/* Mailbox IO */ |
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.mailbox_read = sof_mailbox_read, |
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.mailbox_write = sof_mailbox_write, |
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/* ipc */ |
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.send_msg = imx8m_send_msg, |
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.get_mailbox_offset = imx8m_get_mailbox_offset, |
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.get_window_offset = imx8m_get_window_offset, |
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.ipc_msg_data = sof_ipc_msg_data, |
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.set_stream_data_offset = sof_set_stream_data_offset, |
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.get_bar_index = imx8m_get_bar_index, |
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/* firmware loading */ |
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.load_firmware = snd_sof_load_firmware_memcpy, |
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/* Debug information */ |
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.dbg_dump = imx8_dump, |
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.debugfs_add_region_item = snd_sof_debugfs_add_region_item_iomem, |
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/* stream callbacks */ |
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.pcm_open = sof_stream_pcm_open, |
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.pcm_close = sof_stream_pcm_close, |
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/* Firmware ops */ |
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.dsp_arch_ops = &sof_xtensa_arch_ops, |
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/* DAI drivers */ |
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.drv = imx8m_dai, |
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.num_drv = ARRAY_SIZE(imx8m_dai), |
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.suspend = imx8m_dsp_suspend, |
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.resume = imx8m_dsp_resume, |
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.runtime_suspend = imx8m_dsp_runtime_suspend, |
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.runtime_resume = imx8m_dsp_runtime_resume, |
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.set_power_state = imx8m_dsp_set_power_state, |
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.hw_info = SNDRV_PCM_INFO_MMAP | |
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SNDRV_PCM_INFO_MMAP_VALID | |
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SNDRV_PCM_INFO_INTERLEAVED | |
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SNDRV_PCM_INFO_PAUSE | |
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SNDRV_PCM_INFO_NO_PERIOD_WAKEUP, |
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}; |
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static struct sof_dev_desc sof_of_imx8mp_desc = { |
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.ipc_supported_mask = BIT(SOF_IPC), |
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.ipc_default = SOF_IPC, |
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.default_fw_path = { |
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[SOF_IPC] = "imx/sof", |
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}, |
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.default_tplg_path = { |
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[SOF_IPC] = "imx/sof-tplg", |
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}, |
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.default_fw_filename = { |
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[SOF_IPC] = "sof-imx8m.ri", |
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}, |
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.nocodec_tplg_filename = "sof-imx8-nocodec.tplg", |
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.ops = &sof_imx8m_ops, |
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}; |
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static const struct of_device_id sof_of_imx8m_ids[] = { |
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{ .compatible = "fsl,imx8mp-dsp", .data = &sof_of_imx8mp_desc}, |
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{ } |
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}; |
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MODULE_DEVICE_TABLE(of, sof_of_imx8m_ids); |
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/* DT driver definition */ |
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static struct platform_driver snd_sof_of_imx8m_driver = { |
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.probe = sof_of_probe, |
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.remove = sof_of_remove, |
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.driver = { |
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.name = "sof-audio-of-imx8m", |
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.pm = &sof_of_pm, |
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.of_match_table = sof_of_imx8m_ids, |
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}, |
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}; |
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module_platform_driver(snd_sof_of_imx8m_driver); |
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MODULE_IMPORT_NS(SND_SOC_SOF_XTENSA); |
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MODULE_LICENSE("Dual BSD/GPL");
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