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399 lines
10 KiB
399 lines
10 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* Xilinx Zynq Ultrascale+ MPSoC Real Time Clock Driver |
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* |
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* Copyright (C) 2015 Xilinx, Inc. |
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* |
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*/ |
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#include <linux/clk.h> |
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#include <linux/delay.h> |
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#include <linux/init.h> |
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#include <linux/io.h> |
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#include <linux/module.h> |
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#include <linux/of.h> |
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#include <linux/platform_device.h> |
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#include <linux/rtc.h> |
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/* RTC Registers */ |
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#define RTC_SET_TM_WR 0x00 |
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#define RTC_SET_TM_RD 0x04 |
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#define RTC_CALIB_WR 0x08 |
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#define RTC_CALIB_RD 0x0C |
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#define RTC_CUR_TM 0x10 |
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#define RTC_CUR_TICK 0x14 |
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#define RTC_ALRM 0x18 |
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#define RTC_INT_STS 0x20 |
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#define RTC_INT_MASK 0x24 |
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#define RTC_INT_EN 0x28 |
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#define RTC_INT_DIS 0x2C |
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#define RTC_CTRL 0x40 |
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#define RTC_FR_EN BIT(20) |
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#define RTC_FR_DATSHIFT 16 |
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#define RTC_TICK_MASK 0xFFFF |
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#define RTC_INT_SEC BIT(0) |
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#define RTC_INT_ALRM BIT(1) |
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#define RTC_OSC_EN BIT(24) |
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#define RTC_BATT_EN BIT(31) |
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#define RTC_CALIB_DEF 0x7FFF |
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#define RTC_CALIB_MASK 0x1FFFFF |
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#define RTC_ALRM_MASK BIT(1) |
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#define RTC_MSEC 1000 |
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#define RTC_FR_MASK 0xF0000 |
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#define RTC_FR_MAX_TICKS 16 |
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#define RTC_PPB 1000000000LL |
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#define RTC_MIN_OFFSET -32768000 |
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#define RTC_MAX_OFFSET 32767000 |
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struct xlnx_rtc_dev { |
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struct rtc_device *rtc; |
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void __iomem *reg_base; |
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int alarm_irq; |
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int sec_irq; |
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struct clk *rtc_clk; |
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unsigned int freq; |
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}; |
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static int xlnx_rtc_set_time(struct device *dev, struct rtc_time *tm) |
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{ |
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struct xlnx_rtc_dev *xrtcdev = dev_get_drvdata(dev); |
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unsigned long new_time; |
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/* |
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* The value written will be updated after 1 sec into the |
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* seconds read register, so we need to program time +1 sec |
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* to get the correct time on read. |
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*/ |
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new_time = rtc_tm_to_time64(tm) + 1; |
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writel(new_time, xrtcdev->reg_base + RTC_SET_TM_WR); |
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/* |
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* Clear the rtc interrupt status register after setting the |
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* time. During a read_time function, the code should read the |
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* RTC_INT_STATUS register and if bit 0 is still 0, it means |
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* that one second has not elapsed yet since RTC was set and |
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* the current time should be read from SET_TIME_READ register; |
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* otherwise, CURRENT_TIME register is read to report the time |
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*/ |
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writel(RTC_INT_SEC, xrtcdev->reg_base + RTC_INT_STS); |
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return 0; |
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} |
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static int xlnx_rtc_read_time(struct device *dev, struct rtc_time *tm) |
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{ |
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u32 status; |
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unsigned long read_time; |
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struct xlnx_rtc_dev *xrtcdev = dev_get_drvdata(dev); |
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status = readl(xrtcdev->reg_base + RTC_INT_STS); |
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if (status & RTC_INT_SEC) { |
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/* |
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* RTC has updated the CURRENT_TIME with the time written into |
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* SET_TIME_WRITE register. |
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*/ |
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read_time = readl(xrtcdev->reg_base + RTC_CUR_TM); |
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} else { |
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/* |
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* Time written in SET_TIME_WRITE has not yet updated into |
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* the seconds read register, so read the time from the |
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* SET_TIME_WRITE instead of CURRENT_TIME register. |
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* Since we add +1 sec while writing, we need to -1 sec while |
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* reading. |
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*/ |
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read_time = readl(xrtcdev->reg_base + RTC_SET_TM_RD) - 1; |
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} |
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rtc_time64_to_tm(read_time, tm); |
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return 0; |
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} |
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static int xlnx_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm) |
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{ |
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struct xlnx_rtc_dev *xrtcdev = dev_get_drvdata(dev); |
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rtc_time64_to_tm(readl(xrtcdev->reg_base + RTC_ALRM), &alrm->time); |
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alrm->enabled = readl(xrtcdev->reg_base + RTC_INT_MASK) & RTC_INT_ALRM; |
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return 0; |
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} |
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static int xlnx_rtc_alarm_irq_enable(struct device *dev, u32 enabled) |
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{ |
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struct xlnx_rtc_dev *xrtcdev = dev_get_drvdata(dev); |
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unsigned int status; |
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ulong timeout; |
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timeout = jiffies + msecs_to_jiffies(RTC_MSEC); |
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if (enabled) { |
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while (1) { |
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status = readl(xrtcdev->reg_base + RTC_INT_STS); |
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if (!((status & RTC_ALRM_MASK) == RTC_ALRM_MASK)) |
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break; |
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if (time_after_eq(jiffies, timeout)) { |
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dev_err(dev, "Time out occur, while clearing alarm status bit\n"); |
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return -ETIMEDOUT; |
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} |
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writel(RTC_INT_ALRM, xrtcdev->reg_base + RTC_INT_STS); |
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} |
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writel(RTC_INT_ALRM, xrtcdev->reg_base + RTC_INT_EN); |
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} else { |
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writel(RTC_INT_ALRM, xrtcdev->reg_base + RTC_INT_DIS); |
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} |
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return 0; |
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} |
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static int xlnx_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm) |
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{ |
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struct xlnx_rtc_dev *xrtcdev = dev_get_drvdata(dev); |
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unsigned long alarm_time; |
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alarm_time = rtc_tm_to_time64(&alrm->time); |
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writel((u32)alarm_time, (xrtcdev->reg_base + RTC_ALRM)); |
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xlnx_rtc_alarm_irq_enable(dev, alrm->enabled); |
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return 0; |
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} |
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static void xlnx_init_rtc(struct xlnx_rtc_dev *xrtcdev) |
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{ |
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u32 rtc_ctrl; |
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/* Enable RTC switch to battery when VCC_PSAUX is not available */ |
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rtc_ctrl = readl(xrtcdev->reg_base + RTC_CTRL); |
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rtc_ctrl |= RTC_BATT_EN; |
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writel(rtc_ctrl, xrtcdev->reg_base + RTC_CTRL); |
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} |
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static int xlnx_rtc_read_offset(struct device *dev, long *offset) |
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{ |
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struct xlnx_rtc_dev *xrtcdev = dev_get_drvdata(dev); |
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unsigned long long rtc_ppb = RTC_PPB; |
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unsigned int tick_mult = do_div(rtc_ppb, xrtcdev->freq); |
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unsigned int calibval; |
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long offset_val; |
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calibval = readl(xrtcdev->reg_base + RTC_CALIB_RD); |
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/* Offset with seconds ticks */ |
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offset_val = calibval & RTC_TICK_MASK; |
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offset_val = offset_val - RTC_CALIB_DEF; |
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offset_val = offset_val * tick_mult; |
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/* Offset with fractional ticks */ |
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if (calibval & RTC_FR_EN) |
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offset_val += ((calibval & RTC_FR_MASK) >> RTC_FR_DATSHIFT) |
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* (tick_mult / RTC_FR_MAX_TICKS); |
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*offset = offset_val; |
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return 0; |
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} |
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static int xlnx_rtc_set_offset(struct device *dev, long offset) |
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{ |
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struct xlnx_rtc_dev *xrtcdev = dev_get_drvdata(dev); |
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unsigned long long rtc_ppb = RTC_PPB; |
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unsigned int tick_mult = do_div(rtc_ppb, xrtcdev->freq); |
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unsigned char fract_tick = 0; |
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unsigned int calibval; |
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short int max_tick; |
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int fract_offset; |
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if (offset < RTC_MIN_OFFSET || offset > RTC_MAX_OFFSET) |
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return -ERANGE; |
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/* Number ticks for given offset */ |
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max_tick = div_s64_rem(offset, tick_mult, &fract_offset); |
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/* Number fractional ticks for given offset */ |
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if (fract_offset) { |
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if (fract_offset < 0) { |
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fract_offset = fract_offset + tick_mult; |
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max_tick--; |
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} |
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if (fract_offset > (tick_mult / RTC_FR_MAX_TICKS)) { |
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for (fract_tick = 1; fract_tick < 16; fract_tick++) { |
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if (fract_offset <= |
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(fract_tick * |
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(tick_mult / RTC_FR_MAX_TICKS))) |
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break; |
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} |
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} |
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} |
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/* Zynqmp RTC uses second and fractional tick |
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* counters for compensation |
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*/ |
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calibval = max_tick + RTC_CALIB_DEF; |
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if (fract_tick) |
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calibval |= RTC_FR_EN; |
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calibval |= (fract_tick << RTC_FR_DATSHIFT); |
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writel(calibval, (xrtcdev->reg_base + RTC_CALIB_WR)); |
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return 0; |
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} |
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static const struct rtc_class_ops xlnx_rtc_ops = { |
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.set_time = xlnx_rtc_set_time, |
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.read_time = xlnx_rtc_read_time, |
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.read_alarm = xlnx_rtc_read_alarm, |
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.set_alarm = xlnx_rtc_set_alarm, |
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.alarm_irq_enable = xlnx_rtc_alarm_irq_enable, |
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.read_offset = xlnx_rtc_read_offset, |
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.set_offset = xlnx_rtc_set_offset, |
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}; |
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static irqreturn_t xlnx_rtc_interrupt(int irq, void *id) |
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{ |
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struct xlnx_rtc_dev *xrtcdev = (struct xlnx_rtc_dev *)id; |
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unsigned int status; |
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status = readl(xrtcdev->reg_base + RTC_INT_STS); |
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/* Check if interrupt asserted */ |
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if (!(status & (RTC_INT_SEC | RTC_INT_ALRM))) |
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return IRQ_NONE; |
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/* Disable RTC_INT_ALRM interrupt only */ |
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writel(RTC_INT_ALRM, xrtcdev->reg_base + RTC_INT_DIS); |
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if (status & RTC_INT_ALRM) |
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rtc_update_irq(xrtcdev->rtc, 1, RTC_IRQF | RTC_AF); |
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return IRQ_HANDLED; |
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} |
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static int xlnx_rtc_probe(struct platform_device *pdev) |
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{ |
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struct xlnx_rtc_dev *xrtcdev; |
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int ret; |
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xrtcdev = devm_kzalloc(&pdev->dev, sizeof(*xrtcdev), GFP_KERNEL); |
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if (!xrtcdev) |
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return -ENOMEM; |
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platform_set_drvdata(pdev, xrtcdev); |
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xrtcdev->rtc = devm_rtc_allocate_device(&pdev->dev); |
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if (IS_ERR(xrtcdev->rtc)) |
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return PTR_ERR(xrtcdev->rtc); |
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xrtcdev->rtc->ops = &xlnx_rtc_ops; |
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xrtcdev->rtc->range_max = U32_MAX; |
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xrtcdev->reg_base = devm_platform_ioremap_resource(pdev, 0); |
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if (IS_ERR(xrtcdev->reg_base)) |
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return PTR_ERR(xrtcdev->reg_base); |
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xrtcdev->alarm_irq = platform_get_irq_byname(pdev, "alarm"); |
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if (xrtcdev->alarm_irq < 0) |
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return xrtcdev->alarm_irq; |
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ret = devm_request_irq(&pdev->dev, xrtcdev->alarm_irq, |
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xlnx_rtc_interrupt, 0, |
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dev_name(&pdev->dev), xrtcdev); |
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if (ret) { |
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dev_err(&pdev->dev, "request irq failed\n"); |
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return ret; |
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} |
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xrtcdev->sec_irq = platform_get_irq_byname(pdev, "sec"); |
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if (xrtcdev->sec_irq < 0) |
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return xrtcdev->sec_irq; |
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ret = devm_request_irq(&pdev->dev, xrtcdev->sec_irq, |
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xlnx_rtc_interrupt, 0, |
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dev_name(&pdev->dev), xrtcdev); |
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if (ret) { |
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dev_err(&pdev->dev, "request irq failed\n"); |
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return ret; |
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} |
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/* Getting the rtc_clk info */ |
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xrtcdev->rtc_clk = devm_clk_get_optional(&pdev->dev, "rtc_clk"); |
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if (IS_ERR(xrtcdev->rtc_clk)) { |
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if (PTR_ERR(xrtcdev->rtc_clk) != -EPROBE_DEFER) |
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dev_warn(&pdev->dev, "Device clock not found.\n"); |
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} |
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xrtcdev->freq = clk_get_rate(xrtcdev->rtc_clk); |
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if (!xrtcdev->freq) { |
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ret = of_property_read_u32(pdev->dev.of_node, "calibration", |
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&xrtcdev->freq); |
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if (ret) |
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xrtcdev->freq = RTC_CALIB_DEF; |
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} |
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ret = readl(xrtcdev->reg_base + RTC_CALIB_RD); |
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if (!ret) |
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writel(xrtcdev->freq, (xrtcdev->reg_base + RTC_CALIB_WR)); |
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xlnx_init_rtc(xrtcdev); |
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device_init_wakeup(&pdev->dev, 1); |
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return devm_rtc_register_device(xrtcdev->rtc); |
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} |
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static int xlnx_rtc_remove(struct platform_device *pdev) |
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{ |
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xlnx_rtc_alarm_irq_enable(&pdev->dev, 0); |
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device_init_wakeup(&pdev->dev, 0); |
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return 0; |
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} |
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static int __maybe_unused xlnx_rtc_suspend(struct device *dev) |
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{ |
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struct xlnx_rtc_dev *xrtcdev = dev_get_drvdata(dev); |
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if (device_may_wakeup(dev)) |
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enable_irq_wake(xrtcdev->alarm_irq); |
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else |
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xlnx_rtc_alarm_irq_enable(dev, 0); |
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return 0; |
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} |
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static int __maybe_unused xlnx_rtc_resume(struct device *dev) |
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{ |
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struct xlnx_rtc_dev *xrtcdev = dev_get_drvdata(dev); |
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if (device_may_wakeup(dev)) |
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disable_irq_wake(xrtcdev->alarm_irq); |
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else |
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xlnx_rtc_alarm_irq_enable(dev, 1); |
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return 0; |
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} |
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static SIMPLE_DEV_PM_OPS(xlnx_rtc_pm_ops, xlnx_rtc_suspend, xlnx_rtc_resume); |
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static const struct of_device_id xlnx_rtc_of_match[] = { |
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{.compatible = "xlnx,zynqmp-rtc" }, |
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{ } |
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}; |
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MODULE_DEVICE_TABLE(of, xlnx_rtc_of_match); |
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static struct platform_driver xlnx_rtc_driver = { |
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.probe = xlnx_rtc_probe, |
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.remove = xlnx_rtc_remove, |
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.driver = { |
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.name = KBUILD_MODNAME, |
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.pm = &xlnx_rtc_pm_ops, |
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.of_match_table = xlnx_rtc_of_match, |
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}, |
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}; |
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module_platform_driver(xlnx_rtc_driver); |
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MODULE_DESCRIPTION("Xilinx Zynq MPSoC RTC driver"); |
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MODULE_AUTHOR("Xilinx Inc."); |
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MODULE_LICENSE("GPL v2");
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