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110 lines
2.9 KiB
110 lines
2.9 KiB
/* SPDX-License-Identifier: GPL-2.0 */ |
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#ifndef _ARDUCAM_PIVARIETY_H_ |
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#define _ARDUCAM_PIVARIETY_H_ |
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#define DEVICE_REG_BASE 0x0100 |
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#define PIXFORMAT_REG_BASE 0x0200 |
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#define FORMAT_REG_BASE 0x0300 |
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#define CTRL_REG_BASE 0x0400 |
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#define IPC_REG_BASE 0x0600 |
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#define ARDUCAM_MODE_STANDBY 0x00 |
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#define ARDUCAM_MODE_STREAMING 0x01 |
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#define MODE_SELECT_REG (DEVICE_REG_BASE | 0x0000) |
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#define DEVICE_VERSION_REG (DEVICE_REG_BASE | 0x0001) |
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#define SENSOR_ID_REG (DEVICE_REG_BASE | 0x0002) |
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#define DEVICE_ID_REG (DEVICE_REG_BASE | 0x0003) |
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#define SYSTEM_IDLE_REG (DEVICE_REG_BASE | 0x0007) |
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#define PIXFORMAT_INDEX_REG (PIXFORMAT_REG_BASE | 0x0000) |
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#define PIXFORMAT_TYPE_REG (PIXFORMAT_REG_BASE | 0x0001) |
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#define PIXFORMAT_ORDER_REG (PIXFORMAT_REG_BASE | 0x0002) |
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#define MIPI_LANES_REG (PIXFORMAT_REG_BASE | 0x0003) |
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#define FLIPS_DONT_CHANGE_ORDER_REG (PIXFORMAT_REG_BASE | 0x0004) |
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#define RESOLUTION_INDEX_REG (FORMAT_REG_BASE | 0x0000) |
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#define FORMAT_WIDTH_REG (FORMAT_REG_BASE | 0x0001) |
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#define FORMAT_HEIGHT_REG (FORMAT_REG_BASE | 0x0002) |
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#define CTRL_INDEX_REG (CTRL_REG_BASE | 0x0000) |
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#define CTRL_ID_REG (CTRL_REG_BASE | 0x0001) |
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#define CTRL_MIN_REG (CTRL_REG_BASE | 0x0002) |
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#define CTRL_MAX_REG (CTRL_REG_BASE | 0x0003) |
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#define CTRL_STEP_REG (CTRL_REG_BASE | 0x0004) |
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#define CTRL_DEF_REG (CTRL_REG_BASE | 0x0005) |
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#define CTRL_VALUE_REG (CTRL_REG_BASE | 0x0006) |
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#define IPC_SEL_TARGET_REG (IPC_REG_BASE | 0x0000) |
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#define IPC_SEL_TOP_REG (IPC_REG_BASE | 0x0001) |
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#define IPC_SEL_LEFT_REG (IPC_REG_BASE | 0x0002) |
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#define IPC_SEL_WIDTH_REG (IPC_REG_BASE | 0x0003) |
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#define IPC_SEL_HEIGHT_REG (IPC_REG_BASE | 0x0004) |
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#define IPC_DELAY_REG (IPC_REG_BASE | 0x0005) |
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#define NO_DATA_AVAILABLE 0xFFFFFFFE |
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#define DEVICE_ID 0x0030 |
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#define I2C_READ_RETRY_COUNT 3 |
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#define I2C_WRITE_RETRY_COUNT 2 |
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#define V4L2_CID_ARDUCAM_BASE (V4L2_CID_USER_BASE + 0x1000) |
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#define V4L2_CID_ARDUCAM_EXT_TRI (V4L2_CID_ARDUCAM_BASE + 1) |
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#define V4L2_CID_ARDUCAM_IRCUT (V4L2_CID_ARDUCAM_BASE + 8) |
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#define V4L2_CID_ARDUCAM_STROBE_SHIFT (V4L2_CID_ARDUCAM_BASE + 14) |
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#define V4L2_CID_ARDUCAM_STROBE_WIDTH (V4L2_CID_ARDUCAM_BASE + 15) |
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#define V4L2_CID_ARDUCAM_MODE (V4L2_CID_ARDUCAM_BASE + 16) |
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enum image_dt { |
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IMAGE_DT_YUV420_8 = 0x18, |
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IMAGE_DT_YUV420_10, |
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IMAGE_DT_YUV420CSPS_8 = 0x1C, |
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IMAGE_DT_YUV420CSPS_10, |
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IMAGE_DT_YUV422_8, |
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IMAGE_DT_YUV422_10, |
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IMAGE_DT_RGB444, |
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IMAGE_DT_RGB555, |
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IMAGE_DT_RGB565, |
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IMAGE_DT_RGB666, |
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IMAGE_DT_RGB888, |
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IMAGE_DT_RAW6 = 0x28, |
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IMAGE_DT_RAW7, |
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IMAGE_DT_RAW8, |
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IMAGE_DT_RAW10, |
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IMAGE_DT_RAW12, |
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IMAGE_DT_RAW14, |
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}; |
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enum bayer_order { |
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BAYER_ORDER_BGGR = 0, |
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BAYER_ORDER_GBRG = 1, |
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BAYER_ORDER_GRBG = 2, |
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BAYER_ORDER_RGGB = 3, |
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BAYER_ORDER_GRAY = 4, |
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}; |
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enum yuv_order { |
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YUV_ORDER_YUYV = 0, |
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YUV_ORDER_YVYU = 1, |
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YUV_ORDER_UYVY = 2, |
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YUV_ORDER_VYUY = 3, |
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}; |
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struct arducam_resolution { |
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u32 width; |
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u32 height; |
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}; |
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struct arducam_format { |
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u32 index; |
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u32 mbus_code; |
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u32 bayer_order; |
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u32 data_type; |
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u32 num_resolution_set; |
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struct arducam_resolution *resolution_set; |
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}; |
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#endif
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