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912 lines
27 KiB
912 lines
27 KiB
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) |
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/* |
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* Copyright (C) 2004-2016 Synopsys, Inc. |
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* |
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* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions |
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* are met: |
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* 1. Redistributions of source code must retain the above copyright |
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* notice, this list of conditions, and the following disclaimer, |
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* without modification. |
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* 2. Redistributions in binary form must reproduce the above copyright |
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* notice, this list of conditions and the following disclaimer in the |
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* documentation and/or other materials provided with the distribution. |
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* 3. The names of the above-listed copyright holders may not be used |
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* to endorse or promote products derived from this software without |
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* specific prior written permission. |
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* |
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* ALTERNATIVELY, this software may be distributed under the terms of the |
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* GNU General Public License ("GPL") as published by the Free Software |
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* Foundation; either version 2 of the License, or (at your option) any |
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* later version. |
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* |
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS |
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* IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, |
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* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR |
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR |
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* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, |
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* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, |
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* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR |
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* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF |
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* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING |
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* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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*/ |
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#include <linux/kernel.h> |
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#include <linux/module.h> |
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#include <linux/of_device.h> |
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#include <linux/usb/of.h> |
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#include "core.h" |
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static void dwc2_set_bcm_params(struct dwc2_hsotg *hsotg) |
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{ |
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struct dwc2_core_params *p = &hsotg->params; |
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p->host_rx_fifo_size = 774; |
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p->max_transfer_size = 65535; |
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p->max_packet_count = 511; |
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p->ahbcfg = 0x10; |
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} |
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|
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static void dwc2_set_his_params(struct dwc2_hsotg *hsotg) |
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{ |
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struct dwc2_core_params *p = &hsotg->params; |
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p->otg_caps.hnp_support = false; |
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p->otg_caps.srp_support = false; |
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p->speed = DWC2_SPEED_PARAM_HIGH; |
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p->host_rx_fifo_size = 512; |
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p->host_nperio_tx_fifo_size = 512; |
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p->host_perio_tx_fifo_size = 512; |
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p->max_transfer_size = 65535; |
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p->max_packet_count = 511; |
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p->host_channels = 16; |
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p->phy_type = DWC2_PHY_TYPE_PARAM_UTMI; |
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p->phy_utmi_width = 8; |
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p->i2c_enable = false; |
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p->reload_ctl = false; |
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p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << |
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GAHBCFG_HBSTLEN_SHIFT; |
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p->change_speed_quirk = true; |
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p->power_down = DWC2_POWER_DOWN_PARAM_NONE; |
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} |
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static void dwc2_set_s3c6400_params(struct dwc2_hsotg *hsotg) |
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{ |
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struct dwc2_core_params *p = &hsotg->params; |
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p->power_down = DWC2_POWER_DOWN_PARAM_NONE; |
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p->no_clock_gating = true; |
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p->phy_utmi_width = 8; |
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} |
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static void dwc2_set_rk_params(struct dwc2_hsotg *hsotg) |
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{ |
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struct dwc2_core_params *p = &hsotg->params; |
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p->otg_caps.hnp_support = false; |
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p->otg_caps.srp_support = false; |
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p->host_rx_fifo_size = 525; |
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p->host_nperio_tx_fifo_size = 128; |
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p->host_perio_tx_fifo_size = 256; |
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p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << |
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GAHBCFG_HBSTLEN_SHIFT; |
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p->power_down = DWC2_POWER_DOWN_PARAM_NONE; |
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} |
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static void dwc2_set_ltq_params(struct dwc2_hsotg *hsotg) |
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{ |
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struct dwc2_core_params *p = &hsotg->params; |
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p->otg_caps.hnp_support = false; |
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p->otg_caps.srp_support = false; |
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p->host_rx_fifo_size = 288; |
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p->host_nperio_tx_fifo_size = 128; |
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p->host_perio_tx_fifo_size = 96; |
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p->max_transfer_size = 65535; |
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p->max_packet_count = 511; |
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p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << |
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GAHBCFG_HBSTLEN_SHIFT; |
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} |
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static void dwc2_set_amlogic_params(struct dwc2_hsotg *hsotg) |
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{ |
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struct dwc2_core_params *p = &hsotg->params; |
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p->otg_caps.hnp_support = false; |
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p->otg_caps.srp_support = false; |
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p->speed = DWC2_SPEED_PARAM_HIGH; |
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p->host_rx_fifo_size = 512; |
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p->host_nperio_tx_fifo_size = 500; |
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p->host_perio_tx_fifo_size = 500; |
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p->host_channels = 16; |
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p->phy_type = DWC2_PHY_TYPE_PARAM_UTMI; |
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p->ahbcfg = GAHBCFG_HBSTLEN_INCR8 << |
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GAHBCFG_HBSTLEN_SHIFT; |
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p->power_down = DWC2_POWER_DOWN_PARAM_NONE; |
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} |
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static void dwc2_set_amlogic_g12a_params(struct dwc2_hsotg *hsotg) |
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{ |
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struct dwc2_core_params *p = &hsotg->params; |
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p->lpm = false; |
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p->lpm_clock_gating = false; |
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p->besl = false; |
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p->hird_threshold_en = false; |
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} |
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static void dwc2_set_amcc_params(struct dwc2_hsotg *hsotg) |
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{ |
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struct dwc2_core_params *p = &hsotg->params; |
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p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << GAHBCFG_HBSTLEN_SHIFT; |
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} |
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static void dwc2_set_stm32f4x9_fsotg_params(struct dwc2_hsotg *hsotg) |
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{ |
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struct dwc2_core_params *p = &hsotg->params; |
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p->otg_caps.hnp_support = false; |
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p->otg_caps.srp_support = false; |
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p->speed = DWC2_SPEED_PARAM_FULL; |
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p->host_rx_fifo_size = 128; |
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p->host_nperio_tx_fifo_size = 96; |
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p->host_perio_tx_fifo_size = 96; |
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p->max_packet_count = 256; |
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p->phy_type = DWC2_PHY_TYPE_PARAM_FS; |
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p->i2c_enable = false; |
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p->activate_stm_fs_transceiver = true; |
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} |
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static void dwc2_set_stm32f7_hsotg_params(struct dwc2_hsotg *hsotg) |
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{ |
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struct dwc2_core_params *p = &hsotg->params; |
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p->host_rx_fifo_size = 622; |
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p->host_nperio_tx_fifo_size = 128; |
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p->host_perio_tx_fifo_size = 256; |
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} |
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static void dwc2_set_stm32mp15_fsotg_params(struct dwc2_hsotg *hsotg) |
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{ |
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struct dwc2_core_params *p = &hsotg->params; |
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p->otg_caps.hnp_support = false; |
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p->otg_caps.srp_support = false; |
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p->otg_caps.otg_rev = 0x200; |
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p->speed = DWC2_SPEED_PARAM_FULL; |
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p->host_rx_fifo_size = 128; |
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p->host_nperio_tx_fifo_size = 96; |
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p->host_perio_tx_fifo_size = 96; |
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p->max_packet_count = 256; |
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p->phy_type = DWC2_PHY_TYPE_PARAM_FS; |
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p->i2c_enable = false; |
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p->activate_stm_fs_transceiver = true; |
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p->activate_stm_id_vb_detection = true; |
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p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << GAHBCFG_HBSTLEN_SHIFT; |
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p->power_down = DWC2_POWER_DOWN_PARAM_NONE; |
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p->host_support_fs_ls_low_power = true; |
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p->host_ls_low_power_phy_clk = true; |
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} |
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static void dwc2_set_stm32mp15_hsotg_params(struct dwc2_hsotg *hsotg) |
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{ |
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struct dwc2_core_params *p = &hsotg->params; |
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p->otg_caps.hnp_support = false; |
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p->otg_caps.srp_support = false; |
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p->otg_caps.otg_rev = 0x200; |
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p->activate_stm_id_vb_detection = !device_property_read_bool(hsotg->dev, "usb-role-switch"); |
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p->host_rx_fifo_size = 440; |
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p->host_nperio_tx_fifo_size = 256; |
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p->host_perio_tx_fifo_size = 256; |
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p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << GAHBCFG_HBSTLEN_SHIFT; |
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p->power_down = DWC2_POWER_DOWN_PARAM_NONE; |
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p->lpm = false; |
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p->lpm_clock_gating = false; |
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p->besl = false; |
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p->hird_threshold_en = false; |
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} |
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const struct of_device_id dwc2_of_match_table[] = { |
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{ .compatible = "brcm,bcm2835-usb", .data = dwc2_set_bcm_params }, |
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{ .compatible = "hisilicon,hi6220-usb", .data = dwc2_set_his_params }, |
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{ .compatible = "rockchip,rk3066-usb", .data = dwc2_set_rk_params }, |
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{ .compatible = "lantiq,arx100-usb", .data = dwc2_set_ltq_params }, |
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{ .compatible = "lantiq,xrx200-usb", .data = dwc2_set_ltq_params }, |
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{ .compatible = "snps,dwc2" }, |
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{ .compatible = "samsung,s3c6400-hsotg", |
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.data = dwc2_set_s3c6400_params }, |
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{ .compatible = "amlogic,meson8-usb", |
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.data = dwc2_set_amlogic_params }, |
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{ .compatible = "amlogic,meson8b-usb", |
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.data = dwc2_set_amlogic_params }, |
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{ .compatible = "amlogic,meson-gxbb-usb", |
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.data = dwc2_set_amlogic_params }, |
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{ .compatible = "amlogic,meson-g12a-usb", |
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.data = dwc2_set_amlogic_g12a_params }, |
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{ .compatible = "amcc,dwc-otg", .data = dwc2_set_amcc_params }, |
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{ .compatible = "apm,apm82181-dwc-otg", .data = dwc2_set_amcc_params }, |
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{ .compatible = "st,stm32f4x9-fsotg", |
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.data = dwc2_set_stm32f4x9_fsotg_params }, |
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{ .compatible = "st,stm32f4x9-hsotg" }, |
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{ .compatible = "st,stm32f7-hsotg", |
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.data = dwc2_set_stm32f7_hsotg_params }, |
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{ .compatible = "st,stm32mp15-fsotg", |
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.data = dwc2_set_stm32mp15_fsotg_params }, |
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{ .compatible = "st,stm32mp15-hsotg", |
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.data = dwc2_set_stm32mp15_hsotg_params }, |
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{}, |
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}; |
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MODULE_DEVICE_TABLE(of, dwc2_of_match_table); |
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const struct acpi_device_id dwc2_acpi_match[] = { |
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{ "BCM2848", (kernel_ulong_t)dwc2_set_bcm_params }, |
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{ }, |
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}; |
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MODULE_DEVICE_TABLE(acpi, dwc2_acpi_match); |
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static void dwc2_set_param_otg_cap(struct dwc2_hsotg *hsotg) |
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{ |
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switch (hsotg->hw_params.op_mode) { |
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case GHWCFG2_OP_MODE_HNP_SRP_CAPABLE: |
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hsotg->params.otg_caps.hnp_support = true; |
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hsotg->params.otg_caps.srp_support = true; |
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break; |
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case GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE: |
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case GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE: |
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case GHWCFG2_OP_MODE_SRP_CAPABLE_HOST: |
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hsotg->params.otg_caps.hnp_support = false; |
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hsotg->params.otg_caps.srp_support = true; |
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break; |
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default: |
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hsotg->params.otg_caps.hnp_support = false; |
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hsotg->params.otg_caps.srp_support = false; |
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break; |
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} |
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} |
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static void dwc2_set_param_phy_type(struct dwc2_hsotg *hsotg) |
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{ |
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int val; |
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u32 hs_phy_type = hsotg->hw_params.hs_phy_type; |
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val = DWC2_PHY_TYPE_PARAM_FS; |
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if (hs_phy_type != GHWCFG2_HS_PHY_TYPE_NOT_SUPPORTED) { |
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if (hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI || |
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hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI_ULPI) |
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val = DWC2_PHY_TYPE_PARAM_UTMI; |
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else |
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val = DWC2_PHY_TYPE_PARAM_ULPI; |
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} |
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if (dwc2_is_fs_iot(hsotg)) |
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hsotg->params.phy_type = DWC2_PHY_TYPE_PARAM_FS; |
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hsotg->params.phy_type = val; |
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} |
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static void dwc2_set_param_speed(struct dwc2_hsotg *hsotg) |
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{ |
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int val; |
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val = hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS ? |
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DWC2_SPEED_PARAM_FULL : DWC2_SPEED_PARAM_HIGH; |
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if (dwc2_is_fs_iot(hsotg)) |
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val = DWC2_SPEED_PARAM_FULL; |
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if (dwc2_is_hs_iot(hsotg)) |
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val = DWC2_SPEED_PARAM_HIGH; |
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hsotg->params.speed = val; |
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} |
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static void dwc2_set_param_phy_utmi_width(struct dwc2_hsotg *hsotg) |
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{ |
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int val; |
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val = (hsotg->hw_params.utmi_phy_data_width == |
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GHWCFG4_UTMI_PHY_DATA_WIDTH_8) ? 8 : 16; |
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if (hsotg->phy) { |
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/* |
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* If using the generic PHY framework, check if the PHY bus |
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* width is 8-bit and set the phyif appropriately. |
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*/ |
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if (phy_get_bus_width(hsotg->phy) == 8) |
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val = 8; |
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} |
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hsotg->params.phy_utmi_width = val; |
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} |
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static void dwc2_set_param_tx_fifo_sizes(struct dwc2_hsotg *hsotg) |
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{ |
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struct dwc2_core_params *p = &hsotg->params; |
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int depth_average; |
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int fifo_count; |
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int i; |
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fifo_count = dwc2_hsotg_tx_fifo_count(hsotg); |
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memset(p->g_tx_fifo_size, 0, sizeof(p->g_tx_fifo_size)); |
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depth_average = dwc2_hsotg_tx_fifo_average_depth(hsotg); |
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for (i = 1; i <= fifo_count; i++) |
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p->g_tx_fifo_size[i] = depth_average; |
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} |
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static void dwc2_set_param_power_down(struct dwc2_hsotg *hsotg) |
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{ |
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int val; |
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if (hsotg->hw_params.hibernation) |
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val = DWC2_POWER_DOWN_PARAM_HIBERNATION; |
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else if (hsotg->hw_params.power_optimized) |
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val = DWC2_POWER_DOWN_PARAM_PARTIAL; |
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else |
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val = DWC2_POWER_DOWN_PARAM_NONE; |
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hsotg->params.power_down = val; |
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} |
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static void dwc2_set_param_lpm(struct dwc2_hsotg *hsotg) |
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{ |
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struct dwc2_core_params *p = &hsotg->params; |
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p->lpm = hsotg->hw_params.lpm_mode; |
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if (p->lpm) { |
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p->lpm_clock_gating = true; |
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p->besl = true; |
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p->hird_threshold_en = true; |
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p->hird_threshold = 4; |
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} else { |
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p->lpm_clock_gating = false; |
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p->besl = false; |
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p->hird_threshold_en = false; |
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} |
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} |
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/** |
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* dwc2_set_default_params() - Set all core parameters to their |
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* auto-detected default values. |
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* |
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* @hsotg: Programming view of the DWC_otg controller |
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* |
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*/ |
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static void dwc2_set_default_params(struct dwc2_hsotg *hsotg) |
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{ |
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struct dwc2_hw_params *hw = &hsotg->hw_params; |
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struct dwc2_core_params *p = &hsotg->params; |
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bool dma_capable = !(hw->arch == GHWCFG2_SLAVE_ONLY_ARCH); |
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dwc2_set_param_otg_cap(hsotg); |
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dwc2_set_param_phy_type(hsotg); |
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dwc2_set_param_speed(hsotg); |
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dwc2_set_param_phy_utmi_width(hsotg); |
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dwc2_set_param_power_down(hsotg); |
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dwc2_set_param_lpm(hsotg); |
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p->phy_ulpi_ddr = false; |
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p->phy_ulpi_ext_vbus = false; |
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p->enable_dynamic_fifo = hw->enable_dynamic_fifo; |
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p->en_multiple_tx_fifo = hw->en_multiple_tx_fifo; |
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p->i2c_enable = hw->i2c_enable; |
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p->acg_enable = hw->acg_enable; |
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p->ulpi_fs_ls = false; |
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p->ts_dline = false; |
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p->reload_ctl = (hw->snpsid >= DWC2_CORE_REV_2_92a); |
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p->uframe_sched = true; |
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p->external_id_pin_ctl = false; |
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p->ipg_isoc_en = false; |
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p->service_interval = false; |
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p->max_packet_count = hw->max_packet_count; |
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p->max_transfer_size = hw->max_transfer_size; |
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p->ahbcfg = GAHBCFG_HBSTLEN_INCR << GAHBCFG_HBSTLEN_SHIFT; |
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p->ref_clk_per = 33333; |
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p->sof_cnt_wkup_alert = 100; |
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if ((hsotg->dr_mode == USB_DR_MODE_HOST) || |
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(hsotg->dr_mode == USB_DR_MODE_OTG)) { |
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p->host_dma = dma_capable; |
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p->dma_desc_enable = false; |
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p->dma_desc_fs_enable = false; |
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p->host_support_fs_ls_low_power = false; |
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p->host_ls_low_power_phy_clk = false; |
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p->host_channels = hw->host_channels; |
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p->host_rx_fifo_size = hw->rx_fifo_size; |
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p->host_nperio_tx_fifo_size = hw->host_nperio_tx_fifo_size; |
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p->host_perio_tx_fifo_size = hw->host_perio_tx_fifo_size; |
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} |
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if ((hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) || |
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(hsotg->dr_mode == USB_DR_MODE_OTG)) { |
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p->g_dma = dma_capable; |
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p->g_dma_desc = hw->dma_desc_enable; |
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|
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/* |
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* The values for g_rx_fifo_size (2048) and |
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* g_np_tx_fifo_size (1024) come from the legacy s3c |
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* gadget driver. These defaults have been hard-coded |
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* for some time so many platforms depend on these |
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* values. Leave them as defaults for now and only |
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* auto-detect if the hardware does not support the |
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* default. |
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*/ |
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p->g_rx_fifo_size = 2048; |
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p->g_np_tx_fifo_size = 1024; |
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dwc2_set_param_tx_fifo_sizes(hsotg); |
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} |
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} |
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|
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/** |
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* dwc2_get_device_properties() - Read in device properties. |
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* |
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* @hsotg: Programming view of the DWC_otg controller |
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* |
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* Read in the device properties and adjust core parameters if needed. |
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*/ |
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static void dwc2_get_device_properties(struct dwc2_hsotg *hsotg) |
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{ |
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struct dwc2_core_params *p = &hsotg->params; |
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int num; |
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|
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if ((hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) || |
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(hsotg->dr_mode == USB_DR_MODE_OTG)) { |
|
device_property_read_u32(hsotg->dev, "g-rx-fifo-size", |
|
&p->g_rx_fifo_size); |
|
|
|
device_property_read_u32(hsotg->dev, "g-np-tx-fifo-size", |
|
&p->g_np_tx_fifo_size); |
|
|
|
num = device_property_count_u32(hsotg->dev, "g-tx-fifo-size"); |
|
if (num > 0) { |
|
num = min(num, 15); |
|
memset(p->g_tx_fifo_size, 0, |
|
sizeof(p->g_tx_fifo_size)); |
|
device_property_read_u32_array(hsotg->dev, |
|
"g-tx-fifo-size", |
|
&p->g_tx_fifo_size[1], |
|
num); |
|
} |
|
|
|
of_usb_update_otg_caps(hsotg->dev->of_node, &p->otg_caps); |
|
} |
|
|
|
if (of_find_property(hsotg->dev->of_node, "disable-over-current", NULL)) |
|
p->oc_disable = true; |
|
} |
|
|
|
static void dwc2_check_param_otg_cap(struct dwc2_hsotg *hsotg) |
|
{ |
|
int valid = 1; |
|
|
|
if (hsotg->params.otg_caps.hnp_support && hsotg->params.otg_caps.srp_support) { |
|
/* check HNP && SRP capable */ |
|
if (hsotg->hw_params.op_mode != GHWCFG2_OP_MODE_HNP_SRP_CAPABLE) |
|
valid = 0; |
|
} else if (!hsotg->params.otg_caps.hnp_support) { |
|
/* check SRP only capable */ |
|
if (hsotg->params.otg_caps.srp_support) { |
|
switch (hsotg->hw_params.op_mode) { |
|
case GHWCFG2_OP_MODE_HNP_SRP_CAPABLE: |
|
case GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE: |
|
case GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE: |
|
case GHWCFG2_OP_MODE_SRP_CAPABLE_HOST: |
|
break; |
|
default: |
|
valid = 0; |
|
break; |
|
} |
|
} |
|
/* else: NO HNP && NO SRP capable: always valid */ |
|
} else { |
|
valid = 0; |
|
} |
|
|
|
if (!valid) |
|
dwc2_set_param_otg_cap(hsotg); |
|
} |
|
|
|
static void dwc2_check_param_phy_type(struct dwc2_hsotg *hsotg) |
|
{ |
|
int valid = 0; |
|
u32 hs_phy_type; |
|
u32 fs_phy_type; |
|
|
|
hs_phy_type = hsotg->hw_params.hs_phy_type; |
|
fs_phy_type = hsotg->hw_params.fs_phy_type; |
|
|
|
switch (hsotg->params.phy_type) { |
|
case DWC2_PHY_TYPE_PARAM_FS: |
|
if (fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED) |
|
valid = 1; |
|
break; |
|
case DWC2_PHY_TYPE_PARAM_UTMI: |
|
if ((hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI) || |
|
(hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI_ULPI)) |
|
valid = 1; |
|
break; |
|
case DWC2_PHY_TYPE_PARAM_ULPI: |
|
if ((hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI) || |
|
(hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI_ULPI)) |
|
valid = 1; |
|
break; |
|
default: |
|
break; |
|
} |
|
|
|
if (!valid) |
|
dwc2_set_param_phy_type(hsotg); |
|
} |
|
|
|
static void dwc2_check_param_speed(struct dwc2_hsotg *hsotg) |
|
{ |
|
int valid = 1; |
|
int phy_type = hsotg->params.phy_type; |
|
int speed = hsotg->params.speed; |
|
|
|
switch (speed) { |
|
case DWC2_SPEED_PARAM_HIGH: |
|
if ((hsotg->params.speed == DWC2_SPEED_PARAM_HIGH) && |
|
(phy_type == DWC2_PHY_TYPE_PARAM_FS)) |
|
valid = 0; |
|
break; |
|
case DWC2_SPEED_PARAM_FULL: |
|
case DWC2_SPEED_PARAM_LOW: |
|
break; |
|
default: |
|
valid = 0; |
|
break; |
|
} |
|
|
|
if (!valid) |
|
dwc2_set_param_speed(hsotg); |
|
} |
|
|
|
static void dwc2_check_param_phy_utmi_width(struct dwc2_hsotg *hsotg) |
|
{ |
|
int valid = 0; |
|
int param = hsotg->params.phy_utmi_width; |
|
int width = hsotg->hw_params.utmi_phy_data_width; |
|
|
|
switch (width) { |
|
case GHWCFG4_UTMI_PHY_DATA_WIDTH_8: |
|
valid = (param == 8); |
|
break; |
|
case GHWCFG4_UTMI_PHY_DATA_WIDTH_16: |
|
valid = (param == 16); |
|
break; |
|
case GHWCFG4_UTMI_PHY_DATA_WIDTH_8_OR_16: |
|
valid = (param == 8 || param == 16); |
|
break; |
|
} |
|
|
|
if (!valid) |
|
dwc2_set_param_phy_utmi_width(hsotg); |
|
} |
|
|
|
static void dwc2_check_param_power_down(struct dwc2_hsotg *hsotg) |
|
{ |
|
int param = hsotg->params.power_down; |
|
|
|
switch (param) { |
|
case DWC2_POWER_DOWN_PARAM_NONE: |
|
break; |
|
case DWC2_POWER_DOWN_PARAM_PARTIAL: |
|
if (hsotg->hw_params.power_optimized) |
|
break; |
|
dev_dbg(hsotg->dev, |
|
"Partial power down isn't supported by HW\n"); |
|
param = DWC2_POWER_DOWN_PARAM_NONE; |
|
break; |
|
case DWC2_POWER_DOWN_PARAM_HIBERNATION: |
|
if (hsotg->hw_params.hibernation) |
|
break; |
|
dev_dbg(hsotg->dev, |
|
"Hibernation isn't supported by HW\n"); |
|
param = DWC2_POWER_DOWN_PARAM_NONE; |
|
break; |
|
default: |
|
dev_err(hsotg->dev, |
|
"%s: Invalid parameter power_down=%d\n", |
|
__func__, param); |
|
param = DWC2_POWER_DOWN_PARAM_NONE; |
|
break; |
|
} |
|
|
|
hsotg->params.power_down = param; |
|
} |
|
|
|
static void dwc2_check_param_tx_fifo_sizes(struct dwc2_hsotg *hsotg) |
|
{ |
|
int fifo_count; |
|
int fifo; |
|
int min; |
|
u32 total = 0; |
|
u32 dptxfszn; |
|
|
|
fifo_count = dwc2_hsotg_tx_fifo_count(hsotg); |
|
min = hsotg->hw_params.en_multiple_tx_fifo ? 16 : 4; |
|
|
|
for (fifo = 1; fifo <= fifo_count; fifo++) |
|
total += hsotg->params.g_tx_fifo_size[fifo]; |
|
|
|
if (total > dwc2_hsotg_tx_fifo_total_depth(hsotg) || !total) { |
|
dev_warn(hsotg->dev, "%s: Invalid parameter g-tx-fifo-size, setting to default average\n", |
|
__func__); |
|
dwc2_set_param_tx_fifo_sizes(hsotg); |
|
} |
|
|
|
for (fifo = 1; fifo <= fifo_count; fifo++) { |
|
dptxfszn = hsotg->hw_params.g_tx_fifo_size[fifo]; |
|
|
|
if (hsotg->params.g_tx_fifo_size[fifo] < min || |
|
hsotg->params.g_tx_fifo_size[fifo] > dptxfszn) { |
|
dev_warn(hsotg->dev, "%s: Invalid parameter g_tx_fifo_size[%d]=%d\n", |
|
__func__, fifo, |
|
hsotg->params.g_tx_fifo_size[fifo]); |
|
hsotg->params.g_tx_fifo_size[fifo] = dptxfszn; |
|
} |
|
} |
|
} |
|
|
|
#define CHECK_RANGE(_param, _min, _max, _def) do { \ |
|
if ((int)(hsotg->params._param) < (_min) || \ |
|
(hsotg->params._param) > (_max)) { \ |
|
dev_warn(hsotg->dev, "%s: Invalid parameter %s=%d\n", \ |
|
__func__, #_param, hsotg->params._param); \ |
|
hsotg->params._param = (_def); \ |
|
} \ |
|
} while (0) |
|
|
|
#define CHECK_BOOL(_param, _check) do { \ |
|
if (hsotg->params._param && !(_check)) { \ |
|
dev_warn(hsotg->dev, "%s: Invalid parameter %s=%d\n", \ |
|
__func__, #_param, hsotg->params._param); \ |
|
hsotg->params._param = false; \ |
|
} \ |
|
} while (0) |
|
|
|
static void dwc2_check_params(struct dwc2_hsotg *hsotg) |
|
{ |
|
struct dwc2_hw_params *hw = &hsotg->hw_params; |
|
struct dwc2_core_params *p = &hsotg->params; |
|
bool dma_capable = !(hw->arch == GHWCFG2_SLAVE_ONLY_ARCH); |
|
|
|
dwc2_check_param_otg_cap(hsotg); |
|
dwc2_check_param_phy_type(hsotg); |
|
dwc2_check_param_speed(hsotg); |
|
dwc2_check_param_phy_utmi_width(hsotg); |
|
dwc2_check_param_power_down(hsotg); |
|
CHECK_BOOL(enable_dynamic_fifo, hw->enable_dynamic_fifo); |
|
CHECK_BOOL(en_multiple_tx_fifo, hw->en_multiple_tx_fifo); |
|
CHECK_BOOL(i2c_enable, hw->i2c_enable); |
|
CHECK_BOOL(ipg_isoc_en, hw->ipg_isoc_en); |
|
CHECK_BOOL(acg_enable, hw->acg_enable); |
|
CHECK_BOOL(reload_ctl, (hsotg->hw_params.snpsid > DWC2_CORE_REV_2_92a)); |
|
CHECK_BOOL(lpm, (hsotg->hw_params.snpsid >= DWC2_CORE_REV_2_80a)); |
|
CHECK_BOOL(lpm, hw->lpm_mode); |
|
CHECK_BOOL(lpm_clock_gating, hsotg->params.lpm); |
|
CHECK_BOOL(besl, hsotg->params.lpm); |
|
CHECK_BOOL(besl, (hsotg->hw_params.snpsid >= DWC2_CORE_REV_3_00a)); |
|
CHECK_BOOL(hird_threshold_en, hsotg->params.lpm); |
|
CHECK_RANGE(hird_threshold, 0, hsotg->params.besl ? 12 : 7, 0); |
|
CHECK_BOOL(service_interval, hw->service_interval_mode); |
|
CHECK_RANGE(max_packet_count, |
|
15, hw->max_packet_count, |
|
hw->max_packet_count); |
|
CHECK_RANGE(max_transfer_size, |
|
2047, hw->max_transfer_size, |
|
hw->max_transfer_size); |
|
|
|
if ((hsotg->dr_mode == USB_DR_MODE_HOST) || |
|
(hsotg->dr_mode == USB_DR_MODE_OTG)) { |
|
CHECK_BOOL(host_dma, dma_capable); |
|
CHECK_BOOL(dma_desc_enable, p->host_dma); |
|
CHECK_BOOL(dma_desc_fs_enable, p->dma_desc_enable); |
|
CHECK_BOOL(host_ls_low_power_phy_clk, |
|
p->phy_type == DWC2_PHY_TYPE_PARAM_FS); |
|
CHECK_RANGE(host_channels, |
|
1, hw->host_channels, |
|
hw->host_channels); |
|
CHECK_RANGE(host_rx_fifo_size, |
|
16, hw->rx_fifo_size, |
|
hw->rx_fifo_size); |
|
CHECK_RANGE(host_nperio_tx_fifo_size, |
|
16, hw->host_nperio_tx_fifo_size, |
|
hw->host_nperio_tx_fifo_size); |
|
CHECK_RANGE(host_perio_tx_fifo_size, |
|
16, hw->host_perio_tx_fifo_size, |
|
hw->host_perio_tx_fifo_size); |
|
} |
|
|
|
if ((hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) || |
|
(hsotg->dr_mode == USB_DR_MODE_OTG)) { |
|
CHECK_BOOL(g_dma, dma_capable); |
|
CHECK_BOOL(g_dma_desc, (p->g_dma && hw->dma_desc_enable)); |
|
CHECK_RANGE(g_rx_fifo_size, |
|
16, hw->rx_fifo_size, |
|
hw->rx_fifo_size); |
|
CHECK_RANGE(g_np_tx_fifo_size, |
|
16, hw->dev_nperio_tx_fifo_size, |
|
hw->dev_nperio_tx_fifo_size); |
|
dwc2_check_param_tx_fifo_sizes(hsotg); |
|
} |
|
} |
|
|
|
/* |
|
* Gets host hardware parameters. Forces host mode if not currently in |
|
* host mode. Should be called immediately after a core soft reset in |
|
* order to get the reset values. |
|
*/ |
|
static void dwc2_get_host_hwparams(struct dwc2_hsotg *hsotg) |
|
{ |
|
struct dwc2_hw_params *hw = &hsotg->hw_params; |
|
u32 gnptxfsiz; |
|
u32 hptxfsiz; |
|
|
|
if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) |
|
return; |
|
|
|
dwc2_force_mode(hsotg, true); |
|
|
|
gnptxfsiz = dwc2_readl(hsotg, GNPTXFSIZ); |
|
hptxfsiz = dwc2_readl(hsotg, HPTXFSIZ); |
|
|
|
hw->host_nperio_tx_fifo_size = (gnptxfsiz & FIFOSIZE_DEPTH_MASK) >> |
|
FIFOSIZE_DEPTH_SHIFT; |
|
hw->host_perio_tx_fifo_size = (hptxfsiz & FIFOSIZE_DEPTH_MASK) >> |
|
FIFOSIZE_DEPTH_SHIFT; |
|
} |
|
|
|
/* |
|
* Gets device hardware parameters. Forces device mode if not |
|
* currently in device mode. Should be called immediately after a core |
|
* soft reset in order to get the reset values. |
|
*/ |
|
static void dwc2_get_dev_hwparams(struct dwc2_hsotg *hsotg) |
|
{ |
|
struct dwc2_hw_params *hw = &hsotg->hw_params; |
|
u32 gnptxfsiz; |
|
int fifo, fifo_count; |
|
|
|
if (hsotg->dr_mode == USB_DR_MODE_HOST) |
|
return; |
|
|
|
dwc2_force_mode(hsotg, false); |
|
|
|
gnptxfsiz = dwc2_readl(hsotg, GNPTXFSIZ); |
|
|
|
fifo_count = dwc2_hsotg_tx_fifo_count(hsotg); |
|
|
|
for (fifo = 1; fifo <= fifo_count; fifo++) { |
|
hw->g_tx_fifo_size[fifo] = |
|
(dwc2_readl(hsotg, DPTXFSIZN(fifo)) & |
|
FIFOSIZE_DEPTH_MASK) >> FIFOSIZE_DEPTH_SHIFT; |
|
} |
|
|
|
hw->dev_nperio_tx_fifo_size = (gnptxfsiz & FIFOSIZE_DEPTH_MASK) >> |
|
FIFOSIZE_DEPTH_SHIFT; |
|
} |
|
|
|
/** |
|
* dwc2_get_hwparams() - During device initialization, read various hardware |
|
* configuration registers and interpret the contents. |
|
* |
|
* @hsotg: Programming view of the DWC_otg controller |
|
* |
|
*/ |
|
int dwc2_get_hwparams(struct dwc2_hsotg *hsotg) |
|
{ |
|
struct dwc2_hw_params *hw = &hsotg->hw_params; |
|
unsigned int width; |
|
u32 hwcfg1, hwcfg2, hwcfg3, hwcfg4; |
|
u32 grxfsiz; |
|
|
|
hwcfg1 = dwc2_readl(hsotg, GHWCFG1); |
|
hwcfg2 = dwc2_readl(hsotg, GHWCFG2); |
|
hwcfg3 = dwc2_readl(hsotg, GHWCFG3); |
|
hwcfg4 = dwc2_readl(hsotg, GHWCFG4); |
|
grxfsiz = dwc2_readl(hsotg, GRXFSIZ); |
|
|
|
/* hwcfg1 */ |
|
hw->dev_ep_dirs = hwcfg1; |
|
|
|
/* hwcfg2 */ |
|
hw->op_mode = (hwcfg2 & GHWCFG2_OP_MODE_MASK) >> |
|
GHWCFG2_OP_MODE_SHIFT; |
|
hw->arch = (hwcfg2 & GHWCFG2_ARCHITECTURE_MASK) >> |
|
GHWCFG2_ARCHITECTURE_SHIFT; |
|
hw->enable_dynamic_fifo = !!(hwcfg2 & GHWCFG2_DYNAMIC_FIFO); |
|
hw->host_channels = 1 + ((hwcfg2 & GHWCFG2_NUM_HOST_CHAN_MASK) >> |
|
GHWCFG2_NUM_HOST_CHAN_SHIFT); |
|
hw->hs_phy_type = (hwcfg2 & GHWCFG2_HS_PHY_TYPE_MASK) >> |
|
GHWCFG2_HS_PHY_TYPE_SHIFT; |
|
hw->fs_phy_type = (hwcfg2 & GHWCFG2_FS_PHY_TYPE_MASK) >> |
|
GHWCFG2_FS_PHY_TYPE_SHIFT; |
|
hw->num_dev_ep = (hwcfg2 & GHWCFG2_NUM_DEV_EP_MASK) >> |
|
GHWCFG2_NUM_DEV_EP_SHIFT; |
|
hw->nperio_tx_q_depth = |
|
(hwcfg2 & GHWCFG2_NONPERIO_TX_Q_DEPTH_MASK) >> |
|
GHWCFG2_NONPERIO_TX_Q_DEPTH_SHIFT << 1; |
|
hw->host_perio_tx_q_depth = |
|
(hwcfg2 & GHWCFG2_HOST_PERIO_TX_Q_DEPTH_MASK) >> |
|
GHWCFG2_HOST_PERIO_TX_Q_DEPTH_SHIFT << 1; |
|
hw->dev_token_q_depth = |
|
(hwcfg2 & GHWCFG2_DEV_TOKEN_Q_DEPTH_MASK) >> |
|
GHWCFG2_DEV_TOKEN_Q_DEPTH_SHIFT; |
|
|
|
/* hwcfg3 */ |
|
width = (hwcfg3 & GHWCFG3_XFER_SIZE_CNTR_WIDTH_MASK) >> |
|
GHWCFG3_XFER_SIZE_CNTR_WIDTH_SHIFT; |
|
hw->max_transfer_size = (1 << (width + 11)) - 1; |
|
width = (hwcfg3 & GHWCFG3_PACKET_SIZE_CNTR_WIDTH_MASK) >> |
|
GHWCFG3_PACKET_SIZE_CNTR_WIDTH_SHIFT; |
|
hw->max_packet_count = (1 << (width + 4)) - 1; |
|
hw->i2c_enable = !!(hwcfg3 & GHWCFG3_I2C); |
|
hw->total_fifo_size = (hwcfg3 & GHWCFG3_DFIFO_DEPTH_MASK) >> |
|
GHWCFG3_DFIFO_DEPTH_SHIFT; |
|
hw->lpm_mode = !!(hwcfg3 & GHWCFG3_OTG_LPM_EN); |
|
|
|
/* hwcfg4 */ |
|
hw->en_multiple_tx_fifo = !!(hwcfg4 & GHWCFG4_DED_FIFO_EN); |
|
hw->num_dev_perio_in_ep = (hwcfg4 & GHWCFG4_NUM_DEV_PERIO_IN_EP_MASK) >> |
|
GHWCFG4_NUM_DEV_PERIO_IN_EP_SHIFT; |
|
hw->num_dev_in_eps = (hwcfg4 & GHWCFG4_NUM_IN_EPS_MASK) >> |
|
GHWCFG4_NUM_IN_EPS_SHIFT; |
|
hw->dma_desc_enable = !!(hwcfg4 & GHWCFG4_DESC_DMA); |
|
hw->power_optimized = !!(hwcfg4 & GHWCFG4_POWER_OPTIMIZ); |
|
hw->hibernation = !!(hwcfg4 & GHWCFG4_HIBER); |
|
hw->utmi_phy_data_width = (hwcfg4 & GHWCFG4_UTMI_PHY_DATA_WIDTH_MASK) >> |
|
GHWCFG4_UTMI_PHY_DATA_WIDTH_SHIFT; |
|
hw->acg_enable = !!(hwcfg4 & GHWCFG4_ACG_SUPPORTED); |
|
hw->ipg_isoc_en = !!(hwcfg4 & GHWCFG4_IPG_ISOC_SUPPORTED); |
|
hw->service_interval_mode = !!(hwcfg4 & |
|
GHWCFG4_SERVICE_INTERVAL_SUPPORTED); |
|
|
|
/* fifo sizes */ |
|
hw->rx_fifo_size = (grxfsiz & GRXFSIZ_DEPTH_MASK) >> |
|
GRXFSIZ_DEPTH_SHIFT; |
|
/* |
|
* Host specific hardware parameters. Reading these parameters |
|
* requires the controller to be in host mode. The mode will |
|
* be forced, if necessary, to read these values. |
|
*/ |
|
dwc2_get_host_hwparams(hsotg); |
|
dwc2_get_dev_hwparams(hsotg); |
|
|
|
return 0; |
|
} |
|
|
|
typedef void (*set_params_cb)(struct dwc2_hsotg *data); |
|
|
|
int dwc2_init_params(struct dwc2_hsotg *hsotg) |
|
{ |
|
const struct of_device_id *match; |
|
set_params_cb set_params; |
|
|
|
dwc2_set_default_params(hsotg); |
|
dwc2_get_device_properties(hsotg); |
|
|
|
match = of_match_device(dwc2_of_match_table, hsotg->dev); |
|
if (match && match->data) { |
|
set_params = match->data; |
|
set_params(hsotg); |
|
} else { |
|
const struct acpi_device_id *amatch; |
|
|
|
amatch = acpi_match_device(dwc2_acpi_match, hsotg->dev); |
|
if (amatch && amatch->driver_data) { |
|
set_params = (set_params_cb)amatch->driver_data; |
|
set_params(hsotg); |
|
} |
|
} |
|
|
|
dwc2_check_params(hsotg); |
|
|
|
return 0; |
|
}
|
|
|