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382 lines
9.9 KiB
382 lines
9.9 KiB
// SPDX-License-Identifier: GPL-2.0+ |
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/* Copyright (C) 2014-2018 Broadcom */ |
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/** |
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* DOC: Broadcom V3D Graphics Driver |
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* |
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* This driver supports the Broadcom V3D 3.3 and 4.1 OpenGL ES GPUs. |
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* For V3D 2.x support, see the VC4 driver. |
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* |
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* The V3D GPU includes a tiled render (composed of a bin and render |
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* pipelines), the TFU (texture formatting unit), and the CSD (compute |
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* shader dispatch). |
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*/ |
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#include <linux/clk.h> |
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#include <linux/device.h> |
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#include <linux/dma-mapping.h> |
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#include <linux/io.h> |
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#include <linux/module.h> |
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#include <linux/of_platform.h> |
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#include <linux/platform_device.h> |
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#include <linux/pm_runtime.h> |
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#include <linux/reset.h> |
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#include <drm/drm_drv.h> |
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#include <drm/drm_fb_cma_helper.h> |
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#include <drm/drm_fb_helper.h> |
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#include <drm/drm_managed.h> |
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#include <uapi/drm/v3d_drm.h> |
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#include "v3d_drv.h" |
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#include "v3d_regs.h" |
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#define DRIVER_NAME "v3d" |
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#define DRIVER_DESC "Broadcom V3D graphics" |
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#define DRIVER_DATE "20180419" |
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#define DRIVER_MAJOR 1 |
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#define DRIVER_MINOR 0 |
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#define DRIVER_PATCHLEVEL 0 |
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#ifdef CONFIG_PM |
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static int v3d_runtime_suspend(struct device *dev) |
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{ |
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struct drm_device *drm = dev_get_drvdata(dev); |
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struct v3d_dev *v3d = to_v3d_dev(drm); |
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v3d_irq_disable(v3d); |
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clk_disable_unprepare(v3d->clk); |
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return 0; |
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} |
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static int v3d_runtime_resume(struct device *dev) |
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{ |
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struct drm_device *drm = dev_get_drvdata(dev); |
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struct v3d_dev *v3d = to_v3d_dev(drm); |
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int ret; |
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ret = clk_prepare_enable(v3d->clk); |
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if (ret != 0) |
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return ret; |
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/* XXX: VPM base */ |
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v3d_mmu_set_page_table(v3d); |
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v3d_irq_enable(v3d); |
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return 0; |
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} |
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#endif |
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static const struct dev_pm_ops v3d_pm_ops = { |
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SET_RUNTIME_PM_OPS(v3d_runtime_suspend, v3d_runtime_resume, NULL) |
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}; |
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static int v3d_get_param_ioctl(struct drm_device *dev, void *data, |
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struct drm_file *file_priv) |
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{ |
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struct v3d_dev *v3d = to_v3d_dev(dev); |
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struct drm_v3d_get_param *args = data; |
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static const u32 reg_map[] = { |
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[DRM_V3D_PARAM_V3D_UIFCFG] = V3D_HUB_UIFCFG, |
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[DRM_V3D_PARAM_V3D_HUB_IDENT1] = V3D_HUB_IDENT1, |
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[DRM_V3D_PARAM_V3D_HUB_IDENT2] = V3D_HUB_IDENT2, |
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[DRM_V3D_PARAM_V3D_HUB_IDENT3] = V3D_HUB_IDENT3, |
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[DRM_V3D_PARAM_V3D_CORE0_IDENT0] = V3D_CTL_IDENT0, |
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[DRM_V3D_PARAM_V3D_CORE0_IDENT1] = V3D_CTL_IDENT1, |
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[DRM_V3D_PARAM_V3D_CORE0_IDENT2] = V3D_CTL_IDENT2, |
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}; |
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if (args->pad != 0) |
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return -EINVAL; |
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/* Note that DRM_V3D_PARAM_V3D_CORE0_IDENT0 is 0, so we need |
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* to explicitly allow it in the "the register in our |
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* parameter map" check. |
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*/ |
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if (args->param < ARRAY_SIZE(reg_map) && |
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(reg_map[args->param] || |
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args->param == DRM_V3D_PARAM_V3D_CORE0_IDENT0)) { |
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u32 offset = reg_map[args->param]; |
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if (args->value != 0) |
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return -EINVAL; |
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if (args->param >= DRM_V3D_PARAM_V3D_CORE0_IDENT0 && |
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args->param <= DRM_V3D_PARAM_V3D_CORE0_IDENT2) { |
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args->value = V3D_CORE_READ(0, offset); |
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} else { |
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args->value = V3D_READ(offset); |
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} |
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return 0; |
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} |
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switch (args->param) { |
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case DRM_V3D_PARAM_SUPPORTS_TFU: |
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args->value = 1; |
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return 0; |
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case DRM_V3D_PARAM_SUPPORTS_CSD: |
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args->value = v3d_has_csd(v3d); |
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return 0; |
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case DRM_V3D_PARAM_SUPPORTS_CACHE_FLUSH: |
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args->value = 1; |
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return 0; |
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case DRM_V3D_PARAM_SUPPORTS_PERFMON: |
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args->value = (v3d->ver >= 40); |
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return 0; |
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case DRM_V3D_PARAM_SUPPORTS_MULTISYNC_EXT: |
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args->value = 1; |
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return 0; |
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default: |
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DRM_DEBUG("Unknown parameter %d\n", args->param); |
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return -EINVAL; |
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} |
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} |
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static int |
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v3d_open(struct drm_device *dev, struct drm_file *file) |
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{ |
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struct v3d_dev *v3d = to_v3d_dev(dev); |
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struct v3d_file_priv *v3d_priv; |
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struct drm_gpu_scheduler *sched; |
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int i; |
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v3d_priv = kzalloc(sizeof(*v3d_priv), GFP_KERNEL); |
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if (!v3d_priv) |
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return -ENOMEM; |
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v3d_priv->v3d = v3d; |
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for (i = 0; i < V3D_MAX_QUEUES; i++) { |
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sched = &v3d->queue[i].sched; |
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drm_sched_entity_init(&v3d_priv->sched_entity[i], |
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DRM_SCHED_PRIORITY_NORMAL, &sched, |
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1, NULL); |
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} |
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v3d_perfmon_open_file(v3d_priv); |
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file->driver_priv = v3d_priv; |
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return 0; |
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} |
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static void |
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v3d_postclose(struct drm_device *dev, struct drm_file *file) |
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{ |
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struct v3d_file_priv *v3d_priv = file->driver_priv; |
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enum v3d_queue q; |
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for (q = 0; q < V3D_MAX_QUEUES; q++) |
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drm_sched_entity_destroy(&v3d_priv->sched_entity[q]); |
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v3d_perfmon_close_file(v3d_priv); |
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kfree(v3d_priv); |
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} |
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DEFINE_DRM_GEM_FOPS(v3d_drm_fops); |
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/* DRM_AUTH is required on SUBMIT_CL for now, while we don't have GMP |
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* protection between clients. Note that render nodes would be |
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* able to submit CLs that could access BOs from clients authenticated |
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* with the master node. The TFU doesn't use the GMP, so it would |
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* need to stay DRM_AUTH until we do buffer size/offset validation. |
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*/ |
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static const struct drm_ioctl_desc v3d_drm_ioctls[] = { |
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DRM_IOCTL_DEF_DRV(V3D_SUBMIT_CL, v3d_submit_cl_ioctl, DRM_RENDER_ALLOW | DRM_AUTH), |
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DRM_IOCTL_DEF_DRV(V3D_WAIT_BO, v3d_wait_bo_ioctl, DRM_RENDER_ALLOW), |
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DRM_IOCTL_DEF_DRV(V3D_CREATE_BO, v3d_create_bo_ioctl, DRM_RENDER_ALLOW), |
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DRM_IOCTL_DEF_DRV(V3D_MMAP_BO, v3d_mmap_bo_ioctl, DRM_RENDER_ALLOW), |
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DRM_IOCTL_DEF_DRV(V3D_GET_PARAM, v3d_get_param_ioctl, DRM_RENDER_ALLOW), |
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DRM_IOCTL_DEF_DRV(V3D_GET_BO_OFFSET, v3d_get_bo_offset_ioctl, DRM_RENDER_ALLOW), |
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DRM_IOCTL_DEF_DRV(V3D_SUBMIT_TFU, v3d_submit_tfu_ioctl, DRM_RENDER_ALLOW | DRM_AUTH), |
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DRM_IOCTL_DEF_DRV(V3D_SUBMIT_CSD, v3d_submit_csd_ioctl, DRM_RENDER_ALLOW | DRM_AUTH), |
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DRM_IOCTL_DEF_DRV(V3D_PERFMON_CREATE, v3d_perfmon_create_ioctl, DRM_RENDER_ALLOW), |
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DRM_IOCTL_DEF_DRV(V3D_PERFMON_DESTROY, v3d_perfmon_destroy_ioctl, DRM_RENDER_ALLOW), |
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DRM_IOCTL_DEF_DRV(V3D_PERFMON_GET_VALUES, v3d_perfmon_get_values_ioctl, DRM_RENDER_ALLOW), |
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}; |
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static const struct drm_driver v3d_drm_driver = { |
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.driver_features = (DRIVER_GEM | |
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DRIVER_RENDER | |
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DRIVER_SYNCOBJ), |
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.open = v3d_open, |
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.postclose = v3d_postclose, |
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#if defined(CONFIG_DEBUG_FS) |
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.debugfs_init = v3d_debugfs_init, |
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#endif |
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.gem_create_object = v3d_create_object, |
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.prime_handle_to_fd = drm_gem_prime_handle_to_fd, |
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.prime_fd_to_handle = drm_gem_prime_fd_to_handle, |
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.gem_prime_import_sg_table = v3d_prime_import_sg_table, |
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.gem_prime_mmap = drm_gem_prime_mmap, |
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.ioctls = v3d_drm_ioctls, |
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.num_ioctls = ARRAY_SIZE(v3d_drm_ioctls), |
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.fops = &v3d_drm_fops, |
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.name = DRIVER_NAME, |
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.desc = DRIVER_DESC, |
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.date = DRIVER_DATE, |
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.major = DRIVER_MAJOR, |
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.minor = DRIVER_MINOR, |
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.patchlevel = DRIVER_PATCHLEVEL, |
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}; |
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static const struct of_device_id v3d_of_match[] = { |
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{ .compatible = "brcm,7268-v3d" }, |
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{ .compatible = "brcm,7278-v3d" }, |
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{ .compatible = "brcm,2711-v3d" }, |
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{}, |
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}; |
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MODULE_DEVICE_TABLE(of, v3d_of_match); |
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static int |
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map_regs(struct v3d_dev *v3d, void __iomem **regs, const char *name) |
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{ |
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*regs = devm_platform_ioremap_resource_byname(v3d_to_pdev(v3d), name); |
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return PTR_ERR_OR_ZERO(*regs); |
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} |
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static int v3d_platform_drm_probe(struct platform_device *pdev) |
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{ |
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struct device *dev = &pdev->dev; |
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struct drm_device *drm; |
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struct v3d_dev *v3d; |
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int ret; |
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u32 mmu_debug; |
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u32 ident1; |
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v3d = devm_drm_dev_alloc(dev, &v3d_drm_driver, struct v3d_dev, drm); |
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if (IS_ERR(v3d)) |
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return PTR_ERR(v3d); |
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drm = &v3d->drm; |
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platform_set_drvdata(pdev, drm); |
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ret = map_regs(v3d, &v3d->hub_regs, "hub"); |
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if (ret) |
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return ret; |
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ret = map_regs(v3d, &v3d->core_regs[0], "core0"); |
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if (ret) |
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return ret; |
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mmu_debug = V3D_READ(V3D_MMU_DEBUG_INFO); |
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dma_set_mask_and_coherent(dev, |
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DMA_BIT_MASK(30 + V3D_GET_FIELD(mmu_debug, V3D_MMU_PA_WIDTH))); |
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v3d->va_width = 30 + V3D_GET_FIELD(mmu_debug, V3D_MMU_VA_WIDTH); |
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ident1 = V3D_READ(V3D_HUB_IDENT1); |
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v3d->ver = (V3D_GET_FIELD(ident1, V3D_HUB_IDENT1_TVER) * 10 + |
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V3D_GET_FIELD(ident1, V3D_HUB_IDENT1_REV)); |
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v3d->cores = V3D_GET_FIELD(ident1, V3D_HUB_IDENT1_NCORES); |
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WARN_ON(v3d->cores > 1); /* multicore not yet implemented */ |
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v3d->reset = devm_reset_control_get_exclusive(dev, NULL); |
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if (IS_ERR(v3d->reset)) { |
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ret = PTR_ERR(v3d->reset); |
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if (ret == -EPROBE_DEFER) |
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return ret; |
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v3d->reset = NULL; |
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ret = map_regs(v3d, &v3d->bridge_regs, "bridge"); |
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if (ret) { |
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dev_err(dev, |
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"Failed to get reset control or bridge regs\n"); |
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return ret; |
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} |
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} |
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v3d->clk = devm_clk_get(dev, NULL); |
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if (IS_ERR_OR_NULL(v3d->clk)) { |
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if (PTR_ERR(v3d->clk) != -EPROBE_DEFER) |
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dev_err(dev, "Failed to get clock (%ld)\n", PTR_ERR(v3d->clk)); |
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return PTR_ERR(v3d->clk); |
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} |
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v3d->clk_up_rate = clk_get_rate(v3d->clk); |
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/* For downclocking, drop it to the minimum frequency we can get from |
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* the CPRMAN clock generator dividing off our parent. The divider is |
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* 4 bits, but ask for just higher than that so that rounding doesn't |
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* make cprman reject our rate. |
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*/ |
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v3d->clk_down_rate = |
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(clk_get_rate(clk_get_parent(v3d->clk)) / (1 << 4)) + 10000; |
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if (v3d->ver < 41) { |
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ret = map_regs(v3d, &v3d->gca_regs, "gca"); |
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if (ret) |
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return ret; |
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} |
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v3d->mmu_scratch = dma_alloc_wc(dev, 4096, &v3d->mmu_scratch_paddr, |
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GFP_KERNEL | __GFP_NOWARN | __GFP_ZERO); |
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if (!v3d->mmu_scratch) { |
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dev_err(dev, "Failed to allocate MMU scratch page\n"); |
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return -ENOMEM; |
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} |
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ret = v3d_gem_init(drm); |
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if (ret) |
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goto dma_free; |
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ret = v3d_irq_init(v3d); |
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if (ret) |
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goto gem_destroy; |
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ret = drm_dev_register(drm, 0); |
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if (ret) |
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goto irq_disable; |
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ret = clk_set_rate(v3d->clk, v3d->clk_down_rate); |
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WARN_ON_ONCE(ret != 0); |
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return 0; |
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irq_disable: |
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v3d_irq_disable(v3d); |
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gem_destroy: |
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v3d_gem_destroy(drm); |
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dma_free: |
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dma_free_wc(dev, 4096, v3d->mmu_scratch, v3d->mmu_scratch_paddr); |
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return ret; |
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} |
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static int v3d_platform_drm_remove(struct platform_device *pdev) |
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{ |
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struct drm_device *drm = platform_get_drvdata(pdev); |
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struct v3d_dev *v3d = to_v3d_dev(drm); |
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drm_dev_unregister(drm); |
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v3d_gem_destroy(drm); |
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dma_free_wc(v3d->drm.dev, 4096, v3d->mmu_scratch, |
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v3d->mmu_scratch_paddr); |
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return 0; |
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} |
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static struct platform_driver v3d_platform_driver = { |
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.probe = v3d_platform_drm_probe, |
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.remove = v3d_platform_drm_remove, |
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.driver = { |
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.name = "v3d", |
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.of_match_table = v3d_of_match, |
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.pm = &v3d_pm_ops, |
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}, |
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}; |
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module_platform_driver(v3d_platform_driver); |
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MODULE_ALIAS("platform:v3d-drm"); |
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MODULE_DESCRIPTION("Broadcom V3D DRM Driver"); |
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MODULE_AUTHOR("Eric Anholt <[email protected]>"); |
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MODULE_LICENSE("GPL v2");
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