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126 lines
2.8 KiB
126 lines
2.8 KiB
/* SPDX-License-Identifier: GPL-2.0 */ |
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/* |
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* Copyright (C) 2020 Unisoc Inc. |
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*/ |
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#ifndef __SPRD_DSI_H__ |
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#define __SPRD_DSI_H__ |
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#include <linux/of.h> |
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#include <linux/device.h> |
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#include <linux/regmap.h> |
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#include <video/videomode.h> |
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#include <drm/drm_bridge.h> |
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#include <drm/drm_connector.h> |
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#include <drm/drm_encoder.h> |
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#include <drm/drm_mipi_dsi.h> |
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#include <drm/drm_print.h> |
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#include <drm/drm_panel.h> |
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#define encoder_to_dsi(encoder) \ |
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container_of(encoder, struct sprd_dsi, encoder) |
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enum dsi_work_mode { |
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DSI_MODE_CMD = 0, |
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DSI_MODE_VIDEO |
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}; |
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enum video_burst_mode { |
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VIDEO_NON_BURST_WITH_SYNC_PULSES = 0, |
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VIDEO_NON_BURST_WITH_SYNC_EVENTS, |
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VIDEO_BURST_WITH_SYNC_PULSES |
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}; |
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enum dsi_color_coding { |
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COLOR_CODE_16BIT_CONFIG1 = 0, |
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COLOR_CODE_16BIT_CONFIG2, |
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COLOR_CODE_16BIT_CONFIG3, |
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COLOR_CODE_18BIT_CONFIG1, |
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COLOR_CODE_18BIT_CONFIG2, |
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COLOR_CODE_24BIT, |
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COLOR_CODE_20BIT_YCC422_LOOSELY, |
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COLOR_CODE_24BIT_YCC422, |
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COLOR_CODE_16BIT_YCC422, |
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COLOR_CODE_30BIT, |
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COLOR_CODE_36BIT, |
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COLOR_CODE_12BIT_YCC420, |
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COLOR_CODE_COMPRESSTION, |
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COLOR_CODE_MAX |
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}; |
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enum pll_timing { |
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NONE, |
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REQUEST_TIME, |
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PREPARE_TIME, |
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SETTLE_TIME, |
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ZERO_TIME, |
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TRAIL_TIME, |
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EXIT_TIME, |
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CLKPOST_TIME, |
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TA_GET, |
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TA_GO, |
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TA_SURE, |
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TA_WAIT, |
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}; |
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struct dphy_pll { |
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u8 refin; /* Pre-divider control signal */ |
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u8 cp_s; /* 00: SDM_EN=1, 10: SDM_EN=0 */ |
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u8 fdk_s; /* PLL mode control: integer or fraction */ |
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u8 sdm_en; |
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u8 div; |
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u8 int_n; /* integer N PLL */ |
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u32 ref_clk; /* dphy reference clock, unit: MHz */ |
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u32 freq; /* panel config, unit: KHz */ |
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u32 fvco; |
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u32 potential_fvco; |
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u32 nint; /* sigma delta modulator NINT control */ |
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u32 kint; /* sigma delta modulator KINT control */ |
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u8 lpf_sel; /* low pass filter control */ |
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u8 out_sel; /* post divider control */ |
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u8 vco_band; /* vco range */ |
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u8 det_delay; |
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}; |
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struct dsi_context { |
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void __iomem *base; |
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struct regmap *regmap; |
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struct dphy_pll pll; |
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struct videomode vm; |
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bool enabled; |
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u8 work_mode; |
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u8 burst_mode; |
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u32 int0_mask; |
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u32 int1_mask; |
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/* maximum time (ns) for data lanes from HS to LP */ |
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u16 data_hs2lp; |
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/* maximum time (ns) for data lanes from LP to HS */ |
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u16 data_lp2hs; |
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/* maximum time (ns) for clk lanes from HS to LP */ |
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u16 clk_hs2lp; |
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/* maximum time (ns) for clk lanes from LP to HS */ |
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u16 clk_lp2hs; |
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/* maximum time (ns) for BTA operation - REQUIRED */ |
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u16 max_rd_time; |
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/* enable receiving frame ack packets - for video mode */ |
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bool frame_ack_en; |
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/* enable receiving tear effect ack packets - for cmd mode */ |
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bool te_ack_en; |
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}; |
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struct sprd_dsi { |
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struct drm_device *drm; |
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struct mipi_dsi_host host; |
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struct mipi_dsi_device *slave; |
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struct drm_encoder encoder; |
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struct drm_bridge *panel_bridge; |
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struct dsi_context ctx; |
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}; |
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int dphy_pll_config(struct dsi_context *ctx); |
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void dphy_timing_config(struct dsi_context *ctx); |
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#endif /* __SPRD_DSI_H__ */
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