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365 lines
11 KiB
365 lines
11 KiB
// SPDX-License-Identifier: GPL-2.0+ |
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/* |
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* rcar_du_group.c -- R-Car Display Unit Channels Pair |
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* |
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* Copyright (C) 2013-2015 Renesas Electronics Corporation |
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* |
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* Contact: Laurent Pinchart ([email protected]) |
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*/ |
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/* |
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* The R8A7779 DU is split in per-CRTC resources (scan-out engine, blending |
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* unit, timings generator, ...) and device-global resources (start/stop |
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* control, planes, ...) shared between the two CRTCs. |
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* |
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* The R8A7790 introduced a third CRTC with its own set of global resources. |
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* This would be modeled as two separate DU device instances if it wasn't for |
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* a handful or resources that are shared between the three CRTCs (mostly |
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* related to input and output routing). For this reason the R8A7790 DU must be |
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* modeled as a single device with three CRTCs, two sets of "semi-global" |
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* resources, and a few device-global resources. |
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* |
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* The rcar_du_group object is a driver specific object, without any real |
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* counterpart in the DU documentation, that models those semi-global resources. |
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*/ |
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#include <linux/clk.h> |
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#include <linux/io.h> |
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#include "rcar_du_drv.h" |
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#include "rcar_du_group.h" |
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#include "rcar_du_regs.h" |
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u32 rcar_du_group_read(struct rcar_du_group *rgrp, u32 reg) |
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{ |
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return rcar_du_read(rgrp->dev, rgrp->mmio_offset + reg); |
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} |
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void rcar_du_group_write(struct rcar_du_group *rgrp, u32 reg, u32 data) |
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{ |
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rcar_du_write(rgrp->dev, rgrp->mmio_offset + reg, data); |
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} |
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static void rcar_du_group_setup_pins(struct rcar_du_group *rgrp) |
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{ |
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u32 defr6 = DEFR6_CODE; |
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if (rgrp->channels_mask & BIT(0)) |
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defr6 |= DEFR6_ODPM02_DISP; |
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if (rgrp->channels_mask & BIT(1)) |
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defr6 |= DEFR6_ODPM12_DISP; |
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rcar_du_group_write(rgrp, DEFR6, defr6); |
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} |
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static void rcar_du_group_setup_defr8(struct rcar_du_group *rgrp) |
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{ |
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struct rcar_du_device *rcdu = rgrp->dev; |
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u32 defr8 = DEFR8_CODE; |
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if (rcdu->info->gen < 3) { |
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defr8 |= DEFR8_DEFE8; |
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/* |
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* On Gen2 the DEFR8 register for the first group also controls |
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* RGB output routing to DPAD0 and VSPD1 routing to DU0/1/2 for |
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* DU instances that support it. |
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*/ |
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if (rgrp->index == 0) { |
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defr8 |= DEFR8_DRGBS_DU(rcdu->dpad0_source); |
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if (rgrp->dev->vspd1_sink == 2) |
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defr8 |= DEFR8_VSCS; |
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} |
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} else { |
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/* |
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* On Gen3 VSPD routing can't be configured, and DPAD routing |
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* is set in the group corresponding to the DPAD output (no Gen3 |
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* SoC has multiple DPAD sources belonging to separate groups). |
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*/ |
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if (rgrp->index == rcdu->dpad0_source / 2) |
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defr8 |= DEFR8_DRGBS_DU(rcdu->dpad0_source); |
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} |
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rcar_du_group_write(rgrp, DEFR8, defr8); |
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} |
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static void rcar_du_group_setup_didsr(struct rcar_du_group *rgrp) |
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{ |
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struct rcar_du_device *rcdu = rgrp->dev; |
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struct rcar_du_crtc *rcrtc; |
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unsigned int num_crtcs = 0; |
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unsigned int i; |
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u32 didsr; |
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/* |
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* Configure input dot clock routing with a hardcoded configuration. If |
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* the DU channel can use the LVDS encoder output clock as the dot |
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* clock, do so. Otherwise route DU_DOTCLKINn signal to DUn. |
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* |
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* Each channel can then select between the dot clock configured here |
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* and the clock provided by the CPG through the ESCR register. |
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*/ |
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if (rcdu->info->gen < 3 && rgrp->index == 0) { |
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/* |
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* On Gen2 a single register in the first group controls dot |
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* clock selection for all channels. |
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*/ |
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rcrtc = rcdu->crtcs; |
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num_crtcs = rcdu->num_crtcs; |
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} else if (rcdu->info->gen == 3 && rgrp->num_crtcs > 1) { |
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/* |
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* On Gen3 dot clocks are setup through per-group registers, |
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* only available when the group has two channels. |
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*/ |
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rcrtc = &rcdu->crtcs[rgrp->index * 2]; |
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num_crtcs = rgrp->num_crtcs; |
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} |
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if (!num_crtcs) |
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return; |
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didsr = DIDSR_CODE; |
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for (i = 0; i < num_crtcs; ++i, ++rcrtc) { |
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if (rcdu->info->lvds_clk_mask & BIT(rcrtc->index)) |
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didsr |= DIDSR_LDCS_LVDS0(i) |
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| DIDSR_PDCS_CLK(i, 0); |
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else if (rcdu->info->dsi_clk_mask & BIT(rcrtc->index)) |
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didsr |= DIDSR_LDCS_DSI(i); |
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else |
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didsr |= DIDSR_LDCS_DCLKIN(i) |
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| DIDSR_PDCS_CLK(i, 0); |
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} |
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rcar_du_group_write(rgrp, DIDSR, didsr); |
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} |
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static void rcar_du_group_setup(struct rcar_du_group *rgrp) |
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{ |
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struct rcar_du_device *rcdu = rgrp->dev; |
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u32 defr7 = DEFR7_CODE; |
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/* Enable extended features */ |
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rcar_du_group_write(rgrp, DEFR, DEFR_CODE | DEFR_DEFE); |
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if (rcdu->info->gen < 3) { |
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rcar_du_group_write(rgrp, DEFR2, DEFR2_CODE | DEFR2_DEFE2G); |
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rcar_du_group_write(rgrp, DEFR3, DEFR3_CODE | DEFR3_DEFE3); |
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rcar_du_group_write(rgrp, DEFR4, DEFR4_CODE); |
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} |
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rcar_du_group_write(rgrp, DEFR5, DEFR5_CODE | DEFR5_DEFE5); |
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rcar_du_group_setup_pins(rgrp); |
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/* |
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* TODO: Handle routing of the DU output to CMM dynamically, as we |
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* should bypass CMM completely when no color management feature is |
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* used. |
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*/ |
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defr7 |= (rgrp->cmms_mask & BIT(1) ? DEFR7_CMME1 : 0) | |
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(rgrp->cmms_mask & BIT(0) ? DEFR7_CMME0 : 0); |
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rcar_du_group_write(rgrp, DEFR7, defr7); |
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if (rcdu->info->gen >= 2) { |
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rcar_du_group_setup_defr8(rgrp); |
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rcar_du_group_setup_didsr(rgrp); |
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} |
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if (rcdu->info->gen >= 3) |
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rcar_du_group_write(rgrp, DEFR10, DEFR10_CODE | DEFR10_DEFE10); |
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/* |
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* Use DS1PR and DS2PR to configure planes priorities and connects the |
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* superposition 0 to DU0 pins. DU1 pins will be configured dynamically. |
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*/ |
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rcar_du_group_write(rgrp, DORCR, DORCR_PG1D_DS1 | DORCR_DPRS); |
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/* Apply planes to CRTCs association. */ |
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mutex_lock(&rgrp->lock); |
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rcar_du_group_write(rgrp, DPTSR, (rgrp->dptsr_planes << 16) | |
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rgrp->dptsr_planes); |
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mutex_unlock(&rgrp->lock); |
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} |
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/* |
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* rcar_du_group_get - Acquire a reference to the DU channels group |
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* |
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* Acquiring the first reference setups core registers. A reference must be held |
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* before accessing any hardware registers. |
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* |
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* This function must be called with the DRM mode_config lock held. |
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* |
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* Return 0 in case of success or a negative error code otherwise. |
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*/ |
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int rcar_du_group_get(struct rcar_du_group *rgrp) |
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{ |
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if (rgrp->use_count) |
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goto done; |
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rcar_du_group_setup(rgrp); |
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done: |
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rgrp->use_count++; |
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return 0; |
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} |
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/* |
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* rcar_du_group_put - Release a reference to the DU |
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* |
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* This function must be called with the DRM mode_config lock held. |
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*/ |
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void rcar_du_group_put(struct rcar_du_group *rgrp) |
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{ |
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--rgrp->use_count; |
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} |
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static void __rcar_du_group_start_stop(struct rcar_du_group *rgrp, bool start) |
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{ |
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struct rcar_du_device *rcdu = rgrp->dev; |
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/* |
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* Group start/stop is controlled by the DRES and DEN bits of DSYSR0 |
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* for the first group and DSYSR2 for the second group. On most DU |
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* instances, this maps to the first CRTC of the group, and we can just |
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* use rcar_du_crtc_dsysr_clr_set() to access the correct DSYSR. On |
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* M3-N, however, DU2 doesn't exist, but DSYSR2 does. We thus need to |
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* access the register directly using group read/write. |
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*/ |
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if (rcdu->info->channels_mask & BIT(rgrp->index * 2)) { |
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struct rcar_du_crtc *rcrtc = &rgrp->dev->crtcs[rgrp->index * 2]; |
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rcar_du_crtc_dsysr_clr_set(rcrtc, DSYSR_DRES | DSYSR_DEN, |
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start ? DSYSR_DEN : DSYSR_DRES); |
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} else { |
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rcar_du_group_write(rgrp, DSYSR, |
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start ? DSYSR_DEN : DSYSR_DRES); |
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} |
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} |
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void rcar_du_group_start_stop(struct rcar_du_group *rgrp, bool start) |
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{ |
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/* |
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* Many of the configuration bits are only updated when the display |
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* reset (DRES) bit in DSYSR is set to 1, disabling *both* CRTCs. Some |
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* of those bits could be pre-configured, but others (especially the |
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* bits related to plane assignment to display timing controllers) need |
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* to be modified at runtime. |
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* |
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* Restart the display controller if a start is requested. Sorry for the |
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* flicker. It should be possible to move most of the "DRES-update" bits |
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* setup to driver initialization time and minimize the number of cases |
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* when the display controller will have to be restarted. |
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*/ |
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if (start) { |
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if (rgrp->used_crtcs++ != 0) |
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__rcar_du_group_start_stop(rgrp, false); |
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__rcar_du_group_start_stop(rgrp, true); |
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} else { |
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if (--rgrp->used_crtcs == 0) |
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__rcar_du_group_start_stop(rgrp, false); |
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} |
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} |
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void rcar_du_group_restart(struct rcar_du_group *rgrp) |
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{ |
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rgrp->need_restart = false; |
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__rcar_du_group_start_stop(rgrp, false); |
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__rcar_du_group_start_stop(rgrp, true); |
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} |
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int rcar_du_set_dpad0_vsp1_routing(struct rcar_du_device *rcdu) |
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{ |
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struct rcar_du_group *rgrp; |
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struct rcar_du_crtc *crtc; |
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unsigned int index; |
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int ret; |
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if (rcdu->info->gen < 2) |
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return 0; |
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/* |
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* RGB output routing to DPAD0 and VSP1D routing to DU0/1/2 are |
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* configured in the DEFR8 register of the first group on Gen2 and the |
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* last group on Gen3. As this function can be called with the DU |
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* channels of the corresponding CRTCs disabled, we need to enable the |
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* group clock before accessing the register. |
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*/ |
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index = rcdu->info->gen < 3 ? 0 : DIV_ROUND_UP(rcdu->num_crtcs, 2) - 1; |
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rgrp = &rcdu->groups[index]; |
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crtc = &rcdu->crtcs[index * 2]; |
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ret = clk_prepare_enable(crtc->clock); |
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if (ret < 0) |
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return ret; |
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rcar_du_group_setup_defr8(rgrp); |
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clk_disable_unprepare(crtc->clock); |
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return 0; |
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} |
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static void rcar_du_group_set_dpad_levels(struct rcar_du_group *rgrp) |
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{ |
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static const u32 doflr_values[2] = { |
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DOFLR_HSYCFL0 | DOFLR_VSYCFL0 | DOFLR_ODDFL0 | |
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DOFLR_DISPFL0 | DOFLR_CDEFL0 | DOFLR_RGBFL0, |
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DOFLR_HSYCFL1 | DOFLR_VSYCFL1 | DOFLR_ODDFL1 | |
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DOFLR_DISPFL1 | DOFLR_CDEFL1 | DOFLR_RGBFL1, |
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}; |
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static const u32 dpad_mask = BIT(RCAR_DU_OUTPUT_DPAD1) |
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| BIT(RCAR_DU_OUTPUT_DPAD0); |
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struct rcar_du_device *rcdu = rgrp->dev; |
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u32 doflr = DOFLR_CODE; |
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unsigned int i; |
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if (rcdu->info->gen < 2) |
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return; |
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/* |
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* The DPAD outputs can't be controlled directly. However, the parallel |
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* output of the DU channels routed to DPAD can be set to fixed levels |
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* through the DOFLR group register. Use this to turn the DPAD on or off |
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* by driving fixed low-level signals at the output of any DU channel |
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* not routed to a DPAD output. This doesn't affect the DU output |
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* signals going to other outputs, such as the internal LVDS and HDMI |
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* encoders. |
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*/ |
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for (i = 0; i < rgrp->num_crtcs; ++i) { |
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struct rcar_du_crtc_state *rstate; |
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struct rcar_du_crtc *rcrtc; |
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rcrtc = &rcdu->crtcs[rgrp->index * 2 + i]; |
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rstate = to_rcar_crtc_state(rcrtc->crtc.state); |
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if (!(rstate->outputs & dpad_mask)) |
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doflr |= doflr_values[i]; |
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} |
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rcar_du_group_write(rgrp, DOFLR, doflr); |
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} |
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int rcar_du_group_set_routing(struct rcar_du_group *rgrp) |
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{ |
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struct rcar_du_device *rcdu = rgrp->dev; |
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u32 dorcr = rcar_du_group_read(rgrp, DORCR); |
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dorcr &= ~(DORCR_PG2T | DORCR_DK2S | DORCR_PG2D_MASK); |
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/* |
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* Set the DPAD1 pins sources. Select CRTC 0 if explicitly requested and |
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* CRTC 1 in all other cases to avoid cloning CRTC 0 to DPAD0 and DPAD1 |
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* by default. |
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*/ |
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if (rcdu->dpad1_source == rgrp->index * 2) |
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dorcr |= DORCR_PG2D_DS1; |
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else |
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dorcr |= DORCR_PG2T | DORCR_DK2S | DORCR_PG2D_DS2; |
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rcar_du_group_write(rgrp, DORCR, dorcr); |
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rcar_du_group_set_dpad_levels(rgrp); |
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return rcar_du_set_dpad0_vsp1_routing(rgrp->dev); |
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}
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