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653 lines
19 KiB
653 lines
19 KiB
// SPDX-License-Identifier: GPL-2.0-or-later |
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/* |
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* Copyright (C) 2016 Marek Vasut <[email protected]> |
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* |
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* This code is based on drivers/video/fbdev/mxsfb.c : |
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* Copyright (C) 2010 Juergen Beisert, Pengutronix |
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* Copyright (C) 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. |
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* Copyright (C) 2008 Embedded Alley Solutions, Inc All Rights Reserved. |
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*/ |
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|
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#include <linux/clk.h> |
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#include <linux/io.h> |
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#include <linux/iopoll.h> |
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#include <linux/pm_runtime.h> |
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#include <linux/spinlock.h> |
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|
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#include <drm/drm_atomic.h> |
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#include <drm/drm_atomic_helper.h> |
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#include <drm/drm_bridge.h> |
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#include <drm/drm_crtc.h> |
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#include <drm/drm_encoder.h> |
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#include <drm/drm_fb_cma_helper.h> |
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#include <drm/drm_fourcc.h> |
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#include <drm/drm_gem_atomic_helper.h> |
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#include <drm/drm_gem_cma_helper.h> |
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#include <drm/drm_plane.h> |
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#include <drm/drm_plane_helper.h> |
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#include <drm/drm_vblank.h> |
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#include "mxsfb_drv.h" |
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#include "mxsfb_regs.h" |
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/* 1 second delay should be plenty of time for block reset */ |
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#define RESET_TIMEOUT 1000000 |
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|
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/* ----------------------------------------------------------------------------- |
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* CRTC |
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*/ |
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static u32 set_hsync_pulse_width(struct mxsfb_drm_private *mxsfb, u32 val) |
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{ |
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return (val & mxsfb->devdata->hs_wdth_mask) << |
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mxsfb->devdata->hs_wdth_shift; |
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} |
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/* |
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* Setup the MXSFB registers for decoding the pixels out of the framebuffer and |
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* outputting them on the bus. |
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*/ |
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static void mxsfb_set_formats(struct mxsfb_drm_private *mxsfb, |
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const u32 bus_format) |
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{ |
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struct drm_device *drm = mxsfb->drm; |
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const u32 format = mxsfb->crtc.primary->state->fb->format->format; |
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u32 ctrl, ctrl1; |
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DRM_DEV_DEBUG_DRIVER(drm->dev, "Using bus_format: 0x%08X\n", |
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bus_format); |
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ctrl = CTRL_BYPASS_COUNT | CTRL_MASTER; |
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/* CTRL1 contains IRQ config and status bits, preserve those. */ |
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ctrl1 = readl(mxsfb->base + LCDC_CTRL1); |
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ctrl1 &= CTRL1_CUR_FRAME_DONE_IRQ_EN | CTRL1_CUR_FRAME_DONE_IRQ; |
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switch (format) { |
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case DRM_FORMAT_RGB565: |
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dev_dbg(drm->dev, "Setting up RGB565 mode\n"); |
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ctrl |= CTRL_WORD_LENGTH_16; |
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ctrl1 |= CTRL1_SET_BYTE_PACKAGING(0xf); |
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break; |
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case DRM_FORMAT_XRGB8888: |
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dev_dbg(drm->dev, "Setting up XRGB8888 mode\n"); |
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ctrl |= CTRL_WORD_LENGTH_24; |
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/* Do not use packed pixels = one pixel per word instead. */ |
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ctrl1 |= CTRL1_SET_BYTE_PACKAGING(0x7); |
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break; |
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} |
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switch (bus_format) { |
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case MEDIA_BUS_FMT_RGB565_1X16: |
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ctrl |= CTRL_BUS_WIDTH_16; |
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break; |
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case MEDIA_BUS_FMT_RGB666_1X18: |
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ctrl |= CTRL_BUS_WIDTH_18; |
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break; |
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case MEDIA_BUS_FMT_RGB888_1X24: |
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ctrl |= CTRL_BUS_WIDTH_24; |
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break; |
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default: |
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dev_err(drm->dev, "Unknown media bus format 0x%x\n", bus_format); |
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break; |
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} |
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writel(ctrl1, mxsfb->base + LCDC_CTRL1); |
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writel(ctrl, mxsfb->base + LCDC_CTRL); |
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} |
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static void mxsfb_enable_controller(struct mxsfb_drm_private *mxsfb) |
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{ |
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u32 reg; |
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if (mxsfb->clk_disp_axi) |
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clk_prepare_enable(mxsfb->clk_disp_axi); |
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clk_prepare_enable(mxsfb->clk); |
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/* Increase number of outstanding requests on all supported IPs */ |
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if (mxsfb->devdata->has_ctrl2) { |
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reg = readl(mxsfb->base + LCDC_V4_CTRL2); |
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reg &= ~CTRL2_SET_OUTSTANDING_REQS_MASK; |
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reg |= CTRL2_SET_OUTSTANDING_REQS_16; |
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writel(reg, mxsfb->base + LCDC_V4_CTRL2); |
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} |
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/* If it was disabled, re-enable the mode again */ |
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writel(CTRL_DOTCLK_MODE, mxsfb->base + LCDC_CTRL + REG_SET); |
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/* Enable the SYNC signals first, then the DMA engine */ |
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reg = readl(mxsfb->base + LCDC_VDCTRL4); |
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reg |= VDCTRL4_SYNC_SIGNALS_ON; |
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writel(reg, mxsfb->base + LCDC_VDCTRL4); |
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/* |
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* Enable recovery on underflow. |
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* |
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* There is some sort of corner case behavior of the controller, |
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* which could rarely be triggered at least on i.MX6SX connected |
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* to 800x480 DPI panel and i.MX8MM connected to DPI->DSI->LVDS |
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* bridged 1920x1080 panel (and likely on other setups too), where |
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* the image on the panel shifts to the right and wraps around. |
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* This happens either when the controller is enabled on boot or |
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* even later during run time. The condition does not correct |
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* itself automatically, i.e. the display image remains shifted. |
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* |
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* It seems this problem is known and is due to sporadic underflows |
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* of the LCDIF FIFO. While the LCDIF IP does have underflow/overflow |
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* IRQs, neither of the IRQs trigger and neither IRQ status bit is |
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* asserted when this condition occurs. |
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* |
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* All known revisions of the LCDIF IP have CTRL1 RECOVER_ON_UNDERFLOW |
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* bit, which is described in the reference manual since i.MX23 as |
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* " |
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* Set this bit to enable the LCDIF block to recover in the next |
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* field/frame if there was an underflow in the current field/frame. |
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* " |
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* Enable this bit to mitigate the sporadic underflows. |
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*/ |
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reg = readl(mxsfb->base + LCDC_CTRL1); |
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reg |= CTRL1_RECOVER_ON_UNDERFLOW; |
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writel(reg, mxsfb->base + LCDC_CTRL1); |
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writel(CTRL_RUN, mxsfb->base + LCDC_CTRL + REG_SET); |
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} |
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static void mxsfb_disable_controller(struct mxsfb_drm_private *mxsfb) |
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{ |
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u32 reg; |
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/* |
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* Even if we disable the controller here, it will still continue |
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* until its FIFOs are running out of data |
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*/ |
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writel(CTRL_DOTCLK_MODE, mxsfb->base + LCDC_CTRL + REG_CLR); |
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readl_poll_timeout(mxsfb->base + LCDC_CTRL, reg, !(reg & CTRL_RUN), |
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0, 1000); |
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reg = readl(mxsfb->base + LCDC_VDCTRL4); |
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reg &= ~VDCTRL4_SYNC_SIGNALS_ON; |
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writel(reg, mxsfb->base + LCDC_VDCTRL4); |
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clk_disable_unprepare(mxsfb->clk); |
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if (mxsfb->clk_disp_axi) |
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clk_disable_unprepare(mxsfb->clk_disp_axi); |
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} |
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/* |
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* Clear the bit and poll it cleared. This is usually called with |
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* a reset address and mask being either SFTRST(bit 31) or CLKGATE |
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* (bit 30). |
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*/ |
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static int clear_poll_bit(void __iomem *addr, u32 mask) |
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{ |
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u32 reg; |
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writel(mask, addr + REG_CLR); |
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return readl_poll_timeout(addr, reg, !(reg & mask), 0, RESET_TIMEOUT); |
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} |
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static int mxsfb_reset_block(struct mxsfb_drm_private *mxsfb) |
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{ |
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int ret; |
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ret = clear_poll_bit(mxsfb->base + LCDC_CTRL, CTRL_SFTRST); |
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if (ret) |
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return ret; |
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writel(CTRL_CLKGATE, mxsfb->base + LCDC_CTRL + REG_CLR); |
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ret = clear_poll_bit(mxsfb->base + LCDC_CTRL, CTRL_SFTRST); |
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if (ret) |
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return ret; |
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return clear_poll_bit(mxsfb->base + LCDC_CTRL, CTRL_CLKGATE); |
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} |
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static dma_addr_t mxsfb_get_fb_paddr(struct drm_plane *plane) |
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{ |
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struct drm_framebuffer *fb = plane->state->fb; |
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struct drm_gem_cma_object *gem; |
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if (!fb) |
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return 0; |
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gem = drm_fb_cma_get_gem_obj(fb, 0); |
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if (!gem) |
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return 0; |
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return gem->paddr; |
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} |
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static void mxsfb_crtc_mode_set_nofb(struct mxsfb_drm_private *mxsfb, |
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const u32 bus_format) |
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{ |
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struct drm_device *drm = mxsfb->crtc.dev; |
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struct drm_display_mode *m = &mxsfb->crtc.state->adjusted_mode; |
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u32 bus_flags = mxsfb->connector->display_info.bus_flags; |
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u32 vdctrl0, vsync_pulse_len, hsync_pulse_len; |
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int err; |
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/* |
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* It seems, you can't re-program the controller if it is still |
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* running. This may lead to shifted pictures (FIFO issue?), so |
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* first stop the controller and drain its FIFOs. |
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*/ |
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/* Mandatory eLCDIF reset as per the Reference Manual */ |
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err = mxsfb_reset_block(mxsfb); |
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if (err) |
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return; |
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/* Clear the FIFOs */ |
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writel(CTRL1_FIFO_CLEAR, mxsfb->base + LCDC_CTRL1 + REG_SET); |
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readl(mxsfb->base + LCDC_CTRL1); |
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writel(CTRL1_FIFO_CLEAR, mxsfb->base + LCDC_CTRL1 + REG_CLR); |
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readl(mxsfb->base + LCDC_CTRL1); |
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if (mxsfb->devdata->has_overlay) |
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writel(0, mxsfb->base + LCDC_AS_CTRL); |
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mxsfb_set_formats(mxsfb, bus_format); |
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clk_set_rate(mxsfb->clk, m->crtc_clock * 1000); |
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if (mxsfb->bridge && mxsfb->bridge->timings) |
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bus_flags = mxsfb->bridge->timings->input_bus_flags; |
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DRM_DEV_DEBUG_DRIVER(drm->dev, "Pixel clock: %dkHz (actual: %dkHz)\n", |
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m->crtc_clock, |
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(int)(clk_get_rate(mxsfb->clk) / 1000)); |
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DRM_DEV_DEBUG_DRIVER(drm->dev, "Connector bus_flags: 0x%08X\n", |
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bus_flags); |
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DRM_DEV_DEBUG_DRIVER(drm->dev, "Mode flags: 0x%08X\n", m->flags); |
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writel(TRANSFER_COUNT_SET_VCOUNT(m->crtc_vdisplay) | |
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TRANSFER_COUNT_SET_HCOUNT(m->crtc_hdisplay), |
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mxsfb->base + mxsfb->devdata->transfer_count); |
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vsync_pulse_len = m->crtc_vsync_end - m->crtc_vsync_start; |
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vdctrl0 = VDCTRL0_ENABLE_PRESENT | /* Always in DOTCLOCK mode */ |
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VDCTRL0_VSYNC_PERIOD_UNIT | |
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VDCTRL0_VSYNC_PULSE_WIDTH_UNIT | |
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VDCTRL0_SET_VSYNC_PULSE_WIDTH(vsync_pulse_len); |
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if (m->flags & DRM_MODE_FLAG_PHSYNC) |
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vdctrl0 |= VDCTRL0_HSYNC_ACT_HIGH; |
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if (m->flags & DRM_MODE_FLAG_PVSYNC) |
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vdctrl0 |= VDCTRL0_VSYNC_ACT_HIGH; |
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/* Make sure Data Enable is high active by default */ |
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if (!(bus_flags & DRM_BUS_FLAG_DE_LOW)) |
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vdctrl0 |= VDCTRL0_ENABLE_ACT_HIGH; |
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/* |
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* DRM_BUS_FLAG_PIXDATA_DRIVE_ defines are controller centric, |
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* controllers VDCTRL0_DOTCLK is display centric. |
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* Drive on positive edge -> display samples on falling edge |
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* DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE -> VDCTRL0_DOTCLK_ACT_FALLING |
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*/ |
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if (bus_flags & DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE) |
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vdctrl0 |= VDCTRL0_DOTCLK_ACT_FALLING; |
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writel(vdctrl0, mxsfb->base + LCDC_VDCTRL0); |
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/* Frame length in lines. */ |
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writel(m->crtc_vtotal, mxsfb->base + LCDC_VDCTRL1); |
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/* Line length in units of clocks or pixels. */ |
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hsync_pulse_len = m->crtc_hsync_end - m->crtc_hsync_start; |
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writel(set_hsync_pulse_width(mxsfb, hsync_pulse_len) | |
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VDCTRL2_SET_HSYNC_PERIOD(m->crtc_htotal), |
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mxsfb->base + LCDC_VDCTRL2); |
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writel(SET_HOR_WAIT_CNT(m->crtc_htotal - m->crtc_hsync_start) | |
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SET_VERT_WAIT_CNT(m->crtc_vtotal - m->crtc_vsync_start), |
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mxsfb->base + LCDC_VDCTRL3); |
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writel(SET_DOTCLK_H_VALID_DATA_CNT(m->hdisplay), |
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mxsfb->base + LCDC_VDCTRL4); |
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} |
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static int mxsfb_crtc_atomic_check(struct drm_crtc *crtc, |
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struct drm_atomic_state *state) |
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{ |
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struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, |
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crtc); |
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bool has_primary = crtc_state->plane_mask & |
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drm_plane_mask(crtc->primary); |
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/* The primary plane has to be enabled when the CRTC is active. */ |
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if (crtc_state->active && !has_primary) |
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return -EINVAL; |
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/* TODO: Is this needed ? */ |
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return drm_atomic_add_affected_planes(state, crtc); |
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} |
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static void mxsfb_crtc_atomic_flush(struct drm_crtc *crtc, |
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struct drm_atomic_state *state) |
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{ |
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struct drm_pending_vblank_event *event; |
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event = crtc->state->event; |
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crtc->state->event = NULL; |
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if (!event) |
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return; |
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spin_lock_irq(&crtc->dev->event_lock); |
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if (drm_crtc_vblank_get(crtc) == 0) |
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drm_crtc_arm_vblank_event(crtc, event); |
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else |
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drm_crtc_send_vblank_event(crtc, event); |
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spin_unlock_irq(&crtc->dev->event_lock); |
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} |
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static void mxsfb_crtc_atomic_enable(struct drm_crtc *crtc, |
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struct drm_atomic_state *state) |
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{ |
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struct mxsfb_drm_private *mxsfb = to_mxsfb_drm_private(crtc->dev); |
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struct drm_bridge_state *bridge_state; |
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struct drm_device *drm = mxsfb->drm; |
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u32 bus_format = 0; |
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dma_addr_t paddr; |
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pm_runtime_get_sync(drm->dev); |
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mxsfb_enable_axi_clk(mxsfb); |
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drm_crtc_vblank_on(crtc); |
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/* If there is a bridge attached to the LCDIF, use its bus format */ |
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if (mxsfb->bridge) { |
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bridge_state = |
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drm_atomic_get_new_bridge_state(state, |
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mxsfb->bridge); |
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if (!bridge_state) |
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bus_format = MEDIA_BUS_FMT_FIXED; |
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else |
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bus_format = bridge_state->input_bus_cfg.format; |
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if (bus_format == MEDIA_BUS_FMT_FIXED) { |
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dev_warn_once(drm->dev, |
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"Bridge does not provide bus format, assuming MEDIA_BUS_FMT_RGB888_1X24.\n" |
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"Please fix bridge driver by handling atomic_get_input_bus_fmts.\n"); |
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bus_format = MEDIA_BUS_FMT_RGB888_1X24; |
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} |
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} |
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/* If there is no bridge, use bus format from connector */ |
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if (!bus_format && mxsfb->connector->display_info.num_bus_formats) |
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bus_format = mxsfb->connector->display_info.bus_formats[0]; |
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/* If all else fails, default to RGB888_1X24 */ |
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if (!bus_format) |
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bus_format = MEDIA_BUS_FMT_RGB888_1X24; |
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mxsfb_crtc_mode_set_nofb(mxsfb, bus_format); |
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/* Write cur_buf as well to avoid an initial corrupt frame */ |
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paddr = mxsfb_get_fb_paddr(crtc->primary); |
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if (paddr) { |
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writel(paddr, mxsfb->base + mxsfb->devdata->cur_buf); |
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writel(paddr, mxsfb->base + mxsfb->devdata->next_buf); |
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} |
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mxsfb_enable_controller(mxsfb); |
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} |
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static void mxsfb_crtc_atomic_disable(struct drm_crtc *crtc, |
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struct drm_atomic_state *state) |
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{ |
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struct mxsfb_drm_private *mxsfb = to_mxsfb_drm_private(crtc->dev); |
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struct drm_device *drm = mxsfb->drm; |
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struct drm_pending_vblank_event *event; |
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mxsfb_disable_controller(mxsfb); |
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spin_lock_irq(&drm->event_lock); |
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event = crtc->state->event; |
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if (event) { |
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crtc->state->event = NULL; |
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drm_crtc_send_vblank_event(crtc, event); |
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} |
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spin_unlock_irq(&drm->event_lock); |
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drm_crtc_vblank_off(crtc); |
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mxsfb_disable_axi_clk(mxsfb); |
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pm_runtime_put_sync(drm->dev); |
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} |
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static int mxsfb_crtc_enable_vblank(struct drm_crtc *crtc) |
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{ |
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struct mxsfb_drm_private *mxsfb = to_mxsfb_drm_private(crtc->dev); |
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/* Clear and enable VBLANK IRQ */ |
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writel(CTRL1_CUR_FRAME_DONE_IRQ, mxsfb->base + LCDC_CTRL1 + REG_CLR); |
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writel(CTRL1_CUR_FRAME_DONE_IRQ_EN, mxsfb->base + LCDC_CTRL1 + REG_SET); |
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return 0; |
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} |
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static void mxsfb_crtc_disable_vblank(struct drm_crtc *crtc) |
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{ |
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struct mxsfb_drm_private *mxsfb = to_mxsfb_drm_private(crtc->dev); |
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/* Disable and clear VBLANK IRQ */ |
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writel(CTRL1_CUR_FRAME_DONE_IRQ_EN, mxsfb->base + LCDC_CTRL1 + REG_CLR); |
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writel(CTRL1_CUR_FRAME_DONE_IRQ, mxsfb->base + LCDC_CTRL1 + REG_CLR); |
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} |
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static const struct drm_crtc_helper_funcs mxsfb_crtc_helper_funcs = { |
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.atomic_check = mxsfb_crtc_atomic_check, |
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.atomic_flush = mxsfb_crtc_atomic_flush, |
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.atomic_enable = mxsfb_crtc_atomic_enable, |
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.atomic_disable = mxsfb_crtc_atomic_disable, |
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}; |
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static const struct drm_crtc_funcs mxsfb_crtc_funcs = { |
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.reset = drm_atomic_helper_crtc_reset, |
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.destroy = drm_crtc_cleanup, |
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.set_config = drm_atomic_helper_set_config, |
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.page_flip = drm_atomic_helper_page_flip, |
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.atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state, |
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.atomic_destroy_state = drm_atomic_helper_crtc_destroy_state, |
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.enable_vblank = mxsfb_crtc_enable_vblank, |
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.disable_vblank = mxsfb_crtc_disable_vblank, |
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}; |
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|
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/* ----------------------------------------------------------------------------- |
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* Encoder |
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*/ |
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static const struct drm_encoder_funcs mxsfb_encoder_funcs = { |
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.destroy = drm_encoder_cleanup, |
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}; |
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/* ----------------------------------------------------------------------------- |
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* Planes |
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*/ |
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static int mxsfb_plane_atomic_check(struct drm_plane *plane, |
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struct drm_atomic_state *state) |
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{ |
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struct drm_plane_state *plane_state = drm_atomic_get_new_plane_state(state, |
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plane); |
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struct mxsfb_drm_private *mxsfb = to_mxsfb_drm_private(plane->dev); |
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struct drm_crtc_state *crtc_state; |
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crtc_state = drm_atomic_get_new_crtc_state(state, |
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&mxsfb->crtc); |
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return drm_atomic_helper_check_plane_state(plane_state, crtc_state, |
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DRM_PLANE_HELPER_NO_SCALING, |
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DRM_PLANE_HELPER_NO_SCALING, |
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false, true); |
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} |
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|
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static void mxsfb_plane_primary_atomic_update(struct drm_plane *plane, |
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struct drm_atomic_state *state) |
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{ |
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struct mxsfb_drm_private *mxsfb = to_mxsfb_drm_private(plane->dev); |
|
dma_addr_t paddr; |
|
|
|
paddr = mxsfb_get_fb_paddr(plane); |
|
if (paddr) |
|
writel(paddr, mxsfb->base + mxsfb->devdata->next_buf); |
|
} |
|
|
|
static void mxsfb_plane_overlay_atomic_update(struct drm_plane *plane, |
|
struct drm_atomic_state *state) |
|
{ |
|
struct drm_plane_state *old_pstate = drm_atomic_get_old_plane_state(state, |
|
plane); |
|
struct mxsfb_drm_private *mxsfb = to_mxsfb_drm_private(plane->dev); |
|
struct drm_plane_state *new_pstate = drm_atomic_get_new_plane_state(state, |
|
plane); |
|
dma_addr_t paddr; |
|
u32 ctrl; |
|
|
|
paddr = mxsfb_get_fb_paddr(plane); |
|
if (!paddr) { |
|
writel(0, mxsfb->base + LCDC_AS_CTRL); |
|
return; |
|
} |
|
|
|
/* |
|
* HACK: The hardware seems to output 64 bytes of data of unknown |
|
* origin, and then to proceed with the framebuffer. Until the reason |
|
* is understood, live with the 16 initial invalid pixels on the first |
|
* line and start 64 bytes within the framebuffer. |
|
*/ |
|
paddr += 64; |
|
|
|
writel(paddr, mxsfb->base + LCDC_AS_NEXT_BUF); |
|
|
|
/* |
|
* If the plane was previously disabled, write LCDC_AS_BUF as well to |
|
* provide the first buffer. |
|
*/ |
|
if (!old_pstate->fb) |
|
writel(paddr, mxsfb->base + LCDC_AS_BUF); |
|
|
|
ctrl = AS_CTRL_AS_ENABLE | AS_CTRL_ALPHA(255); |
|
|
|
switch (new_pstate->fb->format->format) { |
|
case DRM_FORMAT_XRGB4444: |
|
ctrl |= AS_CTRL_FORMAT_RGB444 | AS_CTRL_ALPHA_CTRL_OVERRIDE; |
|
break; |
|
case DRM_FORMAT_ARGB4444: |
|
ctrl |= AS_CTRL_FORMAT_ARGB4444 | AS_CTRL_ALPHA_CTRL_EMBEDDED; |
|
break; |
|
case DRM_FORMAT_XRGB1555: |
|
ctrl |= AS_CTRL_FORMAT_RGB555 | AS_CTRL_ALPHA_CTRL_OVERRIDE; |
|
break; |
|
case DRM_FORMAT_ARGB1555: |
|
ctrl |= AS_CTRL_FORMAT_ARGB1555 | AS_CTRL_ALPHA_CTRL_EMBEDDED; |
|
break; |
|
case DRM_FORMAT_RGB565: |
|
ctrl |= AS_CTRL_FORMAT_RGB565 | AS_CTRL_ALPHA_CTRL_OVERRIDE; |
|
break; |
|
case DRM_FORMAT_XRGB8888: |
|
ctrl |= AS_CTRL_FORMAT_RGB888 | AS_CTRL_ALPHA_CTRL_OVERRIDE; |
|
break; |
|
case DRM_FORMAT_ARGB8888: |
|
ctrl |= AS_CTRL_FORMAT_ARGB8888 | AS_CTRL_ALPHA_CTRL_EMBEDDED; |
|
break; |
|
} |
|
|
|
writel(ctrl, mxsfb->base + LCDC_AS_CTRL); |
|
} |
|
|
|
static bool mxsfb_format_mod_supported(struct drm_plane *plane, |
|
uint32_t format, |
|
uint64_t modifier) |
|
{ |
|
return modifier == DRM_FORMAT_MOD_LINEAR; |
|
} |
|
|
|
static const struct drm_plane_helper_funcs mxsfb_plane_primary_helper_funcs = { |
|
.atomic_check = mxsfb_plane_atomic_check, |
|
.atomic_update = mxsfb_plane_primary_atomic_update, |
|
}; |
|
|
|
static const struct drm_plane_helper_funcs mxsfb_plane_overlay_helper_funcs = { |
|
.atomic_check = mxsfb_plane_atomic_check, |
|
.atomic_update = mxsfb_plane_overlay_atomic_update, |
|
}; |
|
|
|
static const struct drm_plane_funcs mxsfb_plane_funcs = { |
|
.format_mod_supported = mxsfb_format_mod_supported, |
|
.update_plane = drm_atomic_helper_update_plane, |
|
.disable_plane = drm_atomic_helper_disable_plane, |
|
.destroy = drm_plane_cleanup, |
|
.reset = drm_atomic_helper_plane_reset, |
|
.atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state, |
|
.atomic_destroy_state = drm_atomic_helper_plane_destroy_state, |
|
}; |
|
|
|
static const uint32_t mxsfb_primary_plane_formats[] = { |
|
DRM_FORMAT_RGB565, |
|
DRM_FORMAT_XRGB8888, |
|
}; |
|
|
|
static const uint32_t mxsfb_overlay_plane_formats[] = { |
|
DRM_FORMAT_XRGB4444, |
|
DRM_FORMAT_ARGB4444, |
|
DRM_FORMAT_XRGB1555, |
|
DRM_FORMAT_ARGB1555, |
|
DRM_FORMAT_RGB565, |
|
DRM_FORMAT_XRGB8888, |
|
DRM_FORMAT_ARGB8888, |
|
}; |
|
|
|
static const uint64_t mxsfb_modifiers[] = { |
|
DRM_FORMAT_MOD_LINEAR, |
|
DRM_FORMAT_MOD_INVALID |
|
}; |
|
|
|
/* ----------------------------------------------------------------------------- |
|
* Initialization |
|
*/ |
|
|
|
int mxsfb_kms_init(struct mxsfb_drm_private *mxsfb) |
|
{ |
|
struct drm_encoder *encoder = &mxsfb->encoder; |
|
struct drm_crtc *crtc = &mxsfb->crtc; |
|
int ret; |
|
|
|
drm_plane_helper_add(&mxsfb->planes.primary, |
|
&mxsfb_plane_primary_helper_funcs); |
|
ret = drm_universal_plane_init(mxsfb->drm, &mxsfb->planes.primary, 1, |
|
&mxsfb_plane_funcs, |
|
mxsfb_primary_plane_formats, |
|
ARRAY_SIZE(mxsfb_primary_plane_formats), |
|
mxsfb_modifiers, DRM_PLANE_TYPE_PRIMARY, |
|
NULL); |
|
if (ret) |
|
return ret; |
|
|
|
if (mxsfb->devdata->has_overlay) { |
|
drm_plane_helper_add(&mxsfb->planes.overlay, |
|
&mxsfb_plane_overlay_helper_funcs); |
|
ret = drm_universal_plane_init(mxsfb->drm, |
|
&mxsfb->planes.overlay, 1, |
|
&mxsfb_plane_funcs, |
|
mxsfb_overlay_plane_formats, |
|
ARRAY_SIZE(mxsfb_overlay_plane_formats), |
|
mxsfb_modifiers, DRM_PLANE_TYPE_OVERLAY, |
|
NULL); |
|
if (ret) |
|
return ret; |
|
} |
|
|
|
drm_crtc_helper_add(crtc, &mxsfb_crtc_helper_funcs); |
|
ret = drm_crtc_init_with_planes(mxsfb->drm, crtc, |
|
&mxsfb->planes.primary, NULL, |
|
&mxsfb_crtc_funcs, NULL); |
|
if (ret) |
|
return ret; |
|
|
|
encoder->possible_crtcs = drm_crtc_mask(crtc); |
|
return drm_encoder_init(mxsfb->drm, encoder, &mxsfb_encoder_funcs, |
|
DRM_MODE_ENCODER_NONE, NULL); |
|
}
|
|
|