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609 lines
17 KiB
609 lines
17 KiB
/* SPDX-License-Identifier: GPL-2.0-only */ |
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/* |
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* Copyright (C) 2013 Red Hat |
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* Author: Rob Clark <[email protected]> |
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*/ |
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#ifndef __MSM_GPU_H__ |
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#define __MSM_GPU_H__ |
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#include <linux/adreno-smmu-priv.h> |
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#include <linux/clk.h> |
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#include <linux/interconnect.h> |
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#include <linux/pm_opp.h> |
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#include <linux/regulator/consumer.h> |
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#include "msm_drv.h" |
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#include "msm_fence.h" |
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#include "msm_ringbuffer.h" |
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#include "msm_gem.h" |
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struct msm_gem_submit; |
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struct msm_gpu_perfcntr; |
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struct msm_gpu_state; |
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struct msm_gpu_config { |
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const char *ioname; |
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unsigned int nr_rings; |
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}; |
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/* So far, with hardware that I've seen to date, we can have: |
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* + zero, one, or two z180 2d cores |
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* + a3xx or a2xx 3d core, which share a common CP (the firmware |
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* for the CP seems to implement some different PM4 packet types |
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* but the basics of cmdstream submission are the same) |
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* |
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* Which means that the eventual complete "class" hierarchy, once |
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* support for all past and present hw is in place, becomes: |
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* + msm_gpu |
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* + adreno_gpu |
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* + a3xx_gpu |
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* + a2xx_gpu |
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* + z180_gpu |
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*/ |
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struct msm_gpu_funcs { |
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int (*get_param)(struct msm_gpu *gpu, uint32_t param, uint64_t *value); |
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int (*hw_init)(struct msm_gpu *gpu); |
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int (*pm_suspend)(struct msm_gpu *gpu); |
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int (*pm_resume)(struct msm_gpu *gpu); |
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void (*submit)(struct msm_gpu *gpu, struct msm_gem_submit *submit); |
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void (*flush)(struct msm_gpu *gpu, struct msm_ringbuffer *ring); |
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irqreturn_t (*irq)(struct msm_gpu *irq); |
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struct msm_ringbuffer *(*active_ring)(struct msm_gpu *gpu); |
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void (*recover)(struct msm_gpu *gpu); |
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void (*destroy)(struct msm_gpu *gpu); |
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#if defined(CONFIG_DEBUG_FS) || defined(CONFIG_DEV_COREDUMP) |
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/* show GPU status in debugfs: */ |
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void (*show)(struct msm_gpu *gpu, struct msm_gpu_state *state, |
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struct drm_printer *p); |
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/* for generation specific debugfs: */ |
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void (*debugfs_init)(struct msm_gpu *gpu, struct drm_minor *minor); |
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#endif |
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unsigned long (*gpu_busy)(struct msm_gpu *gpu); |
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struct msm_gpu_state *(*gpu_state_get)(struct msm_gpu *gpu); |
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int (*gpu_state_put)(struct msm_gpu_state *state); |
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unsigned long (*gpu_get_freq)(struct msm_gpu *gpu); |
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void (*gpu_set_freq)(struct msm_gpu *gpu, struct dev_pm_opp *opp); |
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struct msm_gem_address_space *(*create_address_space) |
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(struct msm_gpu *gpu, struct platform_device *pdev); |
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struct msm_gem_address_space *(*create_private_address_space) |
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(struct msm_gpu *gpu); |
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uint32_t (*get_rptr)(struct msm_gpu *gpu, struct msm_ringbuffer *ring); |
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}; |
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/* Additional state for iommu faults: */ |
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struct msm_gpu_fault_info { |
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u64 ttbr0; |
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unsigned long iova; |
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int flags; |
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const char *type; |
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const char *block; |
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}; |
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/** |
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* struct msm_gpu_devfreq - devfreq related state |
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*/ |
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struct msm_gpu_devfreq { |
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/** devfreq: devfreq instance */ |
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struct devfreq *devfreq; |
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/** |
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* idle_constraint: |
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* |
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* A PM QoS constraint to limit max freq while the GPU is idle. |
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*/ |
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struct dev_pm_qos_request idle_freq; |
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/** |
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* boost_constraint: |
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* |
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* A PM QoS constraint to boost min freq for a period of time |
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* until the boost expires. |
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*/ |
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struct dev_pm_qos_request boost_freq; |
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/** |
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* busy_cycles: |
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* |
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* Used by implementation of gpu->gpu_busy() to track the last |
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* busy counter value, for calculating elapsed busy cycles since |
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* last sampling period. |
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*/ |
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u64 busy_cycles; |
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/** time: Time of last sampling period. */ |
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ktime_t time; |
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/** idle_time: Time of last transition to idle: */ |
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ktime_t idle_time; |
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/** |
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* idle_work: |
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* |
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* Used to delay clamping to idle freq on active->idle transition. |
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*/ |
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struct msm_hrtimer_work idle_work; |
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/** |
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* boost_work: |
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* |
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* Used to reset the boost_constraint after the boost period has |
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* elapsed |
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*/ |
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struct msm_hrtimer_work boost_work; |
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}; |
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struct msm_gpu { |
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const char *name; |
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struct drm_device *dev; |
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struct platform_device *pdev; |
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const struct msm_gpu_funcs *funcs; |
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struct adreno_smmu_priv adreno_smmu; |
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/* performance counters (hw & sw): */ |
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spinlock_t perf_lock; |
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bool perfcntr_active; |
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struct { |
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bool active; |
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ktime_t time; |
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} last_sample; |
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uint32_t totaltime, activetime; /* sw counters */ |
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uint32_t last_cntrs[5]; /* hw counters */ |
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const struct msm_gpu_perfcntr *perfcntrs; |
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uint32_t num_perfcntrs; |
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struct msm_ringbuffer *rb[MSM_GPU_MAX_RINGS]; |
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int nr_rings; |
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/** |
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* cur_ctx_seqno: |
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* |
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* The ctx->seqno value of the last context to submit rendering, |
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* and the one with current pgtables installed (for generations |
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* that support per-context pgtables). Tracked by seqno rather |
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* than pointer value to avoid dangling pointers, and cases where |
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* a ctx can be freed and a new one created with the same address. |
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*/ |
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int cur_ctx_seqno; |
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/* |
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* List of GEM active objects on this gpu. Protected by |
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* msm_drm_private::mm_lock |
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*/ |
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struct list_head active_list; |
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/** |
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* lock: |
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* |
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* General lock for serializing all the gpu things. |
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* |
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* TODO move to per-ring locking where feasible (ie. submit/retire |
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* path, etc) |
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*/ |
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struct mutex lock; |
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/** |
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* active_submits: |
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* |
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* The number of submitted but not yet retired submits, used to |
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* determine transitions between active and idle. |
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* |
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* Protected by active_lock |
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*/ |
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int active_submits; |
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/** lock: protects active_submits and idle/active transitions */ |
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struct mutex active_lock; |
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/* does gpu need hw_init? */ |
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bool needs_hw_init; |
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/* number of GPU hangs (for all contexts) */ |
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int global_faults; |
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void __iomem *mmio; |
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int irq; |
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struct msm_gem_address_space *aspace; |
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/* Power Control: */ |
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struct regulator *gpu_reg, *gpu_cx; |
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struct clk_bulk_data *grp_clks; |
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int nr_clocks; |
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struct clk *ebi1_clk, *core_clk, *rbbmtimer_clk; |
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uint32_t fast_rate; |
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/* Hang and Inactivity Detection: |
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*/ |
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#define DRM_MSM_INACTIVE_PERIOD 66 /* in ms (roughly four frames) */ |
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#define DRM_MSM_HANGCHECK_DEFAULT_PERIOD 500 /* in ms */ |
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struct timer_list hangcheck_timer; |
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/* Fault info for most recent iova fault: */ |
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struct msm_gpu_fault_info fault_info; |
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/* work for handling GPU ioval faults: */ |
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struct kthread_work fault_work; |
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/* work for handling GPU recovery: */ |
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struct kthread_work recover_work; |
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/** retire_event: notified when submits are retired: */ |
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wait_queue_head_t retire_event; |
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/* work for handling active-list retiring: */ |
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struct kthread_work retire_work; |
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/* worker for retire/recover: */ |
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struct kthread_worker *worker; |
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struct drm_gem_object *memptrs_bo; |
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struct msm_gpu_devfreq devfreq; |
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uint32_t suspend_count; |
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struct msm_gpu_state *crashstate; |
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/* Enable clamping to idle freq when inactive: */ |
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bool clamp_to_idle; |
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/* True if the hardware supports expanded apriv (a650 and newer) */ |
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bool hw_apriv; |
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struct thermal_cooling_device *cooling; |
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}; |
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static inline struct msm_gpu *dev_to_gpu(struct device *dev) |
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{ |
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struct adreno_smmu_priv *adreno_smmu = dev_get_drvdata(dev); |
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return container_of(adreno_smmu, struct msm_gpu, adreno_smmu); |
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} |
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/* It turns out that all targets use the same ringbuffer size */ |
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#define MSM_GPU_RINGBUFFER_SZ SZ_32K |
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#define MSM_GPU_RINGBUFFER_BLKSIZE 32 |
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#define MSM_GPU_RB_CNTL_DEFAULT \ |
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(AXXX_CP_RB_CNTL_BUFSZ(ilog2(MSM_GPU_RINGBUFFER_SZ / 8)) | \ |
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AXXX_CP_RB_CNTL_BLKSZ(ilog2(MSM_GPU_RINGBUFFER_BLKSIZE / 8))) |
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static inline bool msm_gpu_active(struct msm_gpu *gpu) |
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{ |
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int i; |
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for (i = 0; i < gpu->nr_rings; i++) { |
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struct msm_ringbuffer *ring = gpu->rb[i]; |
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if (fence_after(ring->seqno, ring->memptrs->fence)) |
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return true; |
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} |
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return false; |
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} |
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/* Perf-Counters: |
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* The select_reg and select_val are just there for the benefit of the child |
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* class that actually enables the perf counter.. but msm_gpu base class |
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* will handle sampling/displaying the counters. |
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*/ |
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struct msm_gpu_perfcntr { |
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uint32_t select_reg; |
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uint32_t sample_reg; |
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uint32_t select_val; |
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const char *name; |
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}; |
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/* |
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* The number of priority levels provided by drm gpu scheduler. The |
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* DRM_SCHED_PRIORITY_KERNEL priority level is treated specially in some |
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* cases, so we don't use it (no need for kernel generated jobs). |
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*/ |
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#define NR_SCHED_PRIORITIES (1 + DRM_SCHED_PRIORITY_HIGH - DRM_SCHED_PRIORITY_MIN) |
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/** |
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* struct msm_file_private - per-drm_file context |
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* |
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* @queuelock: synchronizes access to submitqueues list |
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* @submitqueues: list of &msm_gpu_submitqueue created by userspace |
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* @queueid: counter incremented each time a submitqueue is created, |
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* used to assign &msm_gpu_submitqueue.id |
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* @aspace: the per-process GPU address-space |
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* @ref: reference count |
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* @seqno: unique per process seqno |
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*/ |
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struct msm_file_private { |
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rwlock_t queuelock; |
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struct list_head submitqueues; |
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int queueid; |
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struct msm_gem_address_space *aspace; |
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struct kref ref; |
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int seqno; |
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/** |
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* entities: |
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* |
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* Table of per-priority-level sched entities used by submitqueues |
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* associated with this &drm_file. Because some userspace apps |
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* make assumptions about rendering from multiple gl contexts |
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* (of the same priority) within the process happening in FIFO |
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* order without requiring any fencing beyond MakeCurrent(), we |
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* create at most one &drm_sched_entity per-process per-priority- |
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* level. |
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*/ |
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struct drm_sched_entity *entities[NR_SCHED_PRIORITIES * MSM_GPU_MAX_RINGS]; |
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}; |
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/** |
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* msm_gpu_convert_priority - Map userspace priority to ring # and sched priority |
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* |
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* @gpu: the gpu instance |
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* @prio: the userspace priority level |
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* @ring_nr: [out] the ringbuffer the userspace priority maps to |
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* @sched_prio: [out] the gpu scheduler priority level which the userspace |
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* priority maps to |
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* |
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* With drm/scheduler providing it's own level of prioritization, our total |
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* number of available priority levels is (nr_rings * NR_SCHED_PRIORITIES). |
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* Each ring is associated with it's own scheduler instance. However, our |
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* UABI is that lower numerical values are higher priority. So mapping the |
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* single userspace priority level into ring_nr and sched_prio takes some |
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* care. The userspace provided priority (when a submitqueue is created) |
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* is mapped to ring nr and scheduler priority as such: |
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* |
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* ring_nr = userspace_prio / NR_SCHED_PRIORITIES |
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* sched_prio = NR_SCHED_PRIORITIES - |
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* (userspace_prio % NR_SCHED_PRIORITIES) - 1 |
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* |
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* This allows generations without preemption (nr_rings==1) to have some |
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* amount of prioritization, and provides more priority levels for gens |
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* that do have preemption. |
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*/ |
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static inline int msm_gpu_convert_priority(struct msm_gpu *gpu, int prio, |
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unsigned *ring_nr, enum drm_sched_priority *sched_prio) |
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{ |
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unsigned rn, sp; |
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rn = div_u64_rem(prio, NR_SCHED_PRIORITIES, &sp); |
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/* invert sched priority to map to higher-numeric-is-higher- |
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* priority convention |
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*/ |
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sp = NR_SCHED_PRIORITIES - sp - 1; |
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if (rn >= gpu->nr_rings) |
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return -EINVAL; |
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*ring_nr = rn; |
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*sched_prio = sp; |
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return 0; |
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} |
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/** |
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* struct msm_gpu_submitqueues - Userspace created context. |
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* |
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* A submitqueue is associated with a gl context or vk queue (or equiv) |
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* in userspace. |
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* |
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* @id: userspace id for the submitqueue, unique within the drm_file |
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* @flags: userspace flags for the submitqueue, specified at creation |
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* (currently unusued) |
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* @ring_nr: the ringbuffer used by this submitqueue, which is determined |
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* by the submitqueue's priority |
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* @faults: the number of GPU hangs associated with this submitqueue |
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* @last_fence: the sequence number of the last allocated fence (for error |
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* checking) |
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* @ctx: the per-drm_file context associated with the submitqueue (ie. |
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* which set of pgtables do submits jobs associated with the |
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* submitqueue use) |
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* @node: node in the context's list of submitqueues |
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* @fence_idr: maps fence-id to dma_fence for userspace visible fence |
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* seqno, protected by submitqueue lock |
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* @lock: submitqueue lock |
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* @ref: reference count |
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* @entity: the submit job-queue |
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*/ |
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struct msm_gpu_submitqueue { |
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int id; |
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u32 flags; |
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u32 ring_nr; |
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int faults; |
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uint32_t last_fence; |
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struct msm_file_private *ctx; |
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struct list_head node; |
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struct idr fence_idr; |
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struct mutex lock; |
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struct kref ref; |
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struct drm_sched_entity *entity; |
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}; |
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struct msm_gpu_state_bo { |
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u64 iova; |
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size_t size; |
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void *data; |
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bool encoded; |
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}; |
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struct msm_gpu_state { |
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struct kref ref; |
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struct timespec64 time; |
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struct { |
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u64 iova; |
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u32 fence; |
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u32 seqno; |
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u32 rptr; |
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u32 wptr; |
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void *data; |
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int data_size; |
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bool encoded; |
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} ring[MSM_GPU_MAX_RINGS]; |
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int nr_registers; |
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u32 *registers; |
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u32 rbbm_status; |
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char *comm; |
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char *cmd; |
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struct msm_gpu_fault_info fault_info; |
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int nr_bos; |
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struct msm_gpu_state_bo *bos; |
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}; |
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static inline void gpu_write(struct msm_gpu *gpu, u32 reg, u32 data) |
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{ |
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msm_writel(data, gpu->mmio + (reg << 2)); |
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} |
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static inline u32 gpu_read(struct msm_gpu *gpu, u32 reg) |
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{ |
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return msm_readl(gpu->mmio + (reg << 2)); |
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} |
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static inline void gpu_rmw(struct msm_gpu *gpu, u32 reg, u32 mask, u32 or) |
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{ |
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msm_rmw(gpu->mmio + (reg << 2), mask, or); |
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} |
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static inline u64 gpu_read64(struct msm_gpu *gpu, u32 lo, u32 hi) |
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{ |
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u64 val; |
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/* |
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* Why not a readq here? Two reasons: 1) many of the LO registers are |
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* not quad word aligned and 2) the GPU hardware designers have a bit |
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* of a history of putting registers where they fit, especially in |
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* spins. The longer a GPU family goes the higher the chance that |
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* we'll get burned. We could do a series of validity checks if we |
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* wanted to, but really is a readq() that much better? Nah. |
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*/ |
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/* |
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* For some lo/hi registers (like perfcounters), the hi value is latched |
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* when the lo is read, so make sure to read the lo first to trigger |
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* that |
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*/ |
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val = (u64) msm_readl(gpu->mmio + (lo << 2)); |
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val |= ((u64) msm_readl(gpu->mmio + (hi << 2)) << 32); |
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return val; |
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} |
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static inline void gpu_write64(struct msm_gpu *gpu, u32 lo, u32 hi, u64 val) |
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{ |
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/* Why not a writeq here? Read the screed above */ |
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msm_writel(lower_32_bits(val), gpu->mmio + (lo << 2)); |
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msm_writel(upper_32_bits(val), gpu->mmio + (hi << 2)); |
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} |
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int msm_gpu_pm_suspend(struct msm_gpu *gpu); |
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int msm_gpu_pm_resume(struct msm_gpu *gpu); |
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int msm_submitqueue_init(struct drm_device *drm, struct msm_file_private *ctx); |
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struct msm_gpu_submitqueue *msm_submitqueue_get(struct msm_file_private *ctx, |
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u32 id); |
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int msm_submitqueue_create(struct drm_device *drm, |
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struct msm_file_private *ctx, |
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u32 prio, u32 flags, u32 *id); |
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int msm_submitqueue_query(struct drm_device *drm, struct msm_file_private *ctx, |
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struct drm_msm_submitqueue_query *args); |
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int msm_submitqueue_remove(struct msm_file_private *ctx, u32 id); |
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void msm_submitqueue_close(struct msm_file_private *ctx); |
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void msm_submitqueue_destroy(struct kref *kref); |
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void __msm_file_private_destroy(struct kref *kref); |
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static inline void msm_file_private_put(struct msm_file_private *ctx) |
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{ |
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kref_put(&ctx->ref, __msm_file_private_destroy); |
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} |
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static inline struct msm_file_private *msm_file_private_get( |
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struct msm_file_private *ctx) |
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{ |
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kref_get(&ctx->ref); |
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return ctx; |
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} |
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void msm_devfreq_init(struct msm_gpu *gpu); |
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void msm_devfreq_cleanup(struct msm_gpu *gpu); |
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void msm_devfreq_resume(struct msm_gpu *gpu); |
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void msm_devfreq_suspend(struct msm_gpu *gpu); |
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void msm_devfreq_boost(struct msm_gpu *gpu, unsigned factor); |
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void msm_devfreq_active(struct msm_gpu *gpu); |
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void msm_devfreq_idle(struct msm_gpu *gpu); |
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int msm_gpu_hw_init(struct msm_gpu *gpu); |
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void msm_gpu_perfcntr_start(struct msm_gpu *gpu); |
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void msm_gpu_perfcntr_stop(struct msm_gpu *gpu); |
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int msm_gpu_perfcntr_sample(struct msm_gpu *gpu, uint32_t *activetime, |
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uint32_t *totaltime, uint32_t ncntrs, uint32_t *cntrs); |
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void msm_gpu_retire(struct msm_gpu *gpu); |
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void msm_gpu_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit); |
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int msm_gpu_init(struct drm_device *drm, struct platform_device *pdev, |
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struct msm_gpu *gpu, const struct msm_gpu_funcs *funcs, |
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const char *name, struct msm_gpu_config *config); |
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struct msm_gem_address_space * |
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msm_gpu_create_private_address_space(struct msm_gpu *gpu, struct task_struct *task); |
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void msm_gpu_cleanup(struct msm_gpu *gpu); |
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struct msm_gpu *adreno_load_gpu(struct drm_device *dev); |
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void __init adreno_register(void); |
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void __exit adreno_unregister(void); |
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static inline void msm_submitqueue_put(struct msm_gpu_submitqueue *queue) |
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{ |
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if (queue) |
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kref_put(&queue->ref, msm_submitqueue_destroy); |
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} |
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static inline struct msm_gpu_state *msm_gpu_crashstate_get(struct msm_gpu *gpu) |
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{ |
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struct msm_gpu_state *state = NULL; |
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|
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mutex_lock(&gpu->lock); |
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|
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if (gpu->crashstate) { |
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kref_get(&gpu->crashstate->ref); |
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state = gpu->crashstate; |
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} |
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mutex_unlock(&gpu->lock); |
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return state; |
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} |
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static inline void msm_gpu_crashstate_put(struct msm_gpu *gpu) |
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{ |
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mutex_lock(&gpu->lock); |
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|
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if (gpu->crashstate) { |
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if (gpu->funcs->gpu_state_put(gpu->crashstate)) |
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gpu->crashstate = NULL; |
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} |
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|
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mutex_unlock(&gpu->lock); |
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} |
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|
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/* |
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* Simple macro to semi-cleanly add the MAP_PRIV flag for targets that can |
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* support expanded privileges |
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*/ |
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#define check_apriv(gpu, flags) \ |
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(((gpu)->hw_apriv ? MSM_BO_MAP_PRIV : 0) | (flags)) |
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#endif /* __MSM_GPU_H__ */
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