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249 lines
6.4 KiB
249 lines
6.4 KiB
/* |
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* Copyright (c) 2015 NVIDIA Corporation. All rights reserved. |
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* |
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* Permission is hereby granted, free of charge, to any person obtaining a |
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* copy of this software and associated documentation files (the "Software"), |
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* to deal in the Software without restriction, including without limitation |
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* the rights to use, copy, modify, merge, publish, distribute, sub license, |
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* and/or sell copies of the Software, and to permit persons to whom the |
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* Software is furnished to do so, subject to the following conditions: |
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* |
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* The above copyright notice and this permission notice (including the |
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* next paragraph) shall be included in all copies or substantial portions |
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* of the Software. |
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* |
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL |
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER |
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* DEALINGS IN THE SOFTWARE. |
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*/ |
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#include <linux/slab.h> |
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#include <linux/delay.h> |
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#include <drm/drm_print.h> |
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#include <drm/drm_scdc_helper.h> |
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/** |
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* DOC: scdc helpers |
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* |
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* Status and Control Data Channel (SCDC) is a mechanism introduced by the |
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* HDMI 2.0 specification. It is a point-to-point protocol that allows the |
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* HDMI source and HDMI sink to exchange data. The same I2C interface that |
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* is used to access EDID serves as the transport mechanism for SCDC. |
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*/ |
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#define SCDC_I2C_SLAVE_ADDRESS 0x54 |
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/** |
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* drm_scdc_read - read a block of data from SCDC |
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* @adapter: I2C controller |
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* @offset: start offset of block to read |
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* @buffer: return location for the block to read |
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* @size: size of the block to read |
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* |
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* Reads a block of data from SCDC, starting at a given offset. |
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* |
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* Returns: |
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* 0 on success, negative error code on failure. |
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*/ |
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ssize_t drm_scdc_read(struct i2c_adapter *adapter, u8 offset, void *buffer, |
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size_t size) |
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{ |
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int ret; |
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struct i2c_msg msgs[2] = { |
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{ |
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.addr = SCDC_I2C_SLAVE_ADDRESS, |
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.flags = 0, |
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.len = 1, |
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.buf = &offset, |
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}, { |
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.addr = SCDC_I2C_SLAVE_ADDRESS, |
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.flags = I2C_M_RD, |
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.len = size, |
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.buf = buffer, |
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} |
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}; |
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ret = i2c_transfer(adapter, msgs, ARRAY_SIZE(msgs)); |
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if (ret < 0) |
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return ret; |
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if (ret != ARRAY_SIZE(msgs)) |
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return -EPROTO; |
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return 0; |
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} |
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EXPORT_SYMBOL(drm_scdc_read); |
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/** |
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* drm_scdc_write - write a block of data to SCDC |
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* @adapter: I2C controller |
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* @offset: start offset of block to write |
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* @buffer: block of data to write |
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* @size: size of the block to write |
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* |
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* Writes a block of data to SCDC, starting at a given offset. |
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* |
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* Returns: |
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* 0 on success, negative error code on failure. |
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*/ |
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ssize_t drm_scdc_write(struct i2c_adapter *adapter, u8 offset, |
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const void *buffer, size_t size) |
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{ |
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struct i2c_msg msg = { |
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.addr = SCDC_I2C_SLAVE_ADDRESS, |
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.flags = 0, |
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.len = 1 + size, |
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.buf = NULL, |
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}; |
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void *data; |
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int err; |
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data = kmalloc(1 + size, GFP_KERNEL); |
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if (!data) |
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return -ENOMEM; |
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msg.buf = data; |
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memcpy(data, &offset, sizeof(offset)); |
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memcpy(data + 1, buffer, size); |
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err = i2c_transfer(adapter, &msg, 1); |
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kfree(data); |
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if (err < 0) |
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return err; |
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if (err != 1) |
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return -EPROTO; |
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return 0; |
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} |
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EXPORT_SYMBOL(drm_scdc_write); |
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/** |
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* drm_scdc_get_scrambling_status - what is status of scrambling? |
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* @adapter: I2C adapter for DDC channel |
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* |
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* Reads the scrambler status over SCDC, and checks the |
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* scrambling status. |
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* |
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* Returns: |
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* True if the scrambling is enabled, false otherwise. |
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*/ |
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bool drm_scdc_get_scrambling_status(struct i2c_adapter *adapter) |
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{ |
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u8 status; |
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int ret; |
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ret = drm_scdc_readb(adapter, SCDC_SCRAMBLER_STATUS, &status); |
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if (ret < 0) { |
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DRM_DEBUG_KMS("Failed to read scrambling status: %d\n", ret); |
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return false; |
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} |
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return status & SCDC_SCRAMBLING_STATUS; |
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} |
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EXPORT_SYMBOL(drm_scdc_get_scrambling_status); |
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/** |
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* drm_scdc_set_scrambling - enable scrambling |
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* @adapter: I2C adapter for DDC channel |
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* @enable: bool to indicate if scrambling is to be enabled/disabled |
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* |
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* Writes the TMDS config register over SCDC channel, and: |
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* enables scrambling when enable = 1 |
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* disables scrambling when enable = 0 |
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* |
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* Returns: |
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* True if scrambling is set/reset successfully, false otherwise. |
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*/ |
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bool drm_scdc_set_scrambling(struct i2c_adapter *adapter, bool enable) |
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{ |
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u8 config; |
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int ret; |
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ret = drm_scdc_readb(adapter, SCDC_TMDS_CONFIG, &config); |
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if (ret < 0) { |
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DRM_DEBUG_KMS("Failed to read TMDS config: %d\n", ret); |
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return false; |
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} |
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if (enable) |
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config |= SCDC_SCRAMBLING_ENABLE; |
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else |
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config &= ~SCDC_SCRAMBLING_ENABLE; |
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ret = drm_scdc_writeb(adapter, SCDC_TMDS_CONFIG, config); |
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if (ret < 0) { |
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DRM_DEBUG_KMS("Failed to enable scrambling: %d\n", ret); |
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return false; |
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} |
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return true; |
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} |
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EXPORT_SYMBOL(drm_scdc_set_scrambling); |
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/** |
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* drm_scdc_set_high_tmds_clock_ratio - set TMDS clock ratio |
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* @adapter: I2C adapter for DDC channel |
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* @set: ret or reset the high clock ratio |
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* |
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* |
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* TMDS clock ratio calculations go like this: |
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* TMDS character = 10 bit TMDS encoded value |
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* |
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* TMDS character rate = The rate at which TMDS characters are |
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* transmitted (Mcsc) |
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* |
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* TMDS bit rate = 10x TMDS character rate |
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* |
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* As per the spec: |
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* TMDS clock rate for pixel clock < 340 MHz = 1x the character |
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* rate = 1/10 pixel clock rate |
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* |
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* TMDS clock rate for pixel clock > 340 MHz = 0.25x the character |
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* rate = 1/40 pixel clock rate |
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* |
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* Writes to the TMDS config register over SCDC channel, and: |
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* sets TMDS clock ratio to 1/40 when set = 1 |
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* |
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* sets TMDS clock ratio to 1/10 when set = 0 |
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* |
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* Returns: |
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* True if write is successful, false otherwise. |
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*/ |
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bool drm_scdc_set_high_tmds_clock_ratio(struct i2c_adapter *adapter, bool set) |
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{ |
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u8 config; |
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int ret; |
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ret = drm_scdc_readb(adapter, SCDC_TMDS_CONFIG, &config); |
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if (ret < 0) { |
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DRM_DEBUG_KMS("Failed to read TMDS config: %d\n", ret); |
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return false; |
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} |
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if (set) |
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config |= SCDC_TMDS_BIT_CLOCK_RATIO_BY_40; |
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else |
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config &= ~SCDC_TMDS_BIT_CLOCK_RATIO_BY_40; |
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ret = drm_scdc_writeb(adapter, SCDC_TMDS_CONFIG, config); |
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if (ret < 0) { |
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DRM_DEBUG_KMS("Failed to set TMDS clock ratio: %d\n", ret); |
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return false; |
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} |
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/* |
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* The spec says that a source should wait minimum 1ms and maximum |
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* 100ms after writing the TMDS config for clock ratio. Lets allow a |
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* wait of up to 2ms here. |
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*/ |
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usleep_range(1000, 2000); |
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return true; |
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} |
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EXPORT_SYMBOL(drm_scdc_set_high_tmds_clock_ratio);
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