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314 lines
7.7 KiB
314 lines
7.7 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* Intel Medfield MSIC GPIO driver> |
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* Copyright (c) 2011, Intel Corporation. |
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* |
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* Author: Mathias Nyman <[email protected]> |
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* Based on intel_pmic_gpio.c |
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*/ |
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#include <linux/gpio/driver.h> |
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#include <linux/init.h> |
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#include <linux/interrupt.h> |
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#include <linux/kernel.h> |
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#include <linux/mfd/intel_msic.h> |
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#include <linux/platform_device.h> |
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#include <linux/slab.h> |
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/* the offset for the mapping of global gpio pin to irq */ |
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#define MSIC_GPIO_IRQ_OFFSET 0x100 |
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#define MSIC_GPIO_DIR_IN 0 |
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#define MSIC_GPIO_DIR_OUT BIT(5) |
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#define MSIC_GPIO_TRIG_FALL BIT(1) |
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#define MSIC_GPIO_TRIG_RISE BIT(2) |
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/* masks for msic gpio output GPIOxxxxCTLO registers */ |
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#define MSIC_GPIO_DIR_MASK BIT(5) |
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#define MSIC_GPIO_DRV_MASK BIT(4) |
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#define MSIC_GPIO_REN_MASK BIT(3) |
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#define MSIC_GPIO_RVAL_MASK (BIT(2) | BIT(1)) |
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#define MSIC_GPIO_DOUT_MASK BIT(0) |
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/* masks for msic gpio input GPIOxxxxCTLI registers */ |
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#define MSIC_GPIO_GLBYP_MASK BIT(5) |
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#define MSIC_GPIO_DBNC_MASK (BIT(4) | BIT(3)) |
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#define MSIC_GPIO_INTCNT_MASK (BIT(2) | BIT(1)) |
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#define MSIC_GPIO_DIN_MASK BIT(0) |
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#define MSIC_NUM_GPIO 24 |
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struct msic_gpio { |
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struct platform_device *pdev; |
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struct mutex buslock; |
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struct gpio_chip chip; |
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int irq; |
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unsigned irq_base; |
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unsigned long trig_change_mask; |
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unsigned trig_type; |
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}; |
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/* |
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* MSIC has 24 gpios, 16 low voltage (1.2-1.8v) and 8 high voltage (3v). |
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* Both the high and low voltage gpios are divided in two banks. |
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* GPIOs are numbered with GPIO0LV0 as gpio_base in the following order: |
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* GPIO0LV0..GPIO0LV7: low voltage, bank 0, gpio_base |
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* GPIO1LV0..GPIO1LV7: low voltage, bank 1, gpio_base + 8 |
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* GPIO0HV0..GPIO0HV3: high voltage, bank 0, gpio_base + 16 |
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* GPIO1HV0..GPIO1HV3: high voltage, bank 1, gpio_base + 20 |
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*/ |
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static int msic_gpio_to_ireg(unsigned offset) |
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{ |
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if (offset >= MSIC_NUM_GPIO) |
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return -EINVAL; |
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if (offset < 8) |
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return INTEL_MSIC_GPIO0LV0CTLI - offset; |
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if (offset < 16) |
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return INTEL_MSIC_GPIO1LV0CTLI - offset + 8; |
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if (offset < 20) |
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return INTEL_MSIC_GPIO0HV0CTLI - offset + 16; |
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return INTEL_MSIC_GPIO1HV0CTLI - offset + 20; |
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} |
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static int msic_gpio_to_oreg(unsigned offset) |
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{ |
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if (offset >= MSIC_NUM_GPIO) |
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return -EINVAL; |
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if (offset < 8) |
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return INTEL_MSIC_GPIO0LV0CTLO - offset; |
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if (offset < 16) |
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return INTEL_MSIC_GPIO1LV0CTLO - offset + 8; |
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if (offset < 20) |
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return INTEL_MSIC_GPIO0HV0CTLO - offset + 16; |
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return INTEL_MSIC_GPIO1HV0CTLO - offset + 20; |
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} |
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static int msic_gpio_direction_input(struct gpio_chip *chip, unsigned offset) |
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{ |
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int reg; |
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reg = msic_gpio_to_oreg(offset); |
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if (reg < 0) |
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return reg; |
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return intel_msic_reg_update(reg, MSIC_GPIO_DIR_IN, MSIC_GPIO_DIR_MASK); |
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} |
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static int msic_gpio_direction_output(struct gpio_chip *chip, |
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unsigned offset, int value) |
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{ |
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int reg; |
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unsigned mask; |
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value = (!!value) | MSIC_GPIO_DIR_OUT; |
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mask = MSIC_GPIO_DIR_MASK | MSIC_GPIO_DOUT_MASK; |
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reg = msic_gpio_to_oreg(offset); |
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if (reg < 0) |
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return reg; |
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return intel_msic_reg_update(reg, value, mask); |
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} |
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static int msic_gpio_get(struct gpio_chip *chip, unsigned offset) |
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{ |
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u8 r; |
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int ret; |
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int reg; |
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reg = msic_gpio_to_ireg(offset); |
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if (reg < 0) |
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return reg; |
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ret = intel_msic_reg_read(reg, &r); |
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if (ret < 0) |
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return ret; |
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return !!(r & MSIC_GPIO_DIN_MASK); |
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} |
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static void msic_gpio_set(struct gpio_chip *chip, unsigned offset, int value) |
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{ |
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int reg; |
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reg = msic_gpio_to_oreg(offset); |
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if (reg < 0) |
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return; |
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intel_msic_reg_update(reg, !!value , MSIC_GPIO_DOUT_MASK); |
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} |
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/* |
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* This is called from genirq with mg->buslock locked and |
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* irq_desc->lock held. We can not access the scu bus here, so we |
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* store the change and update in the bus_sync_unlock() function below |
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*/ |
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static int msic_irq_type(struct irq_data *data, unsigned type) |
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{ |
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struct msic_gpio *mg = irq_data_get_irq_chip_data(data); |
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u32 gpio = data->irq - mg->irq_base; |
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if (gpio >= mg->chip.ngpio) |
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return -EINVAL; |
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/* mark for which gpio the trigger changed, protected by buslock */ |
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mg->trig_change_mask |= (1 << gpio); |
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mg->trig_type = type; |
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return 0; |
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} |
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static int msic_gpio_to_irq(struct gpio_chip *chip, unsigned offset) |
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{ |
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struct msic_gpio *mg = gpiochip_get_data(chip); |
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return mg->irq_base + offset; |
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} |
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static void msic_bus_lock(struct irq_data *data) |
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{ |
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struct msic_gpio *mg = irq_data_get_irq_chip_data(data); |
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mutex_lock(&mg->buslock); |
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} |
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static void msic_bus_sync_unlock(struct irq_data *data) |
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{ |
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struct msic_gpio *mg = irq_data_get_irq_chip_data(data); |
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int offset; |
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int reg; |
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u8 trig = 0; |
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/* We can only get one change at a time as the buslock covers the |
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entire transaction. The irq_desc->lock is dropped before we are |
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called but that is fine */ |
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if (mg->trig_change_mask) { |
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offset = __ffs(mg->trig_change_mask); |
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reg = msic_gpio_to_ireg(offset); |
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if (reg < 0) |
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goto out; |
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if (mg->trig_type & IRQ_TYPE_EDGE_RISING) |
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trig |= MSIC_GPIO_TRIG_RISE; |
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if (mg->trig_type & IRQ_TYPE_EDGE_FALLING) |
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trig |= MSIC_GPIO_TRIG_FALL; |
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intel_msic_reg_update(reg, trig, MSIC_GPIO_INTCNT_MASK); |
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mg->trig_change_mask = 0; |
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} |
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out: |
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mutex_unlock(&mg->buslock); |
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} |
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/* Firmware does all the masking and unmasking for us, no masking here. */ |
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static void msic_irq_unmask(struct irq_data *data) { } |
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static void msic_irq_mask(struct irq_data *data) { } |
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static struct irq_chip msic_irqchip = { |
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.name = "MSIC-GPIO", |
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.irq_mask = msic_irq_mask, |
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.irq_unmask = msic_irq_unmask, |
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.irq_set_type = msic_irq_type, |
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.irq_bus_lock = msic_bus_lock, |
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.irq_bus_sync_unlock = msic_bus_sync_unlock, |
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}; |
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static void msic_gpio_irq_handler(struct irq_desc *desc) |
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{ |
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struct irq_data *data = irq_desc_get_irq_data(desc); |
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struct msic_gpio *mg = irq_data_get_irq_handler_data(data); |
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struct irq_chip *chip = irq_data_get_irq_chip(data); |
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struct intel_msic *msic = pdev_to_intel_msic(mg->pdev); |
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unsigned long pending; |
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int i; |
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int bitnr; |
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u8 pin; |
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for (i = 0; i < (mg->chip.ngpio / BITS_PER_BYTE); i++) { |
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intel_msic_irq_read(msic, INTEL_MSIC_GPIO0LVIRQ + i, &pin); |
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pending = pin; |
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for_each_set_bit(bitnr, &pending, BITS_PER_BYTE) |
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generic_handle_irq(mg->irq_base + i * BITS_PER_BYTE + bitnr); |
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} |
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chip->irq_eoi(data); |
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} |
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static int platform_msic_gpio_probe(struct platform_device *pdev) |
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{ |
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struct device *dev = &pdev->dev; |
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struct intel_msic_gpio_pdata *pdata = dev_get_platdata(dev); |
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struct msic_gpio *mg; |
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int irq = platform_get_irq(pdev, 0); |
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int retval; |
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int i; |
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if (irq < 0) { |
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dev_err(dev, "no IRQ line: %d\n", irq); |
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return irq; |
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} |
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if (!pdata || !pdata->gpio_base) { |
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dev_err(dev, "incorrect or missing platform data\n"); |
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return -EINVAL; |
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} |
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mg = kzalloc(sizeof(*mg), GFP_KERNEL); |
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if (!mg) |
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return -ENOMEM; |
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dev_set_drvdata(dev, mg); |
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mg->pdev = pdev; |
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mg->irq = irq; |
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mg->irq_base = pdata->gpio_base + MSIC_GPIO_IRQ_OFFSET; |
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mg->chip.label = "msic_gpio"; |
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mg->chip.direction_input = msic_gpio_direction_input; |
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mg->chip.direction_output = msic_gpio_direction_output; |
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mg->chip.get = msic_gpio_get; |
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mg->chip.set = msic_gpio_set; |
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mg->chip.to_irq = msic_gpio_to_irq; |
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mg->chip.base = pdata->gpio_base; |
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mg->chip.ngpio = MSIC_NUM_GPIO; |
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mg->chip.can_sleep = true; |
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mg->chip.parent = dev; |
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mutex_init(&mg->buslock); |
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retval = gpiochip_add_data(&mg->chip, mg); |
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if (retval) { |
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dev_err(dev, "Adding MSIC gpio chip failed\n"); |
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goto err; |
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} |
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for (i = 0; i < mg->chip.ngpio; i++) { |
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irq_set_chip_data(i + mg->irq_base, mg); |
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irq_set_chip_and_handler(i + mg->irq_base, |
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&msic_irqchip, |
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handle_simple_irq); |
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} |
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irq_set_chained_handler_and_data(mg->irq, msic_gpio_irq_handler, mg); |
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return 0; |
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err: |
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kfree(mg); |
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return retval; |
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} |
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static struct platform_driver platform_msic_gpio_driver = { |
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.driver = { |
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.name = "msic_gpio", |
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}, |
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.probe = platform_msic_gpio_probe, |
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}; |
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static int __init platform_msic_gpio_init(void) |
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{ |
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return platform_driver_register(&platform_msic_gpio_driver); |
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} |
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subsys_initcall(platform_msic_gpio_init);
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