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296 lines
7.6 KiB
296 lines
7.6 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* Watchdog driver for Intel Keem Bay non-secure watchdog. |
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* |
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* Copyright (C) 2020 Intel Corporation |
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*/ |
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#include <linux/arm-smccc.h> |
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#include <linux/bits.h> |
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#include <linux/clk.h> |
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#include <linux/interrupt.h> |
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#include <linux/io.h> |
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#include <linux/limits.h> |
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#include <linux/module.h> |
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#include <linux/mod_devicetable.h> |
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#include <linux/platform_device.h> |
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#include <linux/reboot.h> |
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#include <linux/watchdog.h> |
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/* Non-secure watchdog register offsets */ |
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#define TIM_WATCHDOG 0x0 |
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#define TIM_WATCHDOG_INT_THRES 0x4 |
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#define TIM_WDOG_EN 0x8 |
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#define TIM_SAFE 0xc |
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#define WDT_TH_INT_MASK BIT(8) |
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#define WDT_TO_INT_MASK BIT(9) |
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#define WDT_INT_CLEAR_SMC 0x8200ff18 |
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#define WDT_UNLOCK 0xf1d0dead |
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#define WDT_DISABLE 0x0 |
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#define WDT_ENABLE 0x1 |
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#define WDT_LOAD_MAX U32_MAX |
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#define WDT_LOAD_MIN 1 |
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#define WDT_TIMEOUT 5 |
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#define WDT_PRETIMEOUT 4 |
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static unsigned int timeout = WDT_TIMEOUT; |
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module_param(timeout, int, 0); |
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MODULE_PARM_DESC(timeout, "Watchdog timeout period in seconds (default = " |
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__MODULE_STRING(WDT_TIMEOUT) ")"); |
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static bool nowayout = WATCHDOG_NOWAYOUT; |
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module_param(nowayout, bool, 0); |
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MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default = " |
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__MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); |
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struct keembay_wdt { |
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struct watchdog_device wdd; |
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struct clk *clk; |
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unsigned int rate; |
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int to_irq; |
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int th_irq; |
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void __iomem *base; |
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}; |
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static inline u32 keembay_wdt_readl(struct keembay_wdt *wdt, u32 offset) |
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{ |
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return readl(wdt->base + offset); |
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} |
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static inline void keembay_wdt_writel(struct keembay_wdt *wdt, u32 offset, u32 val) |
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{ |
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writel(WDT_UNLOCK, wdt->base + TIM_SAFE); |
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writel(val, wdt->base + offset); |
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} |
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static void keembay_wdt_set_timeout_reg(struct watchdog_device *wdog) |
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{ |
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struct keembay_wdt *wdt = watchdog_get_drvdata(wdog); |
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keembay_wdt_writel(wdt, TIM_WATCHDOG, wdog->timeout * wdt->rate); |
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} |
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static void keembay_wdt_set_pretimeout_reg(struct watchdog_device *wdog) |
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{ |
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struct keembay_wdt *wdt = watchdog_get_drvdata(wdog); |
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u32 th_val = 0; |
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if (wdog->pretimeout) |
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th_val = wdog->timeout - wdog->pretimeout; |
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keembay_wdt_writel(wdt, TIM_WATCHDOG_INT_THRES, th_val * wdt->rate); |
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} |
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static int keembay_wdt_start(struct watchdog_device *wdog) |
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{ |
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struct keembay_wdt *wdt = watchdog_get_drvdata(wdog); |
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keembay_wdt_writel(wdt, TIM_WDOG_EN, WDT_ENABLE); |
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return 0; |
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} |
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static int keembay_wdt_stop(struct watchdog_device *wdog) |
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{ |
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struct keembay_wdt *wdt = watchdog_get_drvdata(wdog); |
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keembay_wdt_writel(wdt, TIM_WDOG_EN, WDT_DISABLE); |
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return 0; |
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} |
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static int keembay_wdt_ping(struct watchdog_device *wdog) |
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{ |
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keembay_wdt_set_timeout_reg(wdog); |
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return 0; |
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} |
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static int keembay_wdt_set_timeout(struct watchdog_device *wdog, u32 t) |
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{ |
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wdog->timeout = t; |
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keembay_wdt_set_timeout_reg(wdog); |
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keembay_wdt_set_pretimeout_reg(wdog); |
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return 0; |
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} |
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static int keembay_wdt_set_pretimeout(struct watchdog_device *wdog, u32 t) |
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{ |
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if (t > wdog->timeout) |
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return -EINVAL; |
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wdog->pretimeout = t; |
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keembay_wdt_set_pretimeout_reg(wdog); |
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return 0; |
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} |
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static unsigned int keembay_wdt_get_timeleft(struct watchdog_device *wdog) |
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{ |
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struct keembay_wdt *wdt = watchdog_get_drvdata(wdog); |
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return keembay_wdt_readl(wdt, TIM_WATCHDOG) / wdt->rate; |
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} |
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/* |
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* SMC call is used to clear the interrupt bits, because the TIM_GEN_CONFIG |
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* register is in the secure bank. |
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*/ |
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static irqreturn_t keembay_wdt_to_isr(int irq, void *dev_id) |
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{ |
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struct keembay_wdt *wdt = dev_id; |
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struct arm_smccc_res res; |
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arm_smccc_smc(WDT_INT_CLEAR_SMC, WDT_TO_INT_MASK, 0, 0, 0, 0, 0, 0, &res); |
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dev_crit(wdt->wdd.parent, "Intel Keem Bay non-secure wdt timeout.\n"); |
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emergency_restart(); |
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return IRQ_HANDLED; |
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} |
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static irqreturn_t keembay_wdt_th_isr(int irq, void *dev_id) |
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{ |
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struct keembay_wdt *wdt = dev_id; |
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struct arm_smccc_res res; |
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keembay_wdt_set_pretimeout(&wdt->wdd, 0x0); |
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arm_smccc_smc(WDT_INT_CLEAR_SMC, WDT_TH_INT_MASK, 0, 0, 0, 0, 0, 0, &res); |
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dev_crit(wdt->wdd.parent, "Intel Keem Bay non-secure wdt pre-timeout.\n"); |
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watchdog_notify_pretimeout(&wdt->wdd); |
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return IRQ_HANDLED; |
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} |
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static const struct watchdog_info keembay_wdt_info = { |
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.identity = "Intel Keem Bay Watchdog Timer", |
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.options = WDIOF_SETTIMEOUT | |
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WDIOF_PRETIMEOUT | |
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WDIOF_MAGICCLOSE | |
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WDIOF_KEEPALIVEPING, |
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}; |
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static const struct watchdog_ops keembay_wdt_ops = { |
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.owner = THIS_MODULE, |
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.start = keembay_wdt_start, |
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.stop = keembay_wdt_stop, |
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.ping = keembay_wdt_ping, |
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.set_timeout = keembay_wdt_set_timeout, |
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.set_pretimeout = keembay_wdt_set_pretimeout, |
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.get_timeleft = keembay_wdt_get_timeleft, |
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}; |
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static int keembay_wdt_probe(struct platform_device *pdev) |
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{ |
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struct device *dev = &pdev->dev; |
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struct keembay_wdt *wdt; |
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int ret; |
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wdt = devm_kzalloc(dev, sizeof(*wdt), GFP_KERNEL); |
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if (!wdt) |
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return -ENOMEM; |
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wdt->base = devm_platform_ioremap_resource(pdev, 0); |
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if (IS_ERR(wdt->base)) |
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return PTR_ERR(wdt->base); |
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/* we do not need to enable the clock as it is enabled by default */ |
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wdt->clk = devm_clk_get(dev, NULL); |
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if (IS_ERR(wdt->clk)) |
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return dev_err_probe(dev, PTR_ERR(wdt->clk), "Failed to get clock\n"); |
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wdt->rate = clk_get_rate(wdt->clk); |
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if (!wdt->rate) |
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return dev_err_probe(dev, -EINVAL, "Failed to get clock rate\n"); |
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wdt->th_irq = platform_get_irq_byname(pdev, "threshold"); |
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if (wdt->th_irq < 0) |
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return dev_err_probe(dev, wdt->th_irq, "Failed to get IRQ for threshold\n"); |
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ret = devm_request_irq(dev, wdt->th_irq, keembay_wdt_th_isr, 0, |
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"keembay-wdt", wdt); |
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if (ret) |
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return dev_err_probe(dev, ret, "Failed to request IRQ for threshold\n"); |
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wdt->to_irq = platform_get_irq_byname(pdev, "timeout"); |
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if (wdt->to_irq < 0) |
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return dev_err_probe(dev, wdt->to_irq, "Failed to get IRQ for timeout\n"); |
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ret = devm_request_irq(dev, wdt->to_irq, keembay_wdt_to_isr, 0, |
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"keembay-wdt", wdt); |
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if (ret) |
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return dev_err_probe(dev, ret, "Failed to request IRQ for timeout\n"); |
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wdt->wdd.parent = dev; |
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wdt->wdd.info = &keembay_wdt_info; |
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wdt->wdd.ops = &keembay_wdt_ops; |
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wdt->wdd.min_timeout = WDT_LOAD_MIN; |
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wdt->wdd.max_timeout = WDT_LOAD_MAX / wdt->rate; |
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wdt->wdd.timeout = WDT_TIMEOUT; |
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wdt->wdd.pretimeout = WDT_PRETIMEOUT; |
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watchdog_set_drvdata(&wdt->wdd, wdt); |
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watchdog_set_nowayout(&wdt->wdd, nowayout); |
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watchdog_init_timeout(&wdt->wdd, timeout, dev); |
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keembay_wdt_set_timeout(&wdt->wdd, wdt->wdd.timeout); |
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keembay_wdt_set_pretimeout(&wdt->wdd, wdt->wdd.pretimeout); |
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ret = devm_watchdog_register_device(dev, &wdt->wdd); |
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if (ret) |
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return dev_err_probe(dev, ret, "Failed to register watchdog device.\n"); |
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platform_set_drvdata(pdev, wdt); |
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dev_info(dev, "Initial timeout %d sec%s.\n", |
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wdt->wdd.timeout, nowayout ? ", nowayout" : ""); |
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return 0; |
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} |
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static int __maybe_unused keembay_wdt_suspend(struct device *dev) |
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{ |
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struct keembay_wdt *wdt = dev_get_drvdata(dev); |
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if (watchdog_active(&wdt->wdd)) |
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return keembay_wdt_stop(&wdt->wdd); |
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return 0; |
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} |
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static int __maybe_unused keembay_wdt_resume(struct device *dev) |
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{ |
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struct keembay_wdt *wdt = dev_get_drvdata(dev); |
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if (watchdog_active(&wdt->wdd)) |
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return keembay_wdt_start(&wdt->wdd); |
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return 0; |
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} |
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static SIMPLE_DEV_PM_OPS(keembay_wdt_pm_ops, keembay_wdt_suspend, |
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keembay_wdt_resume); |
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static const struct of_device_id keembay_wdt_match[] = { |
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{ .compatible = "intel,keembay-wdt" }, |
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{ } |
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}; |
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MODULE_DEVICE_TABLE(of, keembay_wdt_match); |
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static struct platform_driver keembay_wdt_driver = { |
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.probe = keembay_wdt_probe, |
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.driver = { |
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.name = "keembay_wdt", |
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.of_match_table = keembay_wdt_match, |
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.pm = &keembay_wdt_pm_ops, |
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}, |
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}; |
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module_platform_driver(keembay_wdt_driver); |
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MODULE_DESCRIPTION("Intel Keem Bay SoC watchdog driver"); |
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MODULE_AUTHOR("Wan Ahmad Zainie <[email protected]"); |
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MODULE_LICENSE("GPL v2");
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