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501 lines
12 KiB
501 lines
12 KiB
/* |
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* Shared interrupt handling code for IPR and INTC2 types of IRQs. |
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* |
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* Copyright (C) 2007, 2008 Magnus Damm |
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* Copyright (C) 2009 - 2012 Paul Mundt |
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* |
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* Based on intc2.c and ipr.c |
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* |
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* Copyright (C) 1999 Niibe Yutaka & Takeshi Yaegashi |
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* Copyright (C) 2000 Kazumoto Kojima |
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* Copyright (C) 2001 David J. Mckay ([email protected]) |
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* Copyright (C) 2003 Takashi Kusuda <[email protected]> |
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* Copyright (C) 2005, 2006 Paul Mundt |
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* |
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* This file is subject to the terms and conditions of the GNU General Public |
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* License. See the file "COPYING" in the main directory of this archive |
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* for more details. |
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*/ |
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#define pr_fmt(fmt) "intc: " fmt |
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|
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#include <linux/init.h> |
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#include <linux/irq.h> |
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#include <linux/io.h> |
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#include <linux/slab.h> |
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#include <linux/stat.h> |
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#include <linux/interrupt.h> |
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#include <linux/sh_intc.h> |
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#include <linux/irqdomain.h> |
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#include <linux/device.h> |
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#include <linux/syscore_ops.h> |
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#include <linux/list.h> |
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#include <linux/spinlock.h> |
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#include <linux/radix-tree.h> |
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#include <linux/export.h> |
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#include <linux/sort.h> |
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#include "internals.h" |
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LIST_HEAD(intc_list); |
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DEFINE_RAW_SPINLOCK(intc_big_lock); |
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static unsigned int nr_intc_controllers; |
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/* |
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* Default priority level |
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* - this needs to be at least 2 for 5-bit priorities on 7780 |
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*/ |
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static unsigned int default_prio_level = 2; /* 2 - 16 */ |
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static unsigned int intc_prio_level[INTC_NR_IRQS]; /* for now */ |
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unsigned int intc_get_dfl_prio_level(void) |
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{ |
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return default_prio_level; |
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} |
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unsigned int intc_get_prio_level(unsigned int irq) |
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{ |
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return intc_prio_level[irq]; |
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} |
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void intc_set_prio_level(unsigned int irq, unsigned int level) |
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{ |
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unsigned long flags; |
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raw_spin_lock_irqsave(&intc_big_lock, flags); |
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intc_prio_level[irq] = level; |
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raw_spin_unlock_irqrestore(&intc_big_lock, flags); |
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} |
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static void intc_redirect_irq(struct irq_desc *desc) |
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{ |
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generic_handle_irq((unsigned int)irq_desc_get_handler_data(desc)); |
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} |
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static void __init intc_register_irq(struct intc_desc *desc, |
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struct intc_desc_int *d, |
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intc_enum enum_id, |
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unsigned int irq) |
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{ |
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struct intc_handle_int *hp; |
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struct irq_data *irq_data; |
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unsigned int data[2], primary; |
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unsigned long flags; |
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raw_spin_lock_irqsave(&intc_big_lock, flags); |
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radix_tree_insert(&d->tree, enum_id, intc_irq_xlate_get(irq)); |
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raw_spin_unlock_irqrestore(&intc_big_lock, flags); |
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/* |
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* Prefer single interrupt source bitmap over other combinations: |
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* |
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* 1. bitmap, single interrupt source |
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* 2. priority, single interrupt source |
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* 3. bitmap, multiple interrupt sources (groups) |
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* 4. priority, multiple interrupt sources (groups) |
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*/ |
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data[0] = intc_get_mask_handle(desc, d, enum_id, 0); |
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data[1] = intc_get_prio_handle(desc, d, enum_id, 0); |
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primary = 0; |
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if (!data[0] && data[1]) |
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primary = 1; |
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if (!data[0] && !data[1]) |
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pr_warn("missing unique irq mask for irq %d (vect 0x%04x)\n", |
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irq, irq2evt(irq)); |
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data[0] = data[0] ? data[0] : intc_get_mask_handle(desc, d, enum_id, 1); |
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data[1] = data[1] ? data[1] : intc_get_prio_handle(desc, d, enum_id, 1); |
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if (!data[primary]) |
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primary ^= 1; |
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BUG_ON(!data[primary]); /* must have primary masking method */ |
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irq_data = irq_get_irq_data(irq); |
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disable_irq_nosync(irq); |
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irq_set_chip_and_handler_name(irq, &d->chip, handle_level_irq, |
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"level"); |
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irq_set_chip_data(irq, (void *)data[primary]); |
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/* |
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* set priority level |
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*/ |
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intc_set_prio_level(irq, intc_get_dfl_prio_level()); |
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/* enable secondary masking method if present */ |
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if (data[!primary]) |
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_intc_enable(irq_data, data[!primary]); |
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/* add irq to d->prio list if priority is available */ |
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if (data[1]) { |
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hp = d->prio + d->nr_prio; |
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hp->irq = irq; |
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hp->handle = data[1]; |
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if (primary) { |
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/* |
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* only secondary priority should access registers, so |
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* set _INTC_FN(h) = REG_FN_ERR for intc_set_priority() |
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*/ |
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hp->handle &= ~_INTC_MK(0x0f, 0, 0, 0, 0, 0); |
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hp->handle |= _INTC_MK(REG_FN_ERR, 0, 0, 0, 0, 0); |
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} |
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d->nr_prio++; |
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} |
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/* add irq to d->sense list if sense is available */ |
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data[0] = intc_get_sense_handle(desc, d, enum_id); |
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if (data[0]) { |
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(d->sense + d->nr_sense)->irq = irq; |
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(d->sense + d->nr_sense)->handle = data[0]; |
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d->nr_sense++; |
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} |
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/* irq should be disabled by default */ |
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d->chip.irq_mask(irq_data); |
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intc_set_ack_handle(irq, desc, d, enum_id); |
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intc_set_dist_handle(irq, desc, d, enum_id); |
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activate_irq(irq); |
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} |
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static unsigned int __init save_reg(struct intc_desc_int *d, |
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unsigned int cnt, |
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unsigned long value, |
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unsigned int smp) |
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{ |
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if (value) { |
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value = intc_phys_to_virt(d, value); |
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d->reg[cnt] = value; |
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#ifdef CONFIG_SMP |
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d->smp[cnt] = smp; |
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#endif |
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return 1; |
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} |
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return 0; |
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} |
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static bool __init intc_map(struct irq_domain *domain, int irq) |
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{ |
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if (!irq_to_desc(irq) && irq_alloc_desc_at(irq, NUMA_NO_NODE) != irq) { |
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pr_err("uname to allocate IRQ %d\n", irq); |
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return false; |
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} |
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if (irq_domain_associate(domain, irq, irq)) { |
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pr_err("domain association failure\n"); |
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return false; |
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} |
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return true; |
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} |
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int __init register_intc_controller(struct intc_desc *desc) |
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{ |
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unsigned int i, k, smp; |
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struct intc_hw_desc *hw = &desc->hw; |
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struct intc_desc_int *d; |
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struct resource *res; |
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pr_info("Registered controller '%s' with %u IRQs\n", |
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desc->name, hw->nr_vectors); |
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d = kzalloc(sizeof(*d), GFP_NOWAIT); |
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if (!d) |
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goto err0; |
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INIT_LIST_HEAD(&d->list); |
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list_add_tail(&d->list, &intc_list); |
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raw_spin_lock_init(&d->lock); |
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INIT_RADIX_TREE(&d->tree, GFP_ATOMIC); |
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d->index = nr_intc_controllers; |
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if (desc->num_resources) { |
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d->nr_windows = desc->num_resources; |
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d->window = kcalloc(d->nr_windows, sizeof(*d->window), |
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GFP_NOWAIT); |
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if (!d->window) |
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goto err1; |
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for (k = 0; k < d->nr_windows; k++) { |
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res = desc->resource + k; |
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WARN_ON(resource_type(res) != IORESOURCE_MEM); |
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d->window[k].phys = res->start; |
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d->window[k].size = resource_size(res); |
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d->window[k].virt = ioremap(res->start, |
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resource_size(res)); |
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if (!d->window[k].virt) |
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goto err2; |
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} |
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} |
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d->nr_reg = hw->mask_regs ? hw->nr_mask_regs * 2 : 0; |
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#ifdef CONFIG_INTC_BALANCING |
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if (d->nr_reg) |
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d->nr_reg += hw->nr_mask_regs; |
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#endif |
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d->nr_reg += hw->prio_regs ? hw->nr_prio_regs * 2 : 0; |
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d->nr_reg += hw->sense_regs ? hw->nr_sense_regs : 0; |
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d->nr_reg += hw->ack_regs ? hw->nr_ack_regs : 0; |
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d->nr_reg += hw->subgroups ? hw->nr_subgroups : 0; |
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d->reg = kcalloc(d->nr_reg, sizeof(*d->reg), GFP_NOWAIT); |
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if (!d->reg) |
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goto err2; |
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#ifdef CONFIG_SMP |
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d->smp = kcalloc(d->nr_reg, sizeof(*d->smp), GFP_NOWAIT); |
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if (!d->smp) |
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goto err3; |
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#endif |
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k = 0; |
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if (hw->mask_regs) { |
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for (i = 0; i < hw->nr_mask_regs; i++) { |
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smp = IS_SMP(hw->mask_regs[i]); |
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k += save_reg(d, k, hw->mask_regs[i].set_reg, smp); |
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k += save_reg(d, k, hw->mask_regs[i].clr_reg, smp); |
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#ifdef CONFIG_INTC_BALANCING |
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k += save_reg(d, k, hw->mask_regs[i].dist_reg, 0); |
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#endif |
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} |
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} |
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if (hw->prio_regs) { |
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d->prio = kcalloc(hw->nr_vectors, sizeof(*d->prio), |
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GFP_NOWAIT); |
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if (!d->prio) |
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goto err4; |
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for (i = 0; i < hw->nr_prio_regs; i++) { |
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smp = IS_SMP(hw->prio_regs[i]); |
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k += save_reg(d, k, hw->prio_regs[i].set_reg, smp); |
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k += save_reg(d, k, hw->prio_regs[i].clr_reg, smp); |
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} |
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sort(d->prio, hw->nr_prio_regs, sizeof(*d->prio), |
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intc_handle_int_cmp, NULL); |
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} |
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if (hw->sense_regs) { |
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d->sense = kcalloc(hw->nr_vectors, sizeof(*d->sense), |
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GFP_NOWAIT); |
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if (!d->sense) |
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goto err5; |
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for (i = 0; i < hw->nr_sense_regs; i++) |
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k += save_reg(d, k, hw->sense_regs[i].reg, 0); |
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sort(d->sense, hw->nr_sense_regs, sizeof(*d->sense), |
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intc_handle_int_cmp, NULL); |
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} |
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if (hw->subgroups) |
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for (i = 0; i < hw->nr_subgroups; i++) |
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if (hw->subgroups[i].reg) |
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k+= save_reg(d, k, hw->subgroups[i].reg, 0); |
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memcpy(&d->chip, &intc_irq_chip, sizeof(struct irq_chip)); |
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d->chip.name = desc->name; |
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if (hw->ack_regs) |
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for (i = 0; i < hw->nr_ack_regs; i++) |
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k += save_reg(d, k, hw->ack_regs[i].set_reg, 0); |
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else |
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d->chip.irq_mask_ack = d->chip.irq_disable; |
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/* disable bits matching force_disable before registering irqs */ |
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if (desc->force_disable) |
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intc_enable_disable_enum(desc, d, desc->force_disable, 0); |
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/* disable bits matching force_enable before registering irqs */ |
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if (desc->force_enable) |
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intc_enable_disable_enum(desc, d, desc->force_enable, 0); |
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BUG_ON(k > 256); /* _INTC_ADDR_E() and _INTC_ADDR_D() are 8 bits */ |
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intc_irq_domain_init(d, hw); |
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/* register the vectors one by one */ |
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for (i = 0; i < hw->nr_vectors; i++) { |
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struct intc_vect *vect = hw->vectors + i; |
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unsigned int irq = evt2irq(vect->vect); |
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if (!vect->enum_id) |
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continue; |
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if (!intc_map(d->domain, irq)) |
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continue; |
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intc_irq_xlate_set(irq, vect->enum_id, d); |
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intc_register_irq(desc, d, vect->enum_id, irq); |
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for (k = i + 1; k < hw->nr_vectors; k++) { |
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struct intc_vect *vect2 = hw->vectors + k; |
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unsigned int irq2 = evt2irq(vect2->vect); |
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if (vect->enum_id != vect2->enum_id) |
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continue; |
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/* |
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* In the case of multi-evt handling and sparse |
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* IRQ support, each vector still needs to have |
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* its own backing irq_desc. |
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*/ |
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if (!intc_map(d->domain, irq2)) |
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continue; |
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vect2->enum_id = 0; |
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/* redirect this interrupts to the first one */ |
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irq_set_chip(irq2, &dummy_irq_chip); |
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irq_set_chained_handler_and_data(irq2, |
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intc_redirect_irq, |
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(void *)irq); |
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} |
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} |
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intc_subgroup_init(desc, d); |
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/* enable bits matching force_enable after registering irqs */ |
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if (desc->force_enable) |
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intc_enable_disable_enum(desc, d, desc->force_enable, 1); |
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d->skip_suspend = desc->skip_syscore_suspend; |
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nr_intc_controllers++; |
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return 0; |
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err5: |
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kfree(d->prio); |
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err4: |
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#ifdef CONFIG_SMP |
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kfree(d->smp); |
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err3: |
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#endif |
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kfree(d->reg); |
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err2: |
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for (k = 0; k < d->nr_windows; k++) |
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if (d->window[k].virt) |
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iounmap(d->window[k].virt); |
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kfree(d->window); |
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err1: |
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kfree(d); |
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err0: |
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pr_err("unable to allocate INTC memory\n"); |
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return -ENOMEM; |
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} |
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static int intc_suspend(void) |
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{ |
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struct intc_desc_int *d; |
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list_for_each_entry(d, &intc_list, list) { |
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int irq; |
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if (d->skip_suspend) |
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continue; |
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/* enable wakeup irqs belonging to this intc controller */ |
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for_each_active_irq(irq) { |
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struct irq_data *data; |
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struct irq_chip *chip; |
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data = irq_get_irq_data(irq); |
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chip = irq_data_get_irq_chip(data); |
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if (chip != &d->chip) |
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continue; |
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if (irqd_is_wakeup_set(data)) |
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chip->irq_enable(data); |
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} |
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} |
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return 0; |
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} |
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static void intc_resume(void) |
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{ |
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struct intc_desc_int *d; |
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list_for_each_entry(d, &intc_list, list) { |
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int irq; |
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if (d->skip_suspend) |
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continue; |
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for_each_active_irq(irq) { |
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struct irq_data *data; |
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struct irq_chip *chip; |
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data = irq_get_irq_data(irq); |
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chip = irq_data_get_irq_chip(data); |
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/* |
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* This will catch the redirect and VIRQ cases |
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* due to the dummy_irq_chip being inserted. |
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*/ |
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if (chip != &d->chip) |
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continue; |
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if (irqd_irq_disabled(data)) |
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chip->irq_disable(data); |
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else |
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chip->irq_enable(data); |
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} |
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} |
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} |
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struct syscore_ops intc_syscore_ops = { |
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.suspend = intc_suspend, |
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.resume = intc_resume, |
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}; |
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struct bus_type intc_subsys = { |
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.name = "intc", |
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.dev_name = "intc", |
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}; |
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static ssize_t |
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show_intc_name(struct device *dev, struct device_attribute *attr, char *buf) |
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{ |
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struct intc_desc_int *d; |
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d = container_of(dev, struct intc_desc_int, dev); |
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return sprintf(buf, "%s\n", d->chip.name); |
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} |
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static DEVICE_ATTR(name, S_IRUGO, show_intc_name, NULL); |
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static int __init register_intc_devs(void) |
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{ |
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struct intc_desc_int *d; |
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int error; |
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register_syscore_ops(&intc_syscore_ops); |
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error = subsys_system_register(&intc_subsys, NULL); |
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if (!error) { |
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list_for_each_entry(d, &intc_list, list) { |
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d->dev.id = d->index; |
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d->dev.bus = &intc_subsys; |
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error = device_register(&d->dev); |
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if (error == 0) |
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error = device_create_file(&d->dev, |
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&dev_attr_name); |
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if (error) |
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break; |
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} |
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} |
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if (error) |
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pr_err("device registration error\n"); |
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return error; |
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} |
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device_initcall(register_intc_devs);
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