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252 lines
7.6 KiB
252 lines
7.6 KiB
/* SPDX-License-Identifier: GPL-2.0-or-later */ |
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/* |
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* ASIX AX8817X based USB 2.0 Ethernet Devices |
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* Copyright (C) 2003-2006 David Hollis <[email protected]> |
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* Copyright (C) 2005 Phil Chang <[email protected]> |
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* Copyright (C) 2006 James Painter <[email protected]> |
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* Copyright (c) 2002-2003 TiVo Inc. |
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*/ |
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#ifndef _ASIX_H |
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#define _ASIX_H |
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// #define DEBUG // error path messages, extra info |
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// #define VERBOSE // more; success messages |
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#include <linux/module.h> |
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#include <linux/kmod.h> |
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#include <linux/netdevice.h> |
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#include <linux/etherdevice.h> |
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#include <linux/ethtool.h> |
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#include <linux/workqueue.h> |
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#include <linux/mii.h> |
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#include <linux/usb.h> |
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#include <linux/crc32.h> |
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#include <linux/usb/usbnet.h> |
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#include <linux/slab.h> |
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#include <linux/if_vlan.h> |
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#include <linux/phy.h> |
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#include <net/selftests.h> |
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#define DRIVER_VERSION "22-Dec-2011" |
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#define DRIVER_NAME "asix" |
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/* ASIX AX8817X based USB 2.0 Ethernet Devices */ |
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#define AX_CMD_SET_SW_MII 0x06 |
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#define AX_CMD_READ_MII_REG 0x07 |
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#define AX_CMD_WRITE_MII_REG 0x08 |
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#define AX_CMD_STATMNGSTS_REG 0x09 |
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#define AX_CMD_SET_HW_MII 0x0a |
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#define AX_CMD_READ_EEPROM 0x0b |
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#define AX_CMD_WRITE_EEPROM 0x0c |
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#define AX_CMD_WRITE_ENABLE 0x0d |
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#define AX_CMD_WRITE_DISABLE 0x0e |
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#define AX_CMD_READ_RX_CTL 0x0f |
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#define AX_CMD_WRITE_RX_CTL 0x10 |
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#define AX_CMD_READ_IPG012 0x11 |
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#define AX_CMD_WRITE_IPG0 0x12 |
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#define AX_CMD_WRITE_IPG1 0x13 |
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#define AX_CMD_READ_NODE_ID 0x13 |
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#define AX_CMD_WRITE_NODE_ID 0x14 |
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#define AX_CMD_WRITE_IPG2 0x14 |
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#define AX_CMD_WRITE_MULTI_FILTER 0x16 |
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#define AX88172_CMD_READ_NODE_ID 0x17 |
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#define AX_CMD_READ_PHY_ID 0x19 |
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#define AX_CMD_READ_MEDIUM_STATUS 0x1a |
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#define AX_CMD_WRITE_MEDIUM_MODE 0x1b |
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#define AX_CMD_READ_MONITOR_MODE 0x1c |
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#define AX_CMD_WRITE_MONITOR_MODE 0x1d |
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#define AX_CMD_READ_GPIOS 0x1e |
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#define AX_CMD_WRITE_GPIOS 0x1f |
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#define AX_CMD_SW_RESET 0x20 |
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#define AX_CMD_SW_PHY_STATUS 0x21 |
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#define AX_CMD_SW_PHY_SELECT 0x22 |
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#define AX_QCTCTRL 0x2A |
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#define AX_CHIPCODE_MASK 0x70 |
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#define AX_AX88772_CHIPCODE 0x00 |
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#define AX_AX88772A_CHIPCODE 0x10 |
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#define AX_AX88772B_CHIPCODE 0x20 |
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#define AX_HOST_EN 0x01 |
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#define AX_PHYSEL_PSEL 0x01 |
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#define AX_PHYSEL_SSMII 0 |
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#define AX_PHYSEL_SSEN 0x10 |
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#define AX_PHY_SELECT_MASK (BIT(3) | BIT(2)) |
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#define AX_PHY_SELECT_INTERNAL 0 |
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#define AX_PHY_SELECT_EXTERNAL BIT(2) |
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#define AX_MONITOR_MODE 0x01 |
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#define AX_MONITOR_LINK 0x02 |
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#define AX_MONITOR_MAGIC 0x04 |
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#define AX_MONITOR_HSFS 0x10 |
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/* AX88172 Medium Status Register values */ |
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#define AX88172_MEDIUM_FD 0x02 |
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#define AX88172_MEDIUM_TX 0x04 |
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#define AX88172_MEDIUM_FC 0x10 |
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#define AX88172_MEDIUM_DEFAULT \ |
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( AX88172_MEDIUM_FD | AX88172_MEDIUM_TX | AX88172_MEDIUM_FC ) |
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#define AX_MCAST_FILTER_SIZE 8 |
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#define AX_MAX_MCAST 64 |
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#define AX_SWRESET_CLEAR 0x00 |
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#define AX_SWRESET_RR 0x01 |
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#define AX_SWRESET_RT 0x02 |
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#define AX_SWRESET_PRTE 0x04 |
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#define AX_SWRESET_PRL 0x08 |
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#define AX_SWRESET_BZ 0x10 |
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#define AX_SWRESET_IPRL 0x20 |
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#define AX_SWRESET_IPPD 0x40 |
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#define AX88772_IPG0_DEFAULT 0x15 |
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#define AX88772_IPG1_DEFAULT 0x0c |
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#define AX88772_IPG2_DEFAULT 0x12 |
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/* AX88772 & AX88178 Medium Mode Register */ |
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#define AX_MEDIUM_PF 0x0080 |
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#define AX_MEDIUM_JFE 0x0040 |
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#define AX_MEDIUM_TFC 0x0020 |
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#define AX_MEDIUM_RFC 0x0010 |
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#define AX_MEDIUM_ENCK 0x0008 |
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#define AX_MEDIUM_AC 0x0004 |
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#define AX_MEDIUM_FD 0x0002 |
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#define AX_MEDIUM_GM 0x0001 |
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#define AX_MEDIUM_SM 0x1000 |
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#define AX_MEDIUM_SBP 0x0800 |
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#define AX_MEDIUM_PS 0x0200 |
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#define AX_MEDIUM_RE 0x0100 |
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#define AX88178_MEDIUM_DEFAULT \ |
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(AX_MEDIUM_PS | AX_MEDIUM_FD | AX_MEDIUM_AC | \ |
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AX_MEDIUM_RFC | AX_MEDIUM_TFC | AX_MEDIUM_JFE | \ |
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AX_MEDIUM_RE) |
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#define AX88772_MEDIUM_DEFAULT \ |
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(AX_MEDIUM_FD | AX_MEDIUM_RFC | \ |
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AX_MEDIUM_TFC | AX_MEDIUM_PS | \ |
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AX_MEDIUM_AC | AX_MEDIUM_RE) |
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/* AX88772 & AX88178 RX_CTL values */ |
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#define AX_RX_CTL_SO 0x0080 |
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#define AX_RX_CTL_AP 0x0020 |
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#define AX_RX_CTL_AM 0x0010 |
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#define AX_RX_CTL_AB 0x0008 |
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#define AX_RX_CTL_SEP 0x0004 |
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#define AX_RX_CTL_AMALL 0x0002 |
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#define AX_RX_CTL_PRO 0x0001 |
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#define AX_RX_CTL_MFB_2048 0x0000 |
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#define AX_RX_CTL_MFB_4096 0x0100 |
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#define AX_RX_CTL_MFB_8192 0x0200 |
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#define AX_RX_CTL_MFB_16384 0x0300 |
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#define AX_DEFAULT_RX_CTL (AX_RX_CTL_SO | AX_RX_CTL_AB) |
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/* GPIO 0 .. 2 toggles */ |
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#define AX_GPIO_GPO0EN 0x01 /* GPIO0 Output enable */ |
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#define AX_GPIO_GPO_0 0x02 /* GPIO0 Output value */ |
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#define AX_GPIO_GPO1EN 0x04 /* GPIO1 Output enable */ |
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#define AX_GPIO_GPO_1 0x08 /* GPIO1 Output value */ |
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#define AX_GPIO_GPO2EN 0x10 /* GPIO2 Output enable */ |
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#define AX_GPIO_GPO_2 0x20 /* GPIO2 Output value */ |
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#define AX_GPIO_RESERVED 0x40 /* Reserved */ |
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#define AX_GPIO_RSE 0x80 /* Reload serial EEPROM */ |
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#define AX_EEPROM_MAGIC 0xdeadbeef |
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#define AX_EEPROM_LEN 0x200 |
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/* This structure cannot exceed sizeof(unsigned long [5]) AKA 20 bytes */ |
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struct asix_data { |
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u8 multi_filter[AX_MCAST_FILTER_SIZE]; |
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u8 mac_addr[ETH_ALEN]; |
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u8 phymode; |
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u8 ledmode; |
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u8 res; |
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}; |
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struct asix_rx_fixup_info { |
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struct sk_buff *ax_skb; |
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u32 header; |
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u16 remaining; |
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bool split_head; |
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}; |
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struct asix_common_private { |
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void (*resume)(struct usbnet *dev); |
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void (*suspend)(struct usbnet *dev); |
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u16 presvd_phy_advertise; |
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u16 presvd_phy_bmcr; |
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struct asix_rx_fixup_info rx_fixup_info; |
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struct mii_bus *mdio; |
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struct phy_device *phydev; |
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u16 phy_addr; |
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char phy_name[20]; |
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}; |
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extern const struct driver_info ax88172a_info; |
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/* ASIX specific flags */ |
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#define FLAG_EEPROM_MAC (1UL << 0) /* init device MAC from eeprom */ |
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int asix_read_cmd(struct usbnet *dev, u8 cmd, u16 value, u16 index, |
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u16 size, void *data, int in_pm); |
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int asix_write_cmd(struct usbnet *dev, u8 cmd, u16 value, u16 index, |
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u16 size, void *data, int in_pm); |
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void asix_write_cmd_async(struct usbnet *dev, u8 cmd, u16 value, |
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u16 index, u16 size, void *data); |
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int asix_rx_fixup_internal(struct usbnet *dev, struct sk_buff *skb, |
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struct asix_rx_fixup_info *rx); |
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int asix_rx_fixup_common(struct usbnet *dev, struct sk_buff *skb); |
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void asix_rx_fixup_common_free(struct asix_common_private *dp); |
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struct sk_buff *asix_tx_fixup(struct usbnet *dev, struct sk_buff *skb, |
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gfp_t flags); |
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int asix_set_sw_mii(struct usbnet *dev, int in_pm); |
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int asix_set_hw_mii(struct usbnet *dev, int in_pm); |
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int asix_read_phy_addr(struct usbnet *dev, bool internal); |
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int asix_sw_reset(struct usbnet *dev, u8 flags, int in_pm); |
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u16 asix_read_rx_ctl(struct usbnet *dev, int in_pm); |
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int asix_write_rx_ctl(struct usbnet *dev, u16 mode, int in_pm); |
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u16 asix_read_medium_status(struct usbnet *dev, int in_pm); |
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int asix_write_medium_mode(struct usbnet *dev, u16 mode, int in_pm); |
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void asix_adjust_link(struct net_device *netdev); |
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int asix_write_gpio(struct usbnet *dev, u16 value, int sleep, int in_pm); |
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void asix_set_multicast(struct net_device *net); |
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int asix_mdio_read(struct net_device *netdev, int phy_id, int loc); |
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void asix_mdio_write(struct net_device *netdev, int phy_id, int loc, int val); |
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int asix_mdio_bus_read(struct mii_bus *bus, int phy_id, int regnum); |
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int asix_mdio_bus_write(struct mii_bus *bus, int phy_id, int regnum, u16 val); |
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int asix_mdio_read_nopm(struct net_device *netdev, int phy_id, int loc); |
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void asix_mdio_write_nopm(struct net_device *netdev, int phy_id, int loc, |
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int val); |
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void asix_get_wol(struct net_device *net, struct ethtool_wolinfo *wolinfo); |
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int asix_set_wol(struct net_device *net, struct ethtool_wolinfo *wolinfo); |
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int asix_get_eeprom_len(struct net_device *net); |
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int asix_get_eeprom(struct net_device *net, struct ethtool_eeprom *eeprom, |
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u8 *data); |
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int asix_set_eeprom(struct net_device *net, struct ethtool_eeprom *eeprom, |
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u8 *data); |
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void asix_get_drvinfo(struct net_device *net, struct ethtool_drvinfo *info); |
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int asix_set_mac_address(struct net_device *net, void *p); |
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#endif /* _ASIX_H */
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