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1005 lines
24 KiB
1005 lines
24 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* H/W layer of ISHTP provider device (ISH) |
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* |
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* Copyright (c) 2014-2016, Intel Corporation. |
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*/ |
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|
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#include <linux/sched.h> |
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#include <linux/spinlock.h> |
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#include <linux/delay.h> |
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#include <linux/jiffies.h> |
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#include "client.h" |
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#include "hw-ish.h" |
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#include "hbm.h" |
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/* For FW reset flow */ |
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static struct work_struct fw_reset_work; |
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static struct ishtp_device *ishtp_dev; |
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/** |
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* ish_reg_read() - Read register |
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* @dev: ISHTP device pointer |
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* @offset: Register offset |
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* |
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* Read 32 bit register at a given offset |
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* |
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* Return: Read register value |
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*/ |
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static inline uint32_t ish_reg_read(const struct ishtp_device *dev, |
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unsigned long offset) |
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{ |
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struct ish_hw *hw = to_ish_hw(dev); |
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return readl(hw->mem_addr + offset); |
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} |
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/** |
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* ish_reg_write() - Write register |
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* @dev: ISHTP device pointer |
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* @offset: Register offset |
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* @value: Value to write |
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* |
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* Writes 32 bit register at a give offset |
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*/ |
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static inline void ish_reg_write(struct ishtp_device *dev, |
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unsigned long offset, |
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uint32_t value) |
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{ |
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struct ish_hw *hw = to_ish_hw(dev); |
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writel(value, hw->mem_addr + offset); |
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} |
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/** |
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* _ish_read_fw_sts_reg() - Read FW status register |
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* @dev: ISHTP device pointer |
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* |
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* Read FW status register |
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* |
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* Return: Read register value |
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*/ |
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static inline uint32_t _ish_read_fw_sts_reg(struct ishtp_device *dev) |
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{ |
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return ish_reg_read(dev, IPC_REG_ISH_HOST_FWSTS); |
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} |
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/** |
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* check_generated_interrupt() - Check if ISH interrupt |
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* @dev: ISHTP device pointer |
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* |
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* Check if an interrupt was generated for ISH |
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* |
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* Return: Read true or false |
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*/ |
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static bool check_generated_interrupt(struct ishtp_device *dev) |
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{ |
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bool interrupt_generated = true; |
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uint32_t pisr_val = 0; |
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if (dev->pdev->device == CHV_DEVICE_ID) { |
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pisr_val = ish_reg_read(dev, IPC_REG_PISR_CHV_AB); |
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interrupt_generated = |
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IPC_INT_FROM_ISH_TO_HOST_CHV_AB(pisr_val); |
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} else { |
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pisr_val = ish_reg_read(dev, IPC_REG_PISR_BXT); |
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interrupt_generated = !!pisr_val; |
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/* only busy-clear bit is RW, others are RO */ |
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if (pisr_val) |
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ish_reg_write(dev, IPC_REG_PISR_BXT, pisr_val); |
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} |
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return interrupt_generated; |
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} |
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/** |
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* ish_is_input_ready() - Check if FW ready for RX |
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* @dev: ISHTP device pointer |
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* |
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* Check if ISH FW is ready for receiving data |
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* |
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* Return: Read true or false |
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*/ |
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static bool ish_is_input_ready(struct ishtp_device *dev) |
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{ |
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uint32_t doorbell_val; |
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doorbell_val = ish_reg_read(dev, IPC_REG_HOST2ISH_DRBL); |
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return !IPC_IS_BUSY(doorbell_val); |
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} |
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/** |
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* set_host_ready() - Indicate host ready |
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* @dev: ISHTP device pointer |
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* |
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* Set host ready indication to FW |
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*/ |
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static void set_host_ready(struct ishtp_device *dev) |
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{ |
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if (dev->pdev->device == CHV_DEVICE_ID) { |
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if (dev->pdev->revision == REVISION_ID_CHT_A0 || |
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(dev->pdev->revision & REVISION_ID_SI_MASK) == |
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REVISION_ID_CHT_Ax_SI) |
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ish_reg_write(dev, IPC_REG_HOST_COMM, 0x81); |
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else if (dev->pdev->revision == REVISION_ID_CHT_B0 || |
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(dev->pdev->revision & REVISION_ID_SI_MASK) == |
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REVISION_ID_CHT_Bx_SI || |
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(dev->pdev->revision & REVISION_ID_SI_MASK) == |
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REVISION_ID_CHT_Kx_SI || |
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(dev->pdev->revision & REVISION_ID_SI_MASK) == |
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REVISION_ID_CHT_Dx_SI) { |
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uint32_t host_comm_val; |
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host_comm_val = ish_reg_read(dev, IPC_REG_HOST_COMM); |
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host_comm_val |= IPC_HOSTCOMM_INT_EN_BIT_CHV_AB | 0x81; |
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ish_reg_write(dev, IPC_REG_HOST_COMM, host_comm_val); |
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} |
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} else { |
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uint32_t host_pimr_val; |
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host_pimr_val = ish_reg_read(dev, IPC_REG_PIMR_BXT); |
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host_pimr_val |= IPC_PIMR_INT_EN_BIT_BXT; |
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/* |
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* disable interrupt generated instead of |
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* RX_complete_msg |
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*/ |
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host_pimr_val &= ~IPC_HOST2ISH_BUSYCLEAR_MASK_BIT; |
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ish_reg_write(dev, IPC_REG_PIMR_BXT, host_pimr_val); |
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} |
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} |
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/** |
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* ishtp_fw_is_ready() - Check if FW ready |
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* @dev: ISHTP device pointer |
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* |
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* Check if ISH FW is ready |
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* |
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* Return: Read true or false |
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*/ |
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static bool ishtp_fw_is_ready(struct ishtp_device *dev) |
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{ |
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uint32_t ish_status = _ish_read_fw_sts_reg(dev); |
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return IPC_IS_ISH_ILUP(ish_status) && |
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IPC_IS_ISH_ISHTP_READY(ish_status); |
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} |
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/** |
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* ish_set_host_rdy() - Indicate host ready |
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* @dev: ISHTP device pointer |
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* |
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* Set host ready indication to FW |
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*/ |
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static void ish_set_host_rdy(struct ishtp_device *dev) |
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{ |
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uint32_t host_status = ish_reg_read(dev, IPC_REG_HOST_COMM); |
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IPC_SET_HOST_READY(host_status); |
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ish_reg_write(dev, IPC_REG_HOST_COMM, host_status); |
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} |
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/** |
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* ish_clr_host_rdy() - Indicate host not ready |
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* @dev: ISHTP device pointer |
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* |
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* Send host not ready indication to FW |
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*/ |
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static void ish_clr_host_rdy(struct ishtp_device *dev) |
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{ |
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uint32_t host_status = ish_reg_read(dev, IPC_REG_HOST_COMM); |
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IPC_CLEAR_HOST_READY(host_status); |
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ish_reg_write(dev, IPC_REG_HOST_COMM, host_status); |
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} |
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static bool ish_chk_host_rdy(struct ishtp_device *dev) |
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{ |
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uint32_t host_status = ish_reg_read(dev, IPC_REG_HOST_COMM); |
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return (host_status & IPC_HOSTCOMM_READY_BIT); |
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} |
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/** |
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* ish_set_host_ready() - reconfig ipc host registers |
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* @dev: ishtp device pointer |
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* |
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* Set host to ready state |
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* This API is called in some case: |
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* fw is still on, but ipc is powered down. |
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* such as OOB case. |
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* |
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* Return: 0 for success else error fault code |
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*/ |
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void ish_set_host_ready(struct ishtp_device *dev) |
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{ |
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if (ish_chk_host_rdy(dev)) |
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return; |
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ish_set_host_rdy(dev); |
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set_host_ready(dev); |
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} |
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/** |
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* _ishtp_read_hdr() - Read message header |
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* @dev: ISHTP device pointer |
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* |
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* Read header of 32bit length |
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* |
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* Return: Read register value |
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*/ |
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static uint32_t _ishtp_read_hdr(const struct ishtp_device *dev) |
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{ |
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return ish_reg_read(dev, IPC_REG_ISH2HOST_MSG); |
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} |
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/** |
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* _ishtp_read - Read message |
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* @dev: ISHTP device pointer |
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* @buffer: message buffer |
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* @buffer_length: length of message buffer |
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* |
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* Read message from FW |
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* |
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* Return: Always 0 |
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*/ |
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static int _ishtp_read(struct ishtp_device *dev, unsigned char *buffer, |
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unsigned long buffer_length) |
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{ |
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uint32_t i; |
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uint32_t *r_buf = (uint32_t *)buffer; |
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uint32_t msg_offs; |
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msg_offs = IPC_REG_ISH2HOST_MSG + sizeof(struct ishtp_msg_hdr); |
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for (i = 0; i < buffer_length; i += sizeof(uint32_t)) |
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*r_buf++ = ish_reg_read(dev, msg_offs + i); |
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return 0; |
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} |
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/** |
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* write_ipc_from_queue() - try to write ipc msg from Tx queue to device |
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* @dev: ishtp device pointer |
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* |
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* Check if DRBL is cleared. if it is - write the first IPC msg, then call |
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* the callback function (unless it's NULL) |
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* |
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* Return: 0 for success else failure code |
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*/ |
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static int write_ipc_from_queue(struct ishtp_device *dev) |
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{ |
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struct wr_msg_ctl_info *ipc_link; |
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unsigned long length; |
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unsigned long rem; |
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unsigned long flags; |
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uint32_t doorbell_val; |
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uint32_t *r_buf; |
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uint32_t reg_addr; |
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int i; |
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void (*ipc_send_compl)(void *); |
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void *ipc_send_compl_prm; |
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if (dev->dev_state == ISHTP_DEV_DISABLED) |
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return -EINVAL; |
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spin_lock_irqsave(&dev->wr_processing_spinlock, flags); |
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if (!ish_is_input_ready(dev)) { |
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spin_unlock_irqrestore(&dev->wr_processing_spinlock, flags); |
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return -EBUSY; |
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} |
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/* |
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* if tx send list is empty - return 0; |
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* may happen, as RX_COMPLETE handler doesn't check list emptiness. |
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*/ |
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if (list_empty(&dev->wr_processing_list)) { |
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spin_unlock_irqrestore(&dev->wr_processing_spinlock, flags); |
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return 0; |
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} |
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ipc_link = list_first_entry(&dev->wr_processing_list, |
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struct wr_msg_ctl_info, link); |
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/* first 4 bytes of the data is the doorbell value (IPC header) */ |
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length = ipc_link->length - sizeof(uint32_t); |
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doorbell_val = *(uint32_t *)ipc_link->inline_data; |
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r_buf = (uint32_t *)(ipc_link->inline_data + sizeof(uint32_t)); |
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/* If sending MNG_SYNC_FW_CLOCK, update clock again */ |
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if (IPC_HEADER_GET_PROTOCOL(doorbell_val) == IPC_PROTOCOL_MNG && |
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IPC_HEADER_GET_MNG_CMD(doorbell_val) == MNG_SYNC_FW_CLOCK) { |
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uint64_t usec_system, usec_utc; |
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struct ipc_time_update_msg time_update; |
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struct time_sync_format ts_format; |
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usec_system = ktime_to_us(ktime_get_boottime()); |
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usec_utc = ktime_to_us(ktime_get_real()); |
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ts_format.ts1_source = HOST_SYSTEM_TIME_USEC; |
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ts_format.ts2_source = HOST_UTC_TIME_USEC; |
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ts_format.reserved = 0; |
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time_update.primary_host_time = usec_system; |
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time_update.secondary_host_time = usec_utc; |
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time_update.sync_info = ts_format; |
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memcpy(r_buf, &time_update, |
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sizeof(struct ipc_time_update_msg)); |
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} |
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for (i = 0, reg_addr = IPC_REG_HOST2ISH_MSG; i < length >> 2; i++, |
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reg_addr += 4) |
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ish_reg_write(dev, reg_addr, r_buf[i]); |
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rem = length & 0x3; |
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if (rem > 0) { |
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uint32_t reg = 0; |
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memcpy(®, &r_buf[length >> 2], rem); |
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ish_reg_write(dev, reg_addr, reg); |
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} |
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ish_reg_write(dev, IPC_REG_HOST2ISH_DRBL, doorbell_val); |
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/* Flush writes to msg registers and doorbell */ |
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ish_reg_read(dev, IPC_REG_ISH_HOST_FWSTS); |
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/* Update IPC counters */ |
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++dev->ipc_tx_cnt; |
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dev->ipc_tx_bytes_cnt += IPC_HEADER_GET_LENGTH(doorbell_val); |
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ipc_send_compl = ipc_link->ipc_send_compl; |
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ipc_send_compl_prm = ipc_link->ipc_send_compl_prm; |
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list_del_init(&ipc_link->link); |
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list_add(&ipc_link->link, &dev->wr_free_list); |
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spin_unlock_irqrestore(&dev->wr_processing_spinlock, flags); |
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/* |
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* callback will be called out of spinlock, |
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* after ipc_link returned to free list |
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*/ |
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if (ipc_send_compl) |
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ipc_send_compl(ipc_send_compl_prm); |
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return 0; |
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} |
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/** |
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* write_ipc_to_queue() - write ipc msg to Tx queue |
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* @dev: ishtp device instance |
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* @ipc_send_compl: Send complete callback |
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* @ipc_send_compl_prm: Parameter to send in complete callback |
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* @msg: Pointer to message |
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* @length: Length of message |
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* |
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* Recived msg with IPC (and upper protocol) header and add it to the device |
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* Tx-to-write list then try to send the first IPC waiting msg |
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* (if DRBL is cleared) |
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* This function returns negative value for failure (means free list |
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* is empty, or msg too long) and 0 for success. |
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* |
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* Return: 0 for success else failure code |
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*/ |
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static int write_ipc_to_queue(struct ishtp_device *dev, |
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void (*ipc_send_compl)(void *), void *ipc_send_compl_prm, |
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unsigned char *msg, int length) |
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{ |
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struct wr_msg_ctl_info *ipc_link; |
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unsigned long flags; |
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if (length > IPC_FULL_MSG_SIZE) |
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return -EMSGSIZE; |
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spin_lock_irqsave(&dev->wr_processing_spinlock, flags); |
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if (list_empty(&dev->wr_free_list)) { |
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spin_unlock_irqrestore(&dev->wr_processing_spinlock, flags); |
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return -ENOMEM; |
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} |
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ipc_link = list_first_entry(&dev->wr_free_list, |
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struct wr_msg_ctl_info, link); |
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list_del_init(&ipc_link->link); |
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ipc_link->ipc_send_compl = ipc_send_compl; |
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ipc_link->ipc_send_compl_prm = ipc_send_compl_prm; |
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ipc_link->length = length; |
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memcpy(ipc_link->inline_data, msg, length); |
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list_add_tail(&ipc_link->link, &dev->wr_processing_list); |
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spin_unlock_irqrestore(&dev->wr_processing_spinlock, flags); |
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write_ipc_from_queue(dev); |
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return 0; |
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} |
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/** |
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* ipc_send_mng_msg() - Send management message |
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* @dev: ishtp device instance |
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* @msg_code: Message code |
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* @msg: Pointer to message |
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* @size: Length of message |
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* |
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* Send management message to FW |
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* |
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* Return: 0 for success else failure code |
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*/ |
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static int ipc_send_mng_msg(struct ishtp_device *dev, uint32_t msg_code, |
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void *msg, size_t size) |
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{ |
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unsigned char ipc_msg[IPC_FULL_MSG_SIZE]; |
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uint32_t drbl_val = IPC_BUILD_MNG_MSG(msg_code, size); |
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memcpy(ipc_msg, &drbl_val, sizeof(uint32_t)); |
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memcpy(ipc_msg + sizeof(uint32_t), msg, size); |
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return write_ipc_to_queue(dev, NULL, NULL, ipc_msg, |
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sizeof(uint32_t) + size); |
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} |
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#define WAIT_FOR_FW_RDY 0x1 |
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#define WAIT_FOR_INPUT_RDY 0x2 |
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|
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/** |
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* timed_wait_for_timeout() - wait special event with timeout |
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* @dev: ISHTP device pointer |
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* @condition: indicate the condition for waiting |
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* @timeinc: time slice for every wait cycle, in ms |
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* @timeout: time in ms for timeout |
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* |
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* This function will check special event to be ready in a loop, the loop |
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* period is specificd in timeinc. Wait timeout will causes failure. |
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* |
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* Return: 0 for success else failure code |
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*/ |
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static int timed_wait_for_timeout(struct ishtp_device *dev, int condition, |
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unsigned int timeinc, unsigned int timeout) |
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{ |
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bool complete = false; |
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int ret; |
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do { |
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if (condition == WAIT_FOR_FW_RDY) { |
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complete = ishtp_fw_is_ready(dev); |
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} else if (condition == WAIT_FOR_INPUT_RDY) { |
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complete = ish_is_input_ready(dev); |
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} else { |
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ret = -EINVAL; |
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goto out; |
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} |
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if (!complete) { |
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unsigned long left_time; |
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left_time = msleep_interruptible(timeinc); |
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timeout -= (timeinc - left_time); |
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} |
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} while (!complete && timeout > 0); |
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if (complete) |
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ret = 0; |
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else |
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ret = -EBUSY; |
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out: |
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return ret; |
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} |
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#define TIME_SLICE_FOR_FW_RDY_MS 100 |
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#define TIME_SLICE_FOR_INPUT_RDY_MS 100 |
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#define TIMEOUT_FOR_FW_RDY_MS 2000 |
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#define TIMEOUT_FOR_INPUT_RDY_MS 2000 |
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|
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/** |
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* ish_fw_reset_handler() - FW reset handler |
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* @dev: ishtp device pointer |
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* |
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* Handle FW reset |
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* |
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* Return: 0 for success else failure code |
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*/ |
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static int ish_fw_reset_handler(struct ishtp_device *dev) |
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{ |
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uint32_t reset_id; |
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unsigned long flags; |
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|
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/* Read reset ID */ |
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reset_id = ish_reg_read(dev, IPC_REG_ISH2HOST_MSG) & 0xFFFF; |
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|
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/* Clear IPC output queue */ |
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spin_lock_irqsave(&dev->wr_processing_spinlock, flags); |
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list_splice_init(&dev->wr_processing_list, &dev->wr_free_list); |
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spin_unlock_irqrestore(&dev->wr_processing_spinlock, flags); |
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|
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/* ISHTP notification in IPC_RESET */ |
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ishtp_reset_handler(dev); |
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|
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if (!ish_is_input_ready(dev)) |
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timed_wait_for_timeout(dev, WAIT_FOR_INPUT_RDY, |
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TIME_SLICE_FOR_INPUT_RDY_MS, TIMEOUT_FOR_INPUT_RDY_MS); |
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|
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/* ISH FW is dead */ |
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if (!ish_is_input_ready(dev)) |
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return -EPIPE; |
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/* |
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* Set HOST2ISH.ILUP. Apparently we need this BEFORE sending |
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* RESET_NOTIFY_ACK - FW will be checking for it |
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*/ |
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ish_set_host_rdy(dev); |
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/* Send RESET_NOTIFY_ACK (with reset_id) */ |
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ipc_send_mng_msg(dev, MNG_RESET_NOTIFY_ACK, &reset_id, |
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sizeof(uint32_t)); |
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|
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/* Wait for ISH FW'es ILUP and ISHTP_READY */ |
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timed_wait_for_timeout(dev, WAIT_FOR_FW_RDY, |
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TIME_SLICE_FOR_FW_RDY_MS, TIMEOUT_FOR_FW_RDY_MS); |
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if (!ishtp_fw_is_ready(dev)) { |
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/* ISH FW is dead */ |
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uint32_t ish_status; |
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|
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ish_status = _ish_read_fw_sts_reg(dev); |
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dev_err(dev->devc, |
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"[ishtp-ish]: completed reset, ISH is dead (FWSTS = %08X)\n", |
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ish_status); |
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return -ENODEV; |
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} |
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return 0; |
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} |
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|
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#define TIMEOUT_FOR_HW_RDY_MS 300 |
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|
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/** |
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* fw_reset_work_fn() - FW reset worker function |
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* @unused: not used |
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* |
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* Call ish_fw_reset_handler to complete FW reset |
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*/ |
|
static void fw_reset_work_fn(struct work_struct *unused) |
|
{ |
|
int rv; |
|
|
|
rv = ish_fw_reset_handler(ishtp_dev); |
|
if (!rv) { |
|
/* ISH is ILUP & ISHTP-ready. Restart ISHTP */ |
|
msleep_interruptible(TIMEOUT_FOR_HW_RDY_MS); |
|
ishtp_dev->recvd_hw_ready = 1; |
|
wake_up_interruptible(&ishtp_dev->wait_hw_ready); |
|
|
|
/* ISHTP notification in IPC_RESET sequence completion */ |
|
ishtp_reset_compl_handler(ishtp_dev); |
|
} else |
|
dev_err(ishtp_dev->devc, "[ishtp-ish]: FW reset failed (%d)\n", |
|
rv); |
|
} |
|
|
|
/** |
|
* _ish_sync_fw_clock() -Sync FW clock with the OS clock |
|
* @dev: ishtp device pointer |
|
* |
|
* Sync FW and OS time |
|
*/ |
|
static void _ish_sync_fw_clock(struct ishtp_device *dev) |
|
{ |
|
static unsigned long prev_sync; |
|
uint64_t usec; |
|
|
|
if (prev_sync && jiffies - prev_sync < 20 * HZ) |
|
return; |
|
|
|
prev_sync = jiffies; |
|
usec = ktime_to_us(ktime_get_boottime()); |
|
ipc_send_mng_msg(dev, MNG_SYNC_FW_CLOCK, &usec, sizeof(uint64_t)); |
|
} |
|
|
|
/** |
|
* recv_ipc() - Receive and process IPC management messages |
|
* @dev: ishtp device instance |
|
* @doorbell_val: doorbell value |
|
* |
|
* This function runs in ISR context. |
|
* NOTE: Any other mng command than reset_notify and reset_notify_ack |
|
* won't wake BH handler |
|
*/ |
|
static void recv_ipc(struct ishtp_device *dev, uint32_t doorbell_val) |
|
{ |
|
uint32_t mng_cmd; |
|
|
|
mng_cmd = IPC_HEADER_GET_MNG_CMD(doorbell_val); |
|
|
|
switch (mng_cmd) { |
|
default: |
|
break; |
|
|
|
case MNG_RX_CMPL_INDICATION: |
|
if (dev->suspend_flag) { |
|
dev->suspend_flag = 0; |
|
wake_up_interruptible(&dev->suspend_wait); |
|
} |
|
if (dev->resume_flag) { |
|
dev->resume_flag = 0; |
|
wake_up_interruptible(&dev->resume_wait); |
|
} |
|
|
|
write_ipc_from_queue(dev); |
|
break; |
|
|
|
case MNG_RESET_NOTIFY: |
|
if (!ishtp_dev) { |
|
ishtp_dev = dev; |
|
INIT_WORK(&fw_reset_work, fw_reset_work_fn); |
|
} |
|
schedule_work(&fw_reset_work); |
|
break; |
|
|
|
case MNG_RESET_NOTIFY_ACK: |
|
dev->recvd_hw_ready = 1; |
|
wake_up_interruptible(&dev->wait_hw_ready); |
|
break; |
|
} |
|
} |
|
|
|
/** |
|
* ish_irq_handler() - ISH IRQ handler |
|
* @irq: irq number |
|
* @dev_id: ishtp device pointer |
|
* |
|
* ISH IRQ handler. If interrupt is generated and is for ISH it will process |
|
* the interrupt. |
|
*/ |
|
irqreturn_t ish_irq_handler(int irq, void *dev_id) |
|
{ |
|
struct ishtp_device *dev = dev_id; |
|
uint32_t doorbell_val; |
|
bool interrupt_generated; |
|
|
|
/* Check that it's interrupt from ISH (may be shared) */ |
|
interrupt_generated = check_generated_interrupt(dev); |
|
|
|
if (!interrupt_generated) |
|
return IRQ_NONE; |
|
|
|
doorbell_val = ish_reg_read(dev, IPC_REG_ISH2HOST_DRBL); |
|
if (!IPC_IS_BUSY(doorbell_val)) |
|
return IRQ_HANDLED; |
|
|
|
if (dev->dev_state == ISHTP_DEV_DISABLED) |
|
return IRQ_HANDLED; |
|
|
|
/* Sanity check: IPC dgram length in header */ |
|
if (IPC_HEADER_GET_LENGTH(doorbell_val) > IPC_PAYLOAD_SIZE) { |
|
dev_err(dev->devc, |
|
"IPC hdr - bad length: %u; dropped\n", |
|
(unsigned int)IPC_HEADER_GET_LENGTH(doorbell_val)); |
|
goto eoi; |
|
} |
|
|
|
switch (IPC_HEADER_GET_PROTOCOL(doorbell_val)) { |
|
default: |
|
break; |
|
case IPC_PROTOCOL_MNG: |
|
recv_ipc(dev, doorbell_val); |
|
break; |
|
case IPC_PROTOCOL_ISHTP: |
|
ishtp_recv(dev); |
|
break; |
|
} |
|
|
|
eoi: |
|
/* Update IPC counters */ |
|
++dev->ipc_rx_cnt; |
|
dev->ipc_rx_bytes_cnt += IPC_HEADER_GET_LENGTH(doorbell_val); |
|
|
|
ish_reg_write(dev, IPC_REG_ISH2HOST_DRBL, 0); |
|
/* Flush write to doorbell */ |
|
ish_reg_read(dev, IPC_REG_ISH_HOST_FWSTS); |
|
|
|
return IRQ_HANDLED; |
|
} |
|
|
|
/** |
|
* ish_disable_dma() - disable dma communication between host and ISHFW |
|
* @dev: ishtp device pointer |
|
* |
|
* Clear the dma enable bit and wait for dma inactive. |
|
* |
|
* Return: 0 for success else error code. |
|
*/ |
|
int ish_disable_dma(struct ishtp_device *dev) |
|
{ |
|
unsigned int dma_delay; |
|
|
|
/* Clear the dma enable bit */ |
|
ish_reg_write(dev, IPC_REG_ISH_RMP2, 0); |
|
|
|
/* wait for dma inactive */ |
|
for (dma_delay = 0; dma_delay < MAX_DMA_DELAY && |
|
_ish_read_fw_sts_reg(dev) & (IPC_ISH_IN_DMA); |
|
dma_delay += 5) |
|
mdelay(5); |
|
|
|
if (dma_delay >= MAX_DMA_DELAY) { |
|
dev_err(dev->devc, |
|
"Wait for DMA inactive timeout\n"); |
|
return -EBUSY; |
|
} |
|
|
|
return 0; |
|
} |
|
|
|
/** |
|
* ish_wakeup() - wakeup ishfw from waiting-for-host state |
|
* @dev: ishtp device pointer |
|
* |
|
* Set the dma enable bit and send a void message to FW, |
|
* it wil wakeup FW from waiting-for-host state. |
|
*/ |
|
static void ish_wakeup(struct ishtp_device *dev) |
|
{ |
|
/* Set dma enable bit */ |
|
ish_reg_write(dev, IPC_REG_ISH_RMP2, IPC_RMP2_DMA_ENABLED); |
|
|
|
/* |
|
* Send 0 IPC message so that ISH FW wakes up if it was already |
|
* asleep. |
|
*/ |
|
ish_reg_write(dev, IPC_REG_HOST2ISH_DRBL, IPC_DRBL_BUSY_BIT); |
|
|
|
/* Flush writes to doorbell and REMAP2 */ |
|
ish_reg_read(dev, IPC_REG_ISH_HOST_FWSTS); |
|
} |
|
|
|
/** |
|
* _ish_hw_reset() - HW reset |
|
* @dev: ishtp device pointer |
|
* |
|
* Reset ISH HW to recover if any error |
|
* |
|
* Return: 0 for success else error fault code |
|
*/ |
|
static int _ish_hw_reset(struct ishtp_device *dev) |
|
{ |
|
struct pci_dev *pdev = dev->pdev; |
|
int rv; |
|
uint16_t csr; |
|
|
|
if (!pdev) |
|
return -ENODEV; |
|
|
|
rv = pci_reset_function(pdev); |
|
if (!rv) |
|
dev->dev_state = ISHTP_DEV_RESETTING; |
|
|
|
if (!pdev->pm_cap) { |
|
dev_err(&pdev->dev, "Can't reset - no PM caps\n"); |
|
return -EINVAL; |
|
} |
|
|
|
/* Disable dma communication between FW and host */ |
|
if (ish_disable_dma(dev)) { |
|
dev_err(&pdev->dev, |
|
"Can't reset - stuck with DMA in-progress\n"); |
|
return -EBUSY; |
|
} |
|
|
|
pci_read_config_word(pdev, pdev->pm_cap + PCI_PM_CTRL, &csr); |
|
|
|
csr &= ~PCI_PM_CTRL_STATE_MASK; |
|
csr |= PCI_D3hot; |
|
pci_write_config_word(pdev, pdev->pm_cap + PCI_PM_CTRL, csr); |
|
|
|
mdelay(pdev->d3hot_delay); |
|
|
|
csr &= ~PCI_PM_CTRL_STATE_MASK; |
|
csr |= PCI_D0; |
|
pci_write_config_word(pdev, pdev->pm_cap + PCI_PM_CTRL, csr); |
|
|
|
/* Now we can enable ISH DMA operation and wakeup ISHFW */ |
|
ish_wakeup(dev); |
|
|
|
return 0; |
|
} |
|
|
|
/** |
|
* _ish_ipc_reset() - IPC reset |
|
* @dev: ishtp device pointer |
|
* |
|
* Resets host and fw IPC and upper layers |
|
* |
|
* Return: 0 for success else error fault code |
|
*/ |
|
static int _ish_ipc_reset(struct ishtp_device *dev) |
|
{ |
|
struct ipc_rst_payload_type ipc_mng_msg; |
|
int rv = 0; |
|
|
|
ipc_mng_msg.reset_id = 1; |
|
ipc_mng_msg.reserved = 0; |
|
|
|
set_host_ready(dev); |
|
|
|
/* Clear the incoming doorbell */ |
|
ish_reg_write(dev, IPC_REG_ISH2HOST_DRBL, 0); |
|
/* Flush write to doorbell */ |
|
ish_reg_read(dev, IPC_REG_ISH_HOST_FWSTS); |
|
|
|
dev->recvd_hw_ready = 0; |
|
|
|
/* send message */ |
|
rv = ipc_send_mng_msg(dev, MNG_RESET_NOTIFY, &ipc_mng_msg, |
|
sizeof(struct ipc_rst_payload_type)); |
|
if (rv) { |
|
dev_err(dev->devc, "Failed to send IPC MNG_RESET_NOTIFY\n"); |
|
return rv; |
|
} |
|
|
|
wait_event_interruptible_timeout(dev->wait_hw_ready, |
|
dev->recvd_hw_ready, 2 * HZ); |
|
if (!dev->recvd_hw_ready) { |
|
dev_err(dev->devc, "Timed out waiting for HW ready\n"); |
|
rv = -ENODEV; |
|
} |
|
|
|
return rv; |
|
} |
|
|
|
/** |
|
* ish_hw_start() -Start ISH HW |
|
* @dev: ishtp device pointer |
|
* |
|
* Set host to ready state and wait for FW reset |
|
* |
|
* Return: 0 for success else error fault code |
|
*/ |
|
int ish_hw_start(struct ishtp_device *dev) |
|
{ |
|
ish_set_host_rdy(dev); |
|
|
|
set_host_ready(dev); |
|
|
|
/* After that we can enable ISH DMA operation and wakeup ISHFW */ |
|
ish_wakeup(dev); |
|
|
|
/* wait for FW-initiated reset flow */ |
|
if (!dev->recvd_hw_ready) |
|
wait_event_interruptible_timeout(dev->wait_hw_ready, |
|
dev->recvd_hw_ready, |
|
10 * HZ); |
|
|
|
if (!dev->recvd_hw_ready) { |
|
dev_err(dev->devc, |
|
"[ishtp-ish]: Timed out waiting for FW-initiated reset\n"); |
|
return -ENODEV; |
|
} |
|
|
|
return 0; |
|
} |
|
|
|
/** |
|
* ish_ipc_get_header() -Get doorbell value |
|
* @dev: ishtp device pointer |
|
* @length: length of message |
|
* @busy: busy status |
|
* |
|
* Get door bell value from message header |
|
* |
|
* Return: door bell value |
|
*/ |
|
static uint32_t ish_ipc_get_header(struct ishtp_device *dev, int length, |
|
int busy) |
|
{ |
|
uint32_t drbl_val; |
|
|
|
drbl_val = IPC_BUILD_HEADER(length, IPC_PROTOCOL_ISHTP, busy); |
|
|
|
return drbl_val; |
|
} |
|
|
|
/** |
|
* _dma_no_cache_snooping() |
|
* |
|
* Check on current platform, DMA supports cache snooping or not. |
|
* This callback is used to notify uplayer driver if manully cache |
|
* flush is needed when do DMA operation. |
|
* |
|
* Please pay attention to this callback implementation, if declare |
|
* having cache snooping on a cache snooping not supported platform |
|
* will cause uplayer driver receiving mismatched data; and if |
|
* declare no cache snooping on a cache snooping supported platform |
|
* will cause cache be flushed twice and performance hit. |
|
* |
|
* @dev: ishtp device pointer |
|
* |
|
* Return: false - has cache snooping capability |
|
* true - no cache snooping, need manually cache flush |
|
*/ |
|
static bool _dma_no_cache_snooping(struct ishtp_device *dev) |
|
{ |
|
return dev->pdev->device == EHL_Ax_DEVICE_ID; |
|
} |
|
|
|
static const struct ishtp_hw_ops ish_hw_ops = { |
|
.hw_reset = _ish_hw_reset, |
|
.ipc_reset = _ish_ipc_reset, |
|
.ipc_get_header = ish_ipc_get_header, |
|
.ishtp_read = _ishtp_read, |
|
.write = write_ipc_to_queue, |
|
.get_fw_status = _ish_read_fw_sts_reg, |
|
.sync_fw_clock = _ish_sync_fw_clock, |
|
.ishtp_read_hdr = _ishtp_read_hdr, |
|
.dma_no_cache_snooping = _dma_no_cache_snooping |
|
}; |
|
|
|
/** |
|
* ish_dev_init() -Initialize ISH devoce |
|
* @pdev: PCI device |
|
* |
|
* Allocate ISHTP device and initialize IPC processing |
|
* |
|
* Return: ISHTP device instance on success else NULL |
|
*/ |
|
struct ishtp_device *ish_dev_init(struct pci_dev *pdev) |
|
{ |
|
struct ishtp_device *dev; |
|
int i; |
|
|
|
dev = devm_kzalloc(&pdev->dev, |
|
sizeof(struct ishtp_device) + sizeof(struct ish_hw), |
|
GFP_KERNEL); |
|
if (!dev) |
|
return NULL; |
|
|
|
ishtp_device_init(dev); |
|
|
|
init_waitqueue_head(&dev->wait_hw_ready); |
|
|
|
spin_lock_init(&dev->wr_processing_spinlock); |
|
|
|
/* Init IPC processing and free lists */ |
|
INIT_LIST_HEAD(&dev->wr_processing_list); |
|
INIT_LIST_HEAD(&dev->wr_free_list); |
|
for (i = 0; i < IPC_TX_FIFO_SIZE; i++) { |
|
struct wr_msg_ctl_info *tx_buf; |
|
|
|
tx_buf = devm_kzalloc(&pdev->dev, |
|
sizeof(struct wr_msg_ctl_info), |
|
GFP_KERNEL); |
|
if (!tx_buf) { |
|
/* |
|
* IPC buffers may be limited or not available |
|
* at all - although this shouldn't happen |
|
*/ |
|
dev_err(dev->devc, |
|
"[ishtp-ish]: failure in Tx FIFO allocations (%d)\n", |
|
i); |
|
break; |
|
} |
|
list_add_tail(&tx_buf->link, &dev->wr_free_list); |
|
} |
|
|
|
dev->ops = &ish_hw_ops; |
|
dev->devc = &pdev->dev; |
|
dev->mtu = IPC_PAYLOAD_SIZE - sizeof(struct ishtp_msg_hdr); |
|
return dev; |
|
} |
|
|
|
/** |
|
* ish_device_disable() - Disable ISH device |
|
* @dev: ISHTP device pointer |
|
* |
|
* Disable ISH by clearing host ready to inform firmware. |
|
*/ |
|
void ish_device_disable(struct ishtp_device *dev) |
|
{ |
|
struct pci_dev *pdev = dev->pdev; |
|
|
|
if (!pdev) |
|
return; |
|
|
|
/* Disable dma communication between FW and host */ |
|
if (ish_disable_dma(dev)) { |
|
dev_err(&pdev->dev, |
|
"Can't reset - stuck with DMA in-progress\n"); |
|
return; |
|
} |
|
|
|
/* Put ISH to D3hot state for power saving */ |
|
pci_set_power_state(pdev, PCI_D3hot); |
|
|
|
dev->dev_state = ISHTP_DEV_DISABLED; |
|
ish_clr_host_rdy(dev); |
|
}
|
|
|