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223 lines
5.1 KiB
223 lines
5.1 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* Copyright (c) 2018, The Linux Foundation. All rights reserved. |
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*/ |
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#include <linux/bitops.h> |
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#include <linux/err.h> |
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#include <linux/module.h> |
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#include <linux/platform_device.h> |
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#include <linux/pm_clock.h> |
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#include <linux/pm_runtime.h> |
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#include <linux/regmap.h> |
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#include <dt-bindings/clock/qcom,q6sstopcc-qcs404.h> |
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#include "clk-regmap.h" |
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#include "clk-branch.h" |
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#include "common.h" |
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#include "reset.h" |
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static struct clk_branch lcc_ahbfabric_cbc_clk = { |
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.halt_reg = 0x1b004, |
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.halt_check = BRANCH_HALT, |
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.clkr = { |
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.enable_reg = 0x1b004, |
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.enable_mask = BIT(0), |
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.hw.init = &(struct clk_init_data){ |
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.name = "lcc_ahbfabric_cbc_clk", |
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.ops = &clk_branch2_ops, |
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}, |
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}, |
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}; |
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static struct clk_branch lcc_q6ss_ahbs_cbc_clk = { |
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.halt_reg = 0x22000, |
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.halt_check = BRANCH_VOTED, |
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.clkr = { |
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.enable_reg = 0x22000, |
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.enable_mask = BIT(0), |
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.hw.init = &(struct clk_init_data){ |
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.name = "lcc_q6ss_ahbs_cbc_clk", |
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.ops = &clk_branch2_ops, |
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}, |
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}, |
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}; |
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static struct clk_branch lcc_q6ss_tcm_slave_cbc_clk = { |
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.halt_reg = 0x1c000, |
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.halt_check = BRANCH_VOTED, |
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.clkr = { |
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.enable_reg = 0x1c000, |
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.enable_mask = BIT(0), |
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.hw.init = &(struct clk_init_data){ |
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.name = "lcc_q6ss_tcm_slave_cbc_clk", |
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.ops = &clk_branch2_ops, |
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}, |
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}, |
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}; |
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static struct clk_branch lcc_q6ss_ahbm_cbc_clk = { |
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.halt_reg = 0x22004, |
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.halt_check = BRANCH_VOTED, |
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.clkr = { |
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.enable_reg = 0x22004, |
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.enable_mask = BIT(0), |
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.hw.init = &(struct clk_init_data){ |
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.name = "lcc_q6ss_ahbm_cbc_clk", |
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.ops = &clk_branch2_ops, |
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}, |
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}, |
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}; |
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static struct clk_branch lcc_q6ss_axim_cbc_clk = { |
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.halt_reg = 0x1c004, |
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.halt_check = BRANCH_VOTED, |
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.clkr = { |
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.enable_reg = 0x1c004, |
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.enable_mask = BIT(0), |
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.hw.init = &(struct clk_init_data){ |
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.name = "lcc_q6ss_axim_cbc_clk", |
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.ops = &clk_branch2_ops, |
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}, |
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}, |
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}; |
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static struct clk_branch lcc_q6ss_bcr_sleep_clk = { |
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.halt_reg = 0x6004, |
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.halt_check = BRANCH_VOTED, |
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.clkr = { |
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.enable_reg = 0x6004, |
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.enable_mask = BIT(0), |
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.hw.init = &(struct clk_init_data){ |
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.name = "lcc_q6ss_bcr_sleep_clk", |
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.ops = &clk_branch2_ops, |
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}, |
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}, |
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}; |
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/* TCSR clock */ |
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static struct clk_branch tcsr_lcc_csr_cbcr_clk = { |
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.halt_reg = 0x8008, |
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.halt_check = BRANCH_VOTED, |
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.clkr = { |
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.enable_reg = 0x8008, |
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.enable_mask = BIT(0), |
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.hw.init = &(struct clk_init_data){ |
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.name = "tcsr_lcc_csr_cbcr_clk", |
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.ops = &clk_branch2_ops, |
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}, |
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}, |
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}; |
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static struct regmap_config q6sstop_regmap_config = { |
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.reg_bits = 32, |
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.reg_stride = 4, |
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.val_bits = 32, |
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.fast_io = true, |
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}; |
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static struct clk_regmap *q6sstop_qcs404_clocks[] = { |
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[LCC_AHBFABRIC_CBC_CLK] = &lcc_ahbfabric_cbc_clk.clkr, |
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[LCC_Q6SS_AHBS_CBC_CLK] = &lcc_q6ss_ahbs_cbc_clk.clkr, |
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[LCC_Q6SS_TCM_SLAVE_CBC_CLK] = &lcc_q6ss_tcm_slave_cbc_clk.clkr, |
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[LCC_Q6SS_AHBM_CBC_CLK] = &lcc_q6ss_ahbm_cbc_clk.clkr, |
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[LCC_Q6SS_AXIM_CBC_CLK] = &lcc_q6ss_axim_cbc_clk.clkr, |
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[LCC_Q6SS_BCR_SLEEP_CLK] = &lcc_q6ss_bcr_sleep_clk.clkr, |
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}; |
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static const struct qcom_reset_map q6sstop_qcs404_resets[] = { |
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[Q6SSTOP_BCR_RESET] = { 0x6000 }, |
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}; |
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static const struct qcom_cc_desc q6sstop_qcs404_desc = { |
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.config = &q6sstop_regmap_config, |
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.clks = q6sstop_qcs404_clocks, |
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.num_clks = ARRAY_SIZE(q6sstop_qcs404_clocks), |
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.resets = q6sstop_qcs404_resets, |
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.num_resets = ARRAY_SIZE(q6sstop_qcs404_resets), |
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}; |
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static struct clk_regmap *tcsr_qcs404_clocks[] = { |
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[TCSR_Q6SS_LCC_CBCR_CLK] = &tcsr_lcc_csr_cbcr_clk.clkr, |
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}; |
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static const struct qcom_cc_desc tcsr_qcs404_desc = { |
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.config = &q6sstop_regmap_config, |
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.clks = tcsr_qcs404_clocks, |
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.num_clks = ARRAY_SIZE(tcsr_qcs404_clocks), |
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}; |
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static const struct of_device_id q6sstopcc_qcs404_match_table[] = { |
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{ .compatible = "qcom,qcs404-q6sstopcc" }, |
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{ } |
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}; |
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MODULE_DEVICE_TABLE(of, q6sstopcc_qcs404_match_table); |
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static int q6sstopcc_qcs404_probe(struct platform_device *pdev) |
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{ |
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const struct qcom_cc_desc *desc; |
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int ret; |
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pm_runtime_enable(&pdev->dev); |
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ret = pm_clk_create(&pdev->dev); |
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if (ret) |
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goto disable_pm_runtime; |
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ret = pm_clk_add(&pdev->dev, NULL); |
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if (ret < 0) { |
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dev_err(&pdev->dev, "failed to acquire iface clock\n"); |
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goto destroy_pm_clk; |
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} |
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q6sstop_regmap_config.name = "q6sstop_tcsr"; |
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desc = &tcsr_qcs404_desc; |
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ret = qcom_cc_probe_by_index(pdev, 1, desc); |
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if (ret) |
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goto destroy_pm_clk; |
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q6sstop_regmap_config.name = "q6sstop_cc"; |
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desc = &q6sstop_qcs404_desc; |
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ret = qcom_cc_probe_by_index(pdev, 0, desc); |
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if (ret) |
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goto destroy_pm_clk; |
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return 0; |
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destroy_pm_clk: |
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pm_clk_destroy(&pdev->dev); |
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disable_pm_runtime: |
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pm_runtime_disable(&pdev->dev); |
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return ret; |
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} |
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static int q6sstopcc_qcs404_remove(struct platform_device *pdev) |
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{ |
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pm_clk_destroy(&pdev->dev); |
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pm_runtime_disable(&pdev->dev); |
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return 0; |
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} |
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static const struct dev_pm_ops q6sstopcc_pm_ops = { |
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SET_RUNTIME_PM_OPS(pm_clk_suspend, pm_clk_resume, NULL) |
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}; |
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static struct platform_driver q6sstopcc_qcs404_driver = { |
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.probe = q6sstopcc_qcs404_probe, |
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.remove = q6sstopcc_qcs404_remove, |
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.driver = { |
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.name = "qcs404-q6sstopcc", |
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.of_match_table = q6sstopcc_qcs404_match_table, |
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.pm = &q6sstopcc_pm_ops, |
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}, |
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}; |
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module_platform_driver(q6sstopcc_qcs404_driver); |
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MODULE_DESCRIPTION("QTI QCS404 Q6SSTOP Clock Controller Driver"); |
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MODULE_LICENSE("GPL v2");
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