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108 lines
2.5 KiB
108 lines
2.5 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* Qualcomm A53 PLL driver |
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* |
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* Copyright (c) 2017, Linaro Limited |
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* Author: Georgi Djakov <[email protected]> |
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*/ |
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#include <linux/clk-provider.h> |
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#include <linux/kernel.h> |
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#include <linux/platform_device.h> |
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#include <linux/regmap.h> |
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#include <linux/module.h> |
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#include "clk-pll.h" |
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#include "clk-regmap.h" |
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static const struct pll_freq_tbl a53pll_freq[] = { |
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{ 998400000, 52, 0x0, 0x1, 0 }, |
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{ 1094400000, 57, 0x0, 0x1, 0 }, |
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{ 1152000000, 62, 0x0, 0x1, 0 }, |
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{ 1209600000, 63, 0x0, 0x1, 0 }, |
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{ 1248000000, 65, 0x0, 0x1, 0 }, |
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{ 1363200000, 71, 0x0, 0x1, 0 }, |
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{ 1401600000, 73, 0x0, 0x1, 0 }, |
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{ } |
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}; |
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static const struct regmap_config a53pll_regmap_config = { |
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.reg_bits = 32, |
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.reg_stride = 4, |
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.val_bits = 32, |
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.max_register = 0x40, |
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.fast_io = true, |
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}; |
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static int qcom_a53pll_probe(struct platform_device *pdev) |
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{ |
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struct device *dev = &pdev->dev; |
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struct regmap *regmap; |
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struct resource *res; |
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struct clk_pll *pll; |
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void __iomem *base; |
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struct clk_init_data init = { }; |
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int ret; |
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pll = devm_kzalloc(dev, sizeof(*pll), GFP_KERNEL); |
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if (!pll) |
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return -ENOMEM; |
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
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base = devm_ioremap_resource(dev, res); |
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if (IS_ERR(base)) |
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return PTR_ERR(base); |
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regmap = devm_regmap_init_mmio(dev, base, &a53pll_regmap_config); |
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if (IS_ERR(regmap)) |
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return PTR_ERR(regmap); |
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pll->l_reg = 0x04; |
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pll->m_reg = 0x08; |
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pll->n_reg = 0x0c; |
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pll->config_reg = 0x14; |
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pll->mode_reg = 0x00; |
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pll->status_reg = 0x1c; |
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pll->status_bit = 16; |
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pll->freq_tbl = a53pll_freq; |
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init.name = "a53pll"; |
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init.parent_names = (const char *[]){ "xo" }; |
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init.num_parents = 1; |
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init.ops = &clk_pll_sr2_ops; |
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init.flags = CLK_IS_CRITICAL; |
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pll->clkr.hw.init = &init; |
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ret = devm_clk_register_regmap(dev, &pll->clkr); |
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if (ret) { |
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dev_err(dev, "failed to register regmap clock: %d\n", ret); |
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return ret; |
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} |
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ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, |
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&pll->clkr.hw); |
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if (ret) { |
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dev_err(dev, "failed to add clock provider: %d\n", ret); |
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return ret; |
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} |
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return 0; |
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} |
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static const struct of_device_id qcom_a53pll_match_table[] = { |
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{ .compatible = "qcom,msm8916-a53pll" }, |
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{ } |
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}; |
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MODULE_DEVICE_TABLE(of, qcom_a53pll_match_table); |
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static struct platform_driver qcom_a53pll_driver = { |
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.probe = qcom_a53pll_probe, |
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.driver = { |
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.name = "qcom-a53pll", |
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.of_match_table = qcom_a53pll_match_table, |
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}, |
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}; |
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module_platform_driver(qcom_a53pll_driver); |
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MODULE_DESCRIPTION("Qualcomm A53 PLL Driver"); |
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MODULE_LICENSE("GPL v2");
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