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278 lines
6.1 KiB
278 lines
6.1 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* Marvell Orion SoC clocks |
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* |
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* Copyright (C) 2014 Thomas Petazzoni |
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* |
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* Thomas Petazzoni <[email protected]> |
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* |
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*/ |
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#include <linux/kernel.h> |
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#include <linux/clk-provider.h> |
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#include <linux/io.h> |
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#include <linux/of.h> |
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#include "common.h" |
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static const struct coreclk_ratio orion_coreclk_ratios[] __initconst = { |
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{ .id = 0, .name = "ddrclk", } |
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}; |
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/* |
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* Orion 5181 |
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*/ |
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#define SAR_MV88F5181_TCLK_FREQ 8 |
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#define SAR_MV88F5181_TCLK_FREQ_MASK 0x3 |
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static u32 __init mv88f5181_get_tclk_freq(void __iomem *sar) |
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{ |
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u32 opt = (readl(sar) >> SAR_MV88F5181_TCLK_FREQ) & |
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SAR_MV88F5181_TCLK_FREQ_MASK; |
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if (opt == 0) |
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return 133333333; |
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else if (opt == 1) |
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return 150000000; |
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else if (opt == 2) |
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return 166666667; |
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else |
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return 0; |
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} |
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#define SAR_MV88F5181_CPU_FREQ 4 |
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#define SAR_MV88F5181_CPU_FREQ_MASK 0xf |
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static u32 __init mv88f5181_get_cpu_freq(void __iomem *sar) |
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{ |
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u32 opt = (readl(sar) >> SAR_MV88F5181_CPU_FREQ) & |
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SAR_MV88F5181_CPU_FREQ_MASK; |
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if (opt == 0) |
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return 333333333; |
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else if (opt == 1 || opt == 2) |
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return 400000000; |
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else if (opt == 3) |
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return 500000000; |
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else |
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return 0; |
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} |
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static void __init mv88f5181_get_clk_ratio(void __iomem *sar, int id, |
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int *mult, int *div) |
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{ |
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u32 opt = (readl(sar) >> SAR_MV88F5181_CPU_FREQ) & |
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SAR_MV88F5181_CPU_FREQ_MASK; |
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if (opt == 0 || opt == 1) { |
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*mult = 1; |
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*div = 2; |
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} else if (opt == 2 || opt == 3) { |
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*mult = 1; |
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*div = 3; |
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} else { |
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*mult = 0; |
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*div = 1; |
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} |
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} |
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static const struct coreclk_soc_desc mv88f5181_coreclks = { |
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.get_tclk_freq = mv88f5181_get_tclk_freq, |
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.get_cpu_freq = mv88f5181_get_cpu_freq, |
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.get_clk_ratio = mv88f5181_get_clk_ratio, |
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.ratios = orion_coreclk_ratios, |
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.num_ratios = ARRAY_SIZE(orion_coreclk_ratios), |
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}; |
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static void __init mv88f5181_clk_init(struct device_node *np) |
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{ |
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return mvebu_coreclk_setup(np, &mv88f5181_coreclks); |
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} |
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CLK_OF_DECLARE(mv88f5181_clk, "marvell,mv88f5181-core-clock", mv88f5181_clk_init); |
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/* |
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* Orion 5182 |
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*/ |
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#define SAR_MV88F5182_TCLK_FREQ 8 |
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#define SAR_MV88F5182_TCLK_FREQ_MASK 0x3 |
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static u32 __init mv88f5182_get_tclk_freq(void __iomem *sar) |
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{ |
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u32 opt = (readl(sar) >> SAR_MV88F5182_TCLK_FREQ) & |
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SAR_MV88F5182_TCLK_FREQ_MASK; |
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if (opt == 1) |
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return 150000000; |
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else if (opt == 2) |
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return 166666667; |
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else |
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return 0; |
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} |
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#define SAR_MV88F5182_CPU_FREQ 4 |
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#define SAR_MV88F5182_CPU_FREQ_MASK 0xf |
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static u32 __init mv88f5182_get_cpu_freq(void __iomem *sar) |
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{ |
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u32 opt = (readl(sar) >> SAR_MV88F5182_CPU_FREQ) & |
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SAR_MV88F5182_CPU_FREQ_MASK; |
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if (opt == 0) |
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return 333333333; |
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else if (opt == 1 || opt == 2) |
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return 400000000; |
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else if (opt == 3) |
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return 500000000; |
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else |
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return 0; |
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} |
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static void __init mv88f5182_get_clk_ratio(void __iomem *sar, int id, |
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int *mult, int *div) |
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{ |
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u32 opt = (readl(sar) >> SAR_MV88F5182_CPU_FREQ) & |
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SAR_MV88F5182_CPU_FREQ_MASK; |
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if (opt == 0 || opt == 1) { |
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*mult = 1; |
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*div = 2; |
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} else if (opt == 2 || opt == 3) { |
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*mult = 1; |
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*div = 3; |
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} else { |
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*mult = 0; |
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*div = 1; |
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} |
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} |
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static const struct coreclk_soc_desc mv88f5182_coreclks = { |
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.get_tclk_freq = mv88f5182_get_tclk_freq, |
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.get_cpu_freq = mv88f5182_get_cpu_freq, |
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.get_clk_ratio = mv88f5182_get_clk_ratio, |
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.ratios = orion_coreclk_ratios, |
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.num_ratios = ARRAY_SIZE(orion_coreclk_ratios), |
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}; |
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static void __init mv88f5182_clk_init(struct device_node *np) |
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{ |
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return mvebu_coreclk_setup(np, &mv88f5182_coreclks); |
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} |
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CLK_OF_DECLARE(mv88f5182_clk, "marvell,mv88f5182-core-clock", mv88f5182_clk_init); |
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/* |
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* Orion 5281 |
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*/ |
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static u32 __init mv88f5281_get_tclk_freq(void __iomem *sar) |
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{ |
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/* On 5281, tclk is always 166 Mhz */ |
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return 166666667; |
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} |
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#define SAR_MV88F5281_CPU_FREQ 4 |
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#define SAR_MV88F5281_CPU_FREQ_MASK 0xf |
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static u32 __init mv88f5281_get_cpu_freq(void __iomem *sar) |
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{ |
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u32 opt = (readl(sar) >> SAR_MV88F5281_CPU_FREQ) & |
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SAR_MV88F5281_CPU_FREQ_MASK; |
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if (opt == 1 || opt == 2) |
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return 400000000; |
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else if (opt == 3) |
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return 500000000; |
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else |
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return 0; |
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} |
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static void __init mv88f5281_get_clk_ratio(void __iomem *sar, int id, |
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int *mult, int *div) |
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{ |
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u32 opt = (readl(sar) >> SAR_MV88F5281_CPU_FREQ) & |
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SAR_MV88F5281_CPU_FREQ_MASK; |
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if (opt == 1) { |
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*mult = 1; |
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*div = 2; |
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} else if (opt == 2 || opt == 3) { |
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*mult = 1; |
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*div = 3; |
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} else { |
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*mult = 0; |
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*div = 1; |
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} |
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} |
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static const struct coreclk_soc_desc mv88f5281_coreclks = { |
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.get_tclk_freq = mv88f5281_get_tclk_freq, |
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.get_cpu_freq = mv88f5281_get_cpu_freq, |
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.get_clk_ratio = mv88f5281_get_clk_ratio, |
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.ratios = orion_coreclk_ratios, |
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.num_ratios = ARRAY_SIZE(orion_coreclk_ratios), |
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}; |
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static void __init mv88f5281_clk_init(struct device_node *np) |
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{ |
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return mvebu_coreclk_setup(np, &mv88f5281_coreclks); |
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} |
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CLK_OF_DECLARE(mv88f5281_clk, "marvell,mv88f5281-core-clock", mv88f5281_clk_init); |
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/* |
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* Orion 6183 |
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*/ |
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#define SAR_MV88F6183_TCLK_FREQ 9 |
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#define SAR_MV88F6183_TCLK_FREQ_MASK 0x1 |
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static u32 __init mv88f6183_get_tclk_freq(void __iomem *sar) |
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{ |
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u32 opt = (readl(sar) >> SAR_MV88F6183_TCLK_FREQ) & |
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SAR_MV88F6183_TCLK_FREQ_MASK; |
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if (opt == 0) |
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return 133333333; |
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else if (opt == 1) |
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return 166666667; |
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else |
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return 0; |
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} |
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#define SAR_MV88F6183_CPU_FREQ 1 |
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#define SAR_MV88F6183_CPU_FREQ_MASK 0x3f |
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static u32 __init mv88f6183_get_cpu_freq(void __iomem *sar) |
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{ |
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u32 opt = (readl(sar) >> SAR_MV88F6183_CPU_FREQ) & |
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SAR_MV88F6183_CPU_FREQ_MASK; |
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if (opt == 9) |
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return 333333333; |
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else if (opt == 17) |
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return 400000000; |
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else |
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return 0; |
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} |
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static void __init mv88f6183_get_clk_ratio(void __iomem *sar, int id, |
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int *mult, int *div) |
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{ |
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u32 opt = (readl(sar) >> SAR_MV88F6183_CPU_FREQ) & |
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SAR_MV88F6183_CPU_FREQ_MASK; |
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if (opt == 9 || opt == 17) { |
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*mult = 1; |
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*div = 2; |
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} else { |
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*mult = 0; |
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*div = 1; |
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} |
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} |
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static const struct coreclk_soc_desc mv88f6183_coreclks = { |
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.get_tclk_freq = mv88f6183_get_tclk_freq, |
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.get_cpu_freq = mv88f6183_get_cpu_freq, |
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.get_clk_ratio = mv88f6183_get_clk_ratio, |
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.ratios = orion_coreclk_ratios, |
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.num_ratios = ARRAY_SIZE(orion_coreclk_ratios), |
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}; |
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static void __init mv88f6183_clk_init(struct device_node *np) |
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{ |
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return mvebu_coreclk_setup(np, &mv88f6183_coreclks); |
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} |
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CLK_OF_DECLARE(mv88f6183_clk, "marvell,mv88f6183-core-clock", mv88f6183_clk_init);
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