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817 lines
23 KiB
817 lines
23 KiB
// SPDX-License-Identifier: GPL-2.0-or-later |
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// Copyright IBM Corp |
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// Copyright ASPEED Technology |
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#define pr_fmt(fmt) "clk-ast2600: " fmt |
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#include <linux/mfd/syscon.h> |
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#include <linux/of_address.h> |
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#include <linux/of_device.h> |
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#include <linux/platform_device.h> |
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#include <linux/regmap.h> |
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#include <linux/slab.h> |
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#include <dt-bindings/clock/ast2600-clock.h> |
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#include "clk-aspeed.h" |
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#define ASPEED_G6_NUM_CLKS 71 |
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#define ASPEED_G6_SILICON_REV 0x014 |
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#define CHIP_REVISION_ID GENMASK(23, 16) |
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#define ASPEED_G6_RESET_CTRL 0x040 |
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#define ASPEED_G6_RESET_CTRL2 0x050 |
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#define ASPEED_G6_CLK_STOP_CTRL 0x080 |
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#define ASPEED_G6_CLK_STOP_CTRL2 0x090 |
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#define ASPEED_G6_MISC_CTRL 0x0C0 |
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#define UART_DIV13_EN BIT(12) |
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#define ASPEED_G6_CLK_SELECTION1 0x300 |
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#define ASPEED_G6_CLK_SELECTION2 0x304 |
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#define ASPEED_G6_CLK_SELECTION4 0x310 |
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#define ASPEED_HPLL_PARAM 0x200 |
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#define ASPEED_APLL_PARAM 0x210 |
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#define ASPEED_MPLL_PARAM 0x220 |
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#define ASPEED_EPLL_PARAM 0x240 |
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#define ASPEED_DPLL_PARAM 0x260 |
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#define ASPEED_G6_STRAP1 0x500 |
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#define ASPEED_MAC12_CLK_DLY 0x340 |
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#define ASPEED_MAC34_CLK_DLY 0x350 |
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/* Globally visible clocks */ |
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static DEFINE_SPINLOCK(aspeed_g6_clk_lock); |
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/* Keeps track of all clocks */ |
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static struct clk_hw_onecell_data *aspeed_g6_clk_data; |
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static void __iomem *scu_g6_base; |
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/* |
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* Clocks marked with CLK_IS_CRITICAL: |
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* |
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* ref0 and ref1 are essential for the SoC to operate |
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* mpll is required if SDRAM is used |
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*/ |
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static const struct aspeed_gate_data aspeed_g6_gates[] = { |
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/* clk rst name parent flags */ |
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[ASPEED_CLK_GATE_MCLK] = { 0, -1, "mclk-gate", "mpll", CLK_IS_CRITICAL }, /* SDRAM */ |
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[ASPEED_CLK_GATE_ECLK] = { 1, 6, "eclk-gate", "eclk", 0 }, /* Video Engine */ |
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[ASPEED_CLK_GATE_GCLK] = { 2, 7, "gclk-gate", NULL, 0 }, /* 2D engine */ |
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/* vclk parent - dclk/d1clk/hclk/mclk */ |
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[ASPEED_CLK_GATE_VCLK] = { 3, -1, "vclk-gate", NULL, 0 }, /* Video Capture */ |
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[ASPEED_CLK_GATE_BCLK] = { 4, 8, "bclk-gate", "bclk", 0 }, /* PCIe/PCI */ |
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/* From dpll */ |
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[ASPEED_CLK_GATE_DCLK] = { 5, -1, "dclk-gate", NULL, CLK_IS_CRITICAL }, /* DAC */ |
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[ASPEED_CLK_GATE_REF0CLK] = { 6, -1, "ref0clk-gate", "clkin", CLK_IS_CRITICAL }, |
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[ASPEED_CLK_GATE_USBPORT2CLK] = { 7, 3, "usb-port2-gate", NULL, 0 }, /* USB2.0 Host port 2 */ |
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/* Reserved 8 */ |
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[ASPEED_CLK_GATE_USBUHCICLK] = { 9, 15, "usb-uhci-gate", NULL, 0 }, /* USB1.1 (requires port 2 enabled) */ |
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/* From dpll/epll/40mhz usb p1 phy/gpioc6/dp phy pll */ |
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[ASPEED_CLK_GATE_D1CLK] = { 10, 13, "d1clk-gate", "d1clk", 0 }, /* GFX CRT */ |
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/* Reserved 11/12 */ |
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[ASPEED_CLK_GATE_YCLK] = { 13, 4, "yclk-gate", NULL, 0 }, /* HAC */ |
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[ASPEED_CLK_GATE_USBPORT1CLK] = { 14, 14, "usb-port1-gate", NULL, 0 }, /* USB2 hub/USB2 host port 1/USB1.1 dev */ |
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[ASPEED_CLK_GATE_UART5CLK] = { 15, -1, "uart5clk-gate", "uart", 0 }, /* UART5 */ |
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/* Reserved 16/19 */ |
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[ASPEED_CLK_GATE_MAC1CLK] = { 20, 11, "mac1clk-gate", "mac12", 0 }, /* MAC1 */ |
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[ASPEED_CLK_GATE_MAC2CLK] = { 21, 12, "mac2clk-gate", "mac12", 0 }, /* MAC2 */ |
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/* Reserved 22/23 */ |
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[ASPEED_CLK_GATE_RSACLK] = { 24, 4, "rsaclk-gate", NULL, 0 }, /* HAC */ |
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[ASPEED_CLK_GATE_RVASCLK] = { 25, 9, "rvasclk-gate", NULL, 0 }, /* RVAS */ |
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/* Reserved 26 */ |
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[ASPEED_CLK_GATE_EMMCCLK] = { 27, 16, "emmcclk-gate", NULL, 0 }, /* For card clk */ |
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/* Reserved 28/29/30 */ |
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[ASPEED_CLK_GATE_LCLK] = { 32, 32, "lclk-gate", NULL, 0 }, /* LPC */ |
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[ASPEED_CLK_GATE_ESPICLK] = { 33, -1, "espiclk-gate", NULL, 0 }, /* eSPI */ |
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[ASPEED_CLK_GATE_REF1CLK] = { 34, -1, "ref1clk-gate", "clkin", CLK_IS_CRITICAL }, |
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/* Reserved 35 */ |
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[ASPEED_CLK_GATE_SDCLK] = { 36, 56, "sdclk-gate", NULL, 0 }, /* SDIO/SD */ |
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[ASPEED_CLK_GATE_LHCCLK] = { 37, -1, "lhclk-gate", "lhclk", 0 }, /* LPC master/LPC+ */ |
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/* Reserved 38 RSA: no longer used */ |
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/* Reserved 39 */ |
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[ASPEED_CLK_GATE_I3C0CLK] = { 40, 40, "i3c0clk-gate", NULL, 0 }, /* I3C0 */ |
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[ASPEED_CLK_GATE_I3C1CLK] = { 41, 41, "i3c1clk-gate", NULL, 0 }, /* I3C1 */ |
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[ASPEED_CLK_GATE_I3C2CLK] = { 42, 42, "i3c2clk-gate", NULL, 0 }, /* I3C2 */ |
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[ASPEED_CLK_GATE_I3C3CLK] = { 43, 43, "i3c3clk-gate", NULL, 0 }, /* I3C3 */ |
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[ASPEED_CLK_GATE_I3C4CLK] = { 44, 44, "i3c4clk-gate", NULL, 0 }, /* I3C4 */ |
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[ASPEED_CLK_GATE_I3C5CLK] = { 45, 45, "i3c5clk-gate", NULL, 0 }, /* I3C5 */ |
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[ASPEED_CLK_GATE_I3C6CLK] = { 46, 46, "i3c6clk-gate", NULL, 0 }, /* I3C6 */ |
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[ASPEED_CLK_GATE_I3C7CLK] = { 47, 47, "i3c7clk-gate", NULL, 0 }, /* I3C7 */ |
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[ASPEED_CLK_GATE_UART1CLK] = { 48, -1, "uart1clk-gate", "uart", 0 }, /* UART1 */ |
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[ASPEED_CLK_GATE_UART2CLK] = { 49, -1, "uart2clk-gate", "uart", 0 }, /* UART2 */ |
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[ASPEED_CLK_GATE_UART3CLK] = { 50, -1, "uart3clk-gate", "uart", 0 }, /* UART3 */ |
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[ASPEED_CLK_GATE_UART4CLK] = { 51, -1, "uart4clk-gate", "uart", 0 }, /* UART4 */ |
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[ASPEED_CLK_GATE_MAC3CLK] = { 52, 52, "mac3clk-gate", "mac34", 0 }, /* MAC3 */ |
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[ASPEED_CLK_GATE_MAC4CLK] = { 53, 53, "mac4clk-gate", "mac34", 0 }, /* MAC4 */ |
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[ASPEED_CLK_GATE_UART6CLK] = { 54, -1, "uart6clk-gate", "uartx", 0 }, /* UART6 */ |
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[ASPEED_CLK_GATE_UART7CLK] = { 55, -1, "uart7clk-gate", "uartx", 0 }, /* UART7 */ |
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[ASPEED_CLK_GATE_UART8CLK] = { 56, -1, "uart8clk-gate", "uartx", 0 }, /* UART8 */ |
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[ASPEED_CLK_GATE_UART9CLK] = { 57, -1, "uart9clk-gate", "uartx", 0 }, /* UART9 */ |
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[ASPEED_CLK_GATE_UART10CLK] = { 58, -1, "uart10clk-gate", "uartx", 0 }, /* UART10 */ |
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[ASPEED_CLK_GATE_UART11CLK] = { 59, -1, "uart11clk-gate", "uartx", 0 }, /* UART11 */ |
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[ASPEED_CLK_GATE_UART12CLK] = { 60, -1, "uart12clk-gate", "uartx", 0 }, /* UART12 */ |
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[ASPEED_CLK_GATE_UART13CLK] = { 61, -1, "uart13clk-gate", "uartx", 0 }, /* UART13 */ |
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[ASPEED_CLK_GATE_FSICLK] = { 62, 59, "fsiclk-gate", NULL, 0 }, /* FSI */ |
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}; |
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static const struct clk_div_table ast2600_eclk_div_table[] = { |
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{ 0x0, 2 }, |
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{ 0x1, 2 }, |
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{ 0x2, 3 }, |
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{ 0x3, 4 }, |
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{ 0x4, 5 }, |
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{ 0x5, 6 }, |
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{ 0x6, 7 }, |
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{ 0x7, 8 }, |
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{ 0 } |
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}; |
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static const struct clk_div_table ast2600_emmc_extclk_div_table[] = { |
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{ 0x0, 2 }, |
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{ 0x1, 4 }, |
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{ 0x2, 6 }, |
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{ 0x3, 8 }, |
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{ 0x4, 10 }, |
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{ 0x5, 12 }, |
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{ 0x6, 14 }, |
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{ 0x7, 16 }, |
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{ 0 } |
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}; |
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static const struct clk_div_table ast2600_mac_div_table[] = { |
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{ 0x0, 4 }, |
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{ 0x1, 4 }, |
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{ 0x2, 6 }, |
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{ 0x3, 8 }, |
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{ 0x4, 10 }, |
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{ 0x5, 12 }, |
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{ 0x6, 14 }, |
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{ 0x7, 16 }, |
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{ 0 } |
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}; |
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static const struct clk_div_table ast2600_div_table[] = { |
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{ 0x0, 4 }, |
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{ 0x1, 8 }, |
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{ 0x2, 12 }, |
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{ 0x3, 16 }, |
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{ 0x4, 20 }, |
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{ 0x5, 24 }, |
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{ 0x6, 28 }, |
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{ 0x7, 32 }, |
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{ 0 } |
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}; |
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/* For hpll/dpll/epll/mpll */ |
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static struct clk_hw *ast2600_calc_pll(const char *name, u32 val) |
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{ |
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unsigned int mult, div; |
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if (val & BIT(24)) { |
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/* Pass through mode */ |
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mult = div = 1; |
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} else { |
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/* F = 25Mhz * [(M + 2) / (n + 1)] / (p + 1) */ |
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u32 m = val & 0x1fff; |
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u32 n = (val >> 13) & 0x3f; |
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u32 p = (val >> 19) & 0xf; |
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mult = (m + 1) / (n + 1); |
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div = (p + 1); |
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} |
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return clk_hw_register_fixed_factor(NULL, name, "clkin", 0, |
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mult, div); |
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}; |
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static struct clk_hw *ast2600_calc_apll(const char *name, u32 val) |
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{ |
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unsigned int mult, div; |
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u32 chip_id = readl(scu_g6_base + ASPEED_G6_SILICON_REV); |
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if (((chip_id & CHIP_REVISION_ID) >> 16) >= 2) { |
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if (val & BIT(24)) { |
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/* Pass through mode */ |
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mult = div = 1; |
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} else { |
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/* F = 25Mhz * [(m + 1) / (n + 1)] / (p + 1) */ |
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u32 m = val & 0x1fff; |
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u32 n = (val >> 13) & 0x3f; |
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u32 p = (val >> 19) & 0xf; |
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mult = (m + 1); |
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div = (n + 1) * (p + 1); |
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} |
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} else { |
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if (val & BIT(20)) { |
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/* Pass through mode */ |
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mult = div = 1; |
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} else { |
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/* F = 25Mhz * (2-od) * [(m + 2) / (n + 1)] */ |
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u32 m = (val >> 5) & 0x3f; |
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u32 od = (val >> 4) & 0x1; |
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u32 n = val & 0xf; |
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mult = (2 - od) * (m + 2); |
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div = n + 1; |
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} |
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} |
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return clk_hw_register_fixed_factor(NULL, name, "clkin", 0, |
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mult, div); |
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}; |
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static u32 get_bit(u8 idx) |
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{ |
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return BIT(idx % 32); |
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} |
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static u32 get_reset_reg(struct aspeed_clk_gate *gate) |
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{ |
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if (gate->reset_idx < 32) |
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return ASPEED_G6_RESET_CTRL; |
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return ASPEED_G6_RESET_CTRL2; |
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} |
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static u32 get_clock_reg(struct aspeed_clk_gate *gate) |
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{ |
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if (gate->clock_idx < 32) |
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return ASPEED_G6_CLK_STOP_CTRL; |
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return ASPEED_G6_CLK_STOP_CTRL2; |
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} |
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static int aspeed_g6_clk_is_enabled(struct clk_hw *hw) |
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{ |
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struct aspeed_clk_gate *gate = to_aspeed_clk_gate(hw); |
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u32 clk = get_bit(gate->clock_idx); |
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u32 rst = get_bit(gate->reset_idx); |
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u32 reg; |
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u32 enval; |
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/* |
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* If the IP is in reset, treat the clock as not enabled, |
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* this happens with some clocks such as the USB one when |
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* coming from cold reset. Without this, aspeed_clk_enable() |
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* will fail to lift the reset. |
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*/ |
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if (gate->reset_idx >= 0) { |
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regmap_read(gate->map, get_reset_reg(gate), ®); |
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if (reg & rst) |
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return 0; |
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} |
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regmap_read(gate->map, get_clock_reg(gate), ®); |
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enval = (gate->flags & CLK_GATE_SET_TO_DISABLE) ? 0 : clk; |
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return ((reg & clk) == enval) ? 1 : 0; |
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} |
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static int aspeed_g6_clk_enable(struct clk_hw *hw) |
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{ |
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struct aspeed_clk_gate *gate = to_aspeed_clk_gate(hw); |
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unsigned long flags; |
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u32 clk = get_bit(gate->clock_idx); |
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u32 rst = get_bit(gate->reset_idx); |
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spin_lock_irqsave(gate->lock, flags); |
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if (aspeed_g6_clk_is_enabled(hw)) { |
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spin_unlock_irqrestore(gate->lock, flags); |
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return 0; |
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} |
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if (gate->reset_idx >= 0) { |
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/* Put IP in reset */ |
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regmap_write(gate->map, get_reset_reg(gate), rst); |
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/* Delay 100us */ |
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udelay(100); |
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} |
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/* Enable clock */ |
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if (gate->flags & CLK_GATE_SET_TO_DISABLE) { |
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/* Clock is clear to enable, so use set to clear register */ |
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regmap_write(gate->map, get_clock_reg(gate) + 0x04, clk); |
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} else { |
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/* Clock is set to enable, so use write to set register */ |
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regmap_write(gate->map, get_clock_reg(gate), clk); |
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} |
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if (gate->reset_idx >= 0) { |
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/* A delay of 10ms is specified by the ASPEED docs */ |
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mdelay(10); |
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/* Take IP out of reset */ |
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regmap_write(gate->map, get_reset_reg(gate) + 0x4, rst); |
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} |
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spin_unlock_irqrestore(gate->lock, flags); |
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return 0; |
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} |
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static void aspeed_g6_clk_disable(struct clk_hw *hw) |
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{ |
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struct aspeed_clk_gate *gate = to_aspeed_clk_gate(hw); |
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unsigned long flags; |
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u32 clk = get_bit(gate->clock_idx); |
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spin_lock_irqsave(gate->lock, flags); |
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if (gate->flags & CLK_GATE_SET_TO_DISABLE) { |
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regmap_write(gate->map, get_clock_reg(gate), clk); |
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} else { |
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/* Use set to clear register */ |
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regmap_write(gate->map, get_clock_reg(gate) + 0x4, clk); |
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} |
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spin_unlock_irqrestore(gate->lock, flags); |
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} |
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static const struct clk_ops aspeed_g6_clk_gate_ops = { |
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.enable = aspeed_g6_clk_enable, |
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.disable = aspeed_g6_clk_disable, |
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.is_enabled = aspeed_g6_clk_is_enabled, |
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}; |
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static int aspeed_g6_reset_deassert(struct reset_controller_dev *rcdev, |
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unsigned long id) |
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{ |
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struct aspeed_reset *ar = to_aspeed_reset(rcdev); |
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u32 rst = get_bit(id); |
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u32 reg = id >= 32 ? ASPEED_G6_RESET_CTRL2 : ASPEED_G6_RESET_CTRL; |
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/* Use set to clear register */ |
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return regmap_write(ar->map, reg + 0x04, rst); |
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} |
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static int aspeed_g6_reset_assert(struct reset_controller_dev *rcdev, |
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unsigned long id) |
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{ |
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struct aspeed_reset *ar = to_aspeed_reset(rcdev); |
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u32 rst = get_bit(id); |
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u32 reg = id >= 32 ? ASPEED_G6_RESET_CTRL2 : ASPEED_G6_RESET_CTRL; |
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return regmap_write(ar->map, reg, rst); |
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} |
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static int aspeed_g6_reset_status(struct reset_controller_dev *rcdev, |
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unsigned long id) |
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{ |
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struct aspeed_reset *ar = to_aspeed_reset(rcdev); |
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int ret; |
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u32 val; |
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u32 rst = get_bit(id); |
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u32 reg = id >= 32 ? ASPEED_G6_RESET_CTRL2 : ASPEED_G6_RESET_CTRL; |
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ret = regmap_read(ar->map, reg, &val); |
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if (ret) |
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return ret; |
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return !!(val & rst); |
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} |
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static const struct reset_control_ops aspeed_g6_reset_ops = { |
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.assert = aspeed_g6_reset_assert, |
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.deassert = aspeed_g6_reset_deassert, |
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.status = aspeed_g6_reset_status, |
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}; |
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static struct clk_hw *aspeed_g6_clk_hw_register_gate(struct device *dev, |
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const char *name, const char *parent_name, unsigned long flags, |
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struct regmap *map, u8 clock_idx, u8 reset_idx, |
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u8 clk_gate_flags, spinlock_t *lock) |
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{ |
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struct aspeed_clk_gate *gate; |
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struct clk_init_data init; |
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struct clk_hw *hw; |
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int ret; |
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gate = kzalloc(sizeof(*gate), GFP_KERNEL); |
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if (!gate) |
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return ERR_PTR(-ENOMEM); |
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init.name = name; |
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init.ops = &aspeed_g6_clk_gate_ops; |
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init.flags = flags; |
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init.parent_names = parent_name ? &parent_name : NULL; |
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init.num_parents = parent_name ? 1 : 0; |
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gate->map = map; |
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gate->clock_idx = clock_idx; |
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gate->reset_idx = reset_idx; |
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gate->flags = clk_gate_flags; |
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gate->lock = lock; |
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gate->hw.init = &init; |
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hw = &gate->hw; |
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ret = clk_hw_register(dev, hw); |
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if (ret) { |
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kfree(gate); |
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hw = ERR_PTR(ret); |
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} |
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return hw; |
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} |
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static const char *const emmc_extclk_parent_names[] = { |
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"emmc_extclk_hpll_in", |
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"mpll", |
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}; |
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static const char * const vclk_parent_names[] = { |
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"dpll", |
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"d1pll", |
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"hclk", |
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"mclk", |
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}; |
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static const char * const d1clk_parent_names[] = { |
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"dpll", |
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"epll", |
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"usb-phy-40m", |
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"gpioc6_clkin", |
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"dp_phy_pll", |
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}; |
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static int aspeed_g6_clk_probe(struct platform_device *pdev) |
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{ |
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struct device *dev = &pdev->dev; |
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struct aspeed_reset *ar; |
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struct regmap *map; |
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struct clk_hw *hw; |
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u32 val, rate; |
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int i, ret; |
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map = syscon_node_to_regmap(dev->of_node); |
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if (IS_ERR(map)) { |
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dev_err(dev, "no syscon regmap\n"); |
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return PTR_ERR(map); |
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} |
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ar = devm_kzalloc(dev, sizeof(*ar), GFP_KERNEL); |
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if (!ar) |
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return -ENOMEM; |
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ar->map = map; |
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ar->rcdev.owner = THIS_MODULE; |
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ar->rcdev.nr_resets = 64; |
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ar->rcdev.ops = &aspeed_g6_reset_ops; |
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ar->rcdev.of_node = dev->of_node; |
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|
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ret = devm_reset_controller_register(dev, &ar->rcdev); |
|
if (ret) { |
|
dev_err(dev, "could not register reset controller\n"); |
|
return ret; |
|
} |
|
|
|
/* UART clock div13 setting */ |
|
regmap_read(map, ASPEED_G6_MISC_CTRL, &val); |
|
if (val & UART_DIV13_EN) |
|
rate = 24000000 / 13; |
|
else |
|
rate = 24000000; |
|
hw = clk_hw_register_fixed_rate(dev, "uart", NULL, 0, rate); |
|
if (IS_ERR(hw)) |
|
return PTR_ERR(hw); |
|
aspeed_g6_clk_data->hws[ASPEED_CLK_UART] = hw; |
|
|
|
/* UART6~13 clock div13 setting */ |
|
regmap_read(map, 0x80, &val); |
|
if (val & BIT(31)) |
|
rate = 24000000 / 13; |
|
else |
|
rate = 24000000; |
|
hw = clk_hw_register_fixed_rate(dev, "uartx", NULL, 0, rate); |
|
if (IS_ERR(hw)) |
|
return PTR_ERR(hw); |
|
aspeed_g6_clk_data->hws[ASPEED_CLK_UARTX] = hw; |
|
|
|
/* EMMC ext clock */ |
|
hw = clk_hw_register_fixed_factor(dev, "emmc_extclk_hpll_in", "hpll", |
|
0, 1, 2); |
|
if (IS_ERR(hw)) |
|
return PTR_ERR(hw); |
|
|
|
hw = clk_hw_register_mux(dev, "emmc_extclk_mux", |
|
emmc_extclk_parent_names, |
|
ARRAY_SIZE(emmc_extclk_parent_names), 0, |
|
scu_g6_base + ASPEED_G6_CLK_SELECTION1, 11, 1, |
|
0, &aspeed_g6_clk_lock); |
|
if (IS_ERR(hw)) |
|
return PTR_ERR(hw); |
|
|
|
hw = clk_hw_register_gate(dev, "emmc_extclk_gate", "emmc_extclk_mux", |
|
0, scu_g6_base + ASPEED_G6_CLK_SELECTION1, |
|
15, 0, &aspeed_g6_clk_lock); |
|
if (IS_ERR(hw)) |
|
return PTR_ERR(hw); |
|
|
|
hw = clk_hw_register_divider_table(dev, "emmc_extclk", |
|
"emmc_extclk_gate", 0, |
|
scu_g6_base + |
|
ASPEED_G6_CLK_SELECTION1, 12, |
|
3, 0, ast2600_emmc_extclk_div_table, |
|
&aspeed_g6_clk_lock); |
|
if (IS_ERR(hw)) |
|
return PTR_ERR(hw); |
|
aspeed_g6_clk_data->hws[ASPEED_CLK_EMMC] = hw; |
|
|
|
/* SD/SDIO clock divider and gate */ |
|
hw = clk_hw_register_gate(dev, "sd_extclk_gate", "hpll", 0, |
|
scu_g6_base + ASPEED_G6_CLK_SELECTION4, 31, 0, |
|
&aspeed_g6_clk_lock); |
|
if (IS_ERR(hw)) |
|
return PTR_ERR(hw); |
|
hw = clk_hw_register_divider_table(dev, "sd_extclk", "sd_extclk_gate", |
|
0, scu_g6_base + ASPEED_G6_CLK_SELECTION4, 28, 3, 0, |
|
ast2600_div_table, |
|
&aspeed_g6_clk_lock); |
|
if (IS_ERR(hw)) |
|
return PTR_ERR(hw); |
|
aspeed_g6_clk_data->hws[ASPEED_CLK_SDIO] = hw; |
|
|
|
/* MAC1/2 RMII 50MHz RCLK */ |
|
hw = clk_hw_register_fixed_rate(dev, "mac12rclk", "hpll", 0, 50000000); |
|
if (IS_ERR(hw)) |
|
return PTR_ERR(hw); |
|
|
|
/* MAC1/2 AHB bus clock divider */ |
|
hw = clk_hw_register_divider_table(dev, "mac12", "hpll", 0, |
|
scu_g6_base + ASPEED_G6_CLK_SELECTION1, 16, 3, 0, |
|
ast2600_mac_div_table, |
|
&aspeed_g6_clk_lock); |
|
if (IS_ERR(hw)) |
|
return PTR_ERR(hw); |
|
aspeed_g6_clk_data->hws[ASPEED_CLK_MAC12] = hw; |
|
|
|
/* RMII1 50MHz (RCLK) output enable */ |
|
hw = clk_hw_register_gate(dev, "mac1rclk", "mac12rclk", 0, |
|
scu_g6_base + ASPEED_MAC12_CLK_DLY, 29, 0, |
|
&aspeed_g6_clk_lock); |
|
if (IS_ERR(hw)) |
|
return PTR_ERR(hw); |
|
aspeed_g6_clk_data->hws[ASPEED_CLK_MAC1RCLK] = hw; |
|
|
|
/* RMII2 50MHz (RCLK) output enable */ |
|
hw = clk_hw_register_gate(dev, "mac2rclk", "mac12rclk", 0, |
|
scu_g6_base + ASPEED_MAC12_CLK_DLY, 30, 0, |
|
&aspeed_g6_clk_lock); |
|
if (IS_ERR(hw)) |
|
return PTR_ERR(hw); |
|
aspeed_g6_clk_data->hws[ASPEED_CLK_MAC2RCLK] = hw; |
|
|
|
/* MAC1/2 RMII 50MHz RCLK */ |
|
hw = clk_hw_register_fixed_rate(dev, "mac34rclk", "hclk", 0, 50000000); |
|
if (IS_ERR(hw)) |
|
return PTR_ERR(hw); |
|
|
|
/* MAC3/4 AHB bus clock divider */ |
|
hw = clk_hw_register_divider_table(dev, "mac34", "hpll", 0, |
|
scu_g6_base + 0x310, 24, 3, 0, |
|
ast2600_mac_div_table, |
|
&aspeed_g6_clk_lock); |
|
if (IS_ERR(hw)) |
|
return PTR_ERR(hw); |
|
aspeed_g6_clk_data->hws[ASPEED_CLK_MAC34] = hw; |
|
|
|
/* RMII3 50MHz (RCLK) output enable */ |
|
hw = clk_hw_register_gate(dev, "mac3rclk", "mac34rclk", 0, |
|
scu_g6_base + ASPEED_MAC34_CLK_DLY, 29, 0, |
|
&aspeed_g6_clk_lock); |
|
if (IS_ERR(hw)) |
|
return PTR_ERR(hw); |
|
aspeed_g6_clk_data->hws[ASPEED_CLK_MAC3RCLK] = hw; |
|
|
|
/* RMII4 50MHz (RCLK) output enable */ |
|
hw = clk_hw_register_gate(dev, "mac4rclk", "mac34rclk", 0, |
|
scu_g6_base + ASPEED_MAC34_CLK_DLY, 30, 0, |
|
&aspeed_g6_clk_lock); |
|
if (IS_ERR(hw)) |
|
return PTR_ERR(hw); |
|
aspeed_g6_clk_data->hws[ASPEED_CLK_MAC4RCLK] = hw; |
|
|
|
/* LPC Host (LHCLK) clock divider */ |
|
hw = clk_hw_register_divider_table(dev, "lhclk", "hpll", 0, |
|
scu_g6_base + ASPEED_G6_CLK_SELECTION1, 20, 3, 0, |
|
ast2600_div_table, |
|
&aspeed_g6_clk_lock); |
|
if (IS_ERR(hw)) |
|
return PTR_ERR(hw); |
|
aspeed_g6_clk_data->hws[ASPEED_CLK_LHCLK] = hw; |
|
|
|
/* gfx d1clk : use dp clk */ |
|
regmap_update_bits(map, ASPEED_G6_CLK_SELECTION1, GENMASK(10, 8), BIT(10)); |
|
/* SoC Display clock selection */ |
|
hw = clk_hw_register_mux(dev, "d1clk", d1clk_parent_names, |
|
ARRAY_SIZE(d1clk_parent_names), 0, |
|
scu_g6_base + ASPEED_G6_CLK_SELECTION1, 8, 3, 0, |
|
&aspeed_g6_clk_lock); |
|
if (IS_ERR(hw)) |
|
return PTR_ERR(hw); |
|
aspeed_g6_clk_data->hws[ASPEED_CLK_D1CLK] = hw; |
|
|
|
/* d1 clk div 0x308[17:15] x [14:12] - 8,7,6,5,4,3,2,1 */ |
|
regmap_write(map, 0x308, 0x12000); /* 3x3 = 9 */ |
|
|
|
/* P-Bus (BCLK) clock divider */ |
|
hw = clk_hw_register_divider_table(dev, "bclk", "hpll", 0, |
|
scu_g6_base + ASPEED_G6_CLK_SELECTION1, 20, 3, 0, |
|
ast2600_div_table, |
|
&aspeed_g6_clk_lock); |
|
if (IS_ERR(hw)) |
|
return PTR_ERR(hw); |
|
aspeed_g6_clk_data->hws[ASPEED_CLK_BCLK] = hw; |
|
|
|
/* Video Capture clock selection */ |
|
hw = clk_hw_register_mux(dev, "vclk", vclk_parent_names, |
|
ARRAY_SIZE(vclk_parent_names), 0, |
|
scu_g6_base + ASPEED_G6_CLK_SELECTION2, 12, 3, 0, |
|
&aspeed_g6_clk_lock); |
|
if (IS_ERR(hw)) |
|
return PTR_ERR(hw); |
|
aspeed_g6_clk_data->hws[ASPEED_CLK_VCLK] = hw; |
|
|
|
/* Video Engine clock divider */ |
|
hw = clk_hw_register_divider_table(dev, "eclk", NULL, 0, |
|
scu_g6_base + ASPEED_G6_CLK_SELECTION1, 28, 3, 0, |
|
ast2600_eclk_div_table, |
|
&aspeed_g6_clk_lock); |
|
if (IS_ERR(hw)) |
|
return PTR_ERR(hw); |
|
aspeed_g6_clk_data->hws[ASPEED_CLK_ECLK] = hw; |
|
|
|
for (i = 0; i < ARRAY_SIZE(aspeed_g6_gates); i++) { |
|
const struct aspeed_gate_data *gd = &aspeed_g6_gates[i]; |
|
u32 gate_flags; |
|
|
|
/* |
|
* Special case: the USB port 1 clock (bit 14) is always |
|
* working the opposite way from the other ones. |
|
*/ |
|
gate_flags = (gd->clock_idx == 14) ? 0 : CLK_GATE_SET_TO_DISABLE; |
|
hw = aspeed_g6_clk_hw_register_gate(dev, |
|
gd->name, |
|
gd->parent_name, |
|
gd->flags, |
|
map, |
|
gd->clock_idx, |
|
gd->reset_idx, |
|
gate_flags, |
|
&aspeed_g6_clk_lock); |
|
if (IS_ERR(hw)) |
|
return PTR_ERR(hw); |
|
aspeed_g6_clk_data->hws[i] = hw; |
|
} |
|
|
|
return 0; |
|
}; |
|
|
|
static const struct of_device_id aspeed_g6_clk_dt_ids[] = { |
|
{ .compatible = "aspeed,ast2600-scu" }, |
|
{ } |
|
}; |
|
|
|
static struct platform_driver aspeed_g6_clk_driver = { |
|
.probe = aspeed_g6_clk_probe, |
|
.driver = { |
|
.name = "ast2600-clk", |
|
.of_match_table = aspeed_g6_clk_dt_ids, |
|
.suppress_bind_attrs = true, |
|
}, |
|
}; |
|
builtin_platform_driver(aspeed_g6_clk_driver); |
|
|
|
static const u32 ast2600_a0_axi_ahb_div_table[] = { |
|
2, 2, 3, 5, |
|
}; |
|
|
|
static const u32 ast2600_a1_axi_ahb_div0_tbl[] = { |
|
3, 2, 3, 4, |
|
}; |
|
|
|
static const u32 ast2600_a1_axi_ahb_div1_tbl[] = { |
|
3, 4, 6, 8, |
|
}; |
|
|
|
static const u32 ast2600_a1_axi_ahb200_tbl[] = { |
|
3, 4, 3, 4, 2, 2, 2, 2, |
|
}; |
|
|
|
static void __init aspeed_g6_cc(struct regmap *map) |
|
{ |
|
struct clk_hw *hw; |
|
u32 val, div, divbits, chip_id, axi_div, ahb_div; |
|
|
|
clk_hw_register_fixed_rate(NULL, "clkin", NULL, 0, 25000000); |
|
|
|
/* |
|
* High-speed PLL clock derived from the crystal. This the CPU clock, |
|
* and we assume that it is enabled |
|
*/ |
|
regmap_read(map, ASPEED_HPLL_PARAM, &val); |
|
aspeed_g6_clk_data->hws[ASPEED_CLK_HPLL] = ast2600_calc_pll("hpll", val); |
|
|
|
regmap_read(map, ASPEED_MPLL_PARAM, &val); |
|
aspeed_g6_clk_data->hws[ASPEED_CLK_MPLL] = ast2600_calc_pll("mpll", val); |
|
|
|
regmap_read(map, ASPEED_DPLL_PARAM, &val); |
|
aspeed_g6_clk_data->hws[ASPEED_CLK_DPLL] = ast2600_calc_pll("dpll", val); |
|
|
|
regmap_read(map, ASPEED_EPLL_PARAM, &val); |
|
aspeed_g6_clk_data->hws[ASPEED_CLK_EPLL] = ast2600_calc_pll("epll", val); |
|
|
|
regmap_read(map, ASPEED_APLL_PARAM, &val); |
|
aspeed_g6_clk_data->hws[ASPEED_CLK_APLL] = ast2600_calc_apll("apll", val); |
|
|
|
/* Strap bits 12:11 define the AXI/AHB clock frequency ratio (aka HCLK)*/ |
|
regmap_read(map, ASPEED_G6_STRAP1, &val); |
|
if (val & BIT(16)) |
|
axi_div = 1; |
|
else |
|
axi_div = 2; |
|
|
|
divbits = (val >> 11) & 0x3; |
|
regmap_read(map, ASPEED_G6_SILICON_REV, &chip_id); |
|
if (chip_id & BIT(16)) { |
|
if (!divbits) { |
|
ahb_div = ast2600_a1_axi_ahb200_tbl[(val >> 8) & 0x3]; |
|
if (val & BIT(16)) |
|
ahb_div *= 2; |
|
} else { |
|
if (val & BIT(16)) |
|
ahb_div = ast2600_a1_axi_ahb_div1_tbl[divbits]; |
|
else |
|
ahb_div = ast2600_a1_axi_ahb_div0_tbl[divbits]; |
|
} |
|
} else { |
|
ahb_div = ast2600_a0_axi_ahb_div_table[(val >> 11) & 0x3]; |
|
} |
|
|
|
hw = clk_hw_register_fixed_factor(NULL, "ahb", "hpll", 0, 1, axi_div * ahb_div); |
|
aspeed_g6_clk_data->hws[ASPEED_CLK_AHB] = hw; |
|
|
|
regmap_read(map, ASPEED_G6_CLK_SELECTION1, &val); |
|
val = (val >> 23) & 0x7; |
|
div = 4 * (val + 1); |
|
hw = clk_hw_register_fixed_factor(NULL, "apb1", "hpll", 0, 1, div); |
|
aspeed_g6_clk_data->hws[ASPEED_CLK_APB1] = hw; |
|
|
|
regmap_read(map, ASPEED_G6_CLK_SELECTION4, &val); |
|
val = (val >> 9) & 0x7; |
|
div = 2 * (val + 1); |
|
hw = clk_hw_register_fixed_factor(NULL, "apb2", "ahb", 0, 1, div); |
|
aspeed_g6_clk_data->hws[ASPEED_CLK_APB2] = hw; |
|
|
|
/* USB 2.0 port1 phy 40MHz clock */ |
|
hw = clk_hw_register_fixed_rate(NULL, "usb-phy-40m", NULL, 0, 40000000); |
|
aspeed_g6_clk_data->hws[ASPEED_CLK_USBPHY_40M] = hw; |
|
}; |
|
|
|
static void __init aspeed_g6_cc_init(struct device_node *np) |
|
{ |
|
struct regmap *map; |
|
int ret; |
|
int i; |
|
|
|
scu_g6_base = of_iomap(np, 0); |
|
if (!scu_g6_base) |
|
return; |
|
|
|
aspeed_g6_clk_data = kzalloc(struct_size(aspeed_g6_clk_data, hws, |
|
ASPEED_G6_NUM_CLKS), GFP_KERNEL); |
|
if (!aspeed_g6_clk_data) |
|
return; |
|
|
|
/* |
|
* This way all clocks fetched before the platform device probes, |
|
* except those we assign here for early use, will be deferred. |
|
*/ |
|
for (i = 0; i < ASPEED_G6_NUM_CLKS; i++) |
|
aspeed_g6_clk_data->hws[i] = ERR_PTR(-EPROBE_DEFER); |
|
|
|
/* |
|
* We check that the regmap works on this very first access, |
|
* but as this is an MMIO-backed regmap, subsequent regmap |
|
* access is not going to fail and we skip error checks from |
|
* this point. |
|
*/ |
|
map = syscon_node_to_regmap(np); |
|
if (IS_ERR(map)) { |
|
pr_err("no syscon regmap\n"); |
|
return; |
|
} |
|
|
|
aspeed_g6_cc(map); |
|
aspeed_g6_clk_data->num = ASPEED_G6_NUM_CLKS; |
|
ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, aspeed_g6_clk_data); |
|
if (ret) |
|
pr_err("failed to add DT provider: %d\n", ret); |
|
}; |
|
CLK_OF_DECLARE_DRIVER(aspeed_cc_g6, "aspeed,ast2600-scu", aspeed_g6_cc_init);
|
|
|