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1357 lines
34 KiB
1357 lines
34 KiB
/* SPDX-License-Identifier: GPL-2.0-or-later */ |
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/* |
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* PARISC TLB and cache flushing support |
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* Copyright (C) 2000-2001 Hewlett-Packard (John Marvin) |
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* Copyright (C) 2001 Matthew Wilcox (willy at parisc-linux.org) |
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* Copyright (C) 2002 Richard Hirst (rhirst with parisc-linux.org) |
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*/ |
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|
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/* |
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* NOTE: fdc,fic, and pdc instructions that use base register modification |
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* should only use index and base registers that are not shadowed, |
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* so that the fast path emulation in the non access miss handler |
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* can be used. |
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*/ |
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#ifdef CONFIG_64BIT |
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.level 2.0w |
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#else |
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.level 2.0 |
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#endif |
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#include <asm/psw.h> |
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#include <asm/assembly.h> |
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#include <asm/cache.h> |
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#include <asm/ldcw.h> |
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#include <asm/alternative.h> |
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#include <linux/linkage.h> |
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#include <linux/init.h> |
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#include <linux/pgtable.h> |
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.section .text.hot |
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.align 16 |
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ENTRY_CFI(flush_tlb_all_local) |
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/* |
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* The pitlbe and pdtlbe instructions should only be used to |
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* flush the entire tlb. Also, there needs to be no intervening |
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* tlb operations, e.g. tlb misses, so the operation needs |
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* to happen in real mode with all interruptions disabled. |
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*/ |
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/* pcxt_ssm_bug - relied upon translation! PA 2.0 Arch. F-4 and F-5 */ |
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rsm PSW_SM_I, %r19 /* save I-bit state */ |
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load32 PA(1f), %r1 |
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nop |
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nop |
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nop |
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nop |
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nop |
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rsm PSW_SM_Q, %r0 /* prep to load iia queue */ |
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mtctl %r0, %cr17 /* Clear IIASQ tail */ |
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mtctl %r0, %cr17 /* Clear IIASQ head */ |
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mtctl %r1, %cr18 /* IIAOQ head */ |
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ldo 4(%r1), %r1 |
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mtctl %r1, %cr18 /* IIAOQ tail */ |
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load32 REAL_MODE_PSW, %r1 |
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mtctl %r1, %ipsw |
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rfi |
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nop |
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1: load32 PA(cache_info), %r1 |
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/* Flush Instruction Tlb */ |
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88: LDREG ITLB_SID_BASE(%r1), %r20 |
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LDREG ITLB_SID_STRIDE(%r1), %r21 |
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LDREG ITLB_SID_COUNT(%r1), %r22 |
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LDREG ITLB_OFF_BASE(%r1), %arg0 |
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LDREG ITLB_OFF_STRIDE(%r1), %arg1 |
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LDREG ITLB_OFF_COUNT(%r1), %arg2 |
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LDREG ITLB_LOOP(%r1), %arg3 |
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addib,COND(=) -1, %arg3, fitoneloop /* Preadjust and test */ |
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movb,<,n %arg3, %r31, fitdone /* If loop < 0, skip */ |
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copy %arg0, %r28 /* Init base addr */ |
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fitmanyloop: /* Loop if LOOP >= 2 */ |
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mtsp %r20, %sr1 |
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add %r21, %r20, %r20 /* increment space */ |
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copy %arg2, %r29 /* Init middle loop count */ |
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fitmanymiddle: /* Loop if LOOP >= 2 */ |
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addib,COND(>) -1, %r31, fitmanymiddle /* Adjusted inner loop decr */ |
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pitlbe %r0(%sr1, %r28) |
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pitlbe,m %arg1(%sr1, %r28) /* Last pitlbe and addr adjust */ |
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addib,COND(>) -1, %r29, fitmanymiddle /* Middle loop decr */ |
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copy %arg3, %r31 /* Re-init inner loop count */ |
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movb,tr %arg0, %r28, fitmanyloop /* Re-init base addr */ |
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addib,COND(<=),n -1, %r22, fitdone /* Outer loop count decr */ |
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fitoneloop: /* Loop if LOOP = 1 */ |
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mtsp %r20, %sr1 |
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copy %arg0, %r28 /* init base addr */ |
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copy %arg2, %r29 /* init middle loop count */ |
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fitonemiddle: /* Loop if LOOP = 1 */ |
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addib,COND(>) -1, %r29, fitonemiddle /* Middle loop count decr */ |
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pitlbe,m %arg1(%sr1, %r28) /* pitlbe for one loop */ |
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addib,COND(>) -1, %r22, fitoneloop /* Outer loop count decr */ |
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add %r21, %r20, %r20 /* increment space */ |
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fitdone: |
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ALTERNATIVE(88b, fitdone, ALT_COND_NO_SPLIT_TLB, INSN_NOP) |
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/* Flush Data Tlb */ |
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LDREG DTLB_SID_BASE(%r1), %r20 |
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LDREG DTLB_SID_STRIDE(%r1), %r21 |
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LDREG DTLB_SID_COUNT(%r1), %r22 |
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LDREG DTLB_OFF_BASE(%r1), %arg0 |
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LDREG DTLB_OFF_STRIDE(%r1), %arg1 |
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LDREG DTLB_OFF_COUNT(%r1), %arg2 |
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LDREG DTLB_LOOP(%r1), %arg3 |
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addib,COND(=) -1, %arg3, fdtoneloop /* Preadjust and test */ |
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movb,<,n %arg3, %r31, fdtdone /* If loop < 0, skip */ |
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copy %arg0, %r28 /* Init base addr */ |
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fdtmanyloop: /* Loop if LOOP >= 2 */ |
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mtsp %r20, %sr1 |
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add %r21, %r20, %r20 /* increment space */ |
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copy %arg2, %r29 /* Init middle loop count */ |
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fdtmanymiddle: /* Loop if LOOP >= 2 */ |
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addib,COND(>) -1, %r31, fdtmanymiddle /* Adjusted inner loop decr */ |
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pdtlbe %r0(%sr1, %r28) |
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pdtlbe,m %arg1(%sr1, %r28) /* Last pdtlbe and addr adjust */ |
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addib,COND(>) -1, %r29, fdtmanymiddle /* Middle loop decr */ |
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copy %arg3, %r31 /* Re-init inner loop count */ |
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movb,tr %arg0, %r28, fdtmanyloop /* Re-init base addr */ |
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addib,COND(<=),n -1, %r22,fdtdone /* Outer loop count decr */ |
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fdtoneloop: /* Loop if LOOP = 1 */ |
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mtsp %r20, %sr1 |
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copy %arg0, %r28 /* init base addr */ |
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copy %arg2, %r29 /* init middle loop count */ |
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fdtonemiddle: /* Loop if LOOP = 1 */ |
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addib,COND(>) -1, %r29, fdtonemiddle /* Middle loop count decr */ |
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pdtlbe,m %arg1(%sr1, %r28) /* pdtlbe for one loop */ |
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addib,COND(>) -1, %r22, fdtoneloop /* Outer loop count decr */ |
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add %r21, %r20, %r20 /* increment space */ |
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fdtdone: |
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/* |
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* Switch back to virtual mode |
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*/ |
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/* pcxt_ssm_bug */ |
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rsm PSW_SM_I, %r0 |
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load32 2f, %r1 |
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nop |
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nop |
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nop |
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nop |
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nop |
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rsm PSW_SM_Q, %r0 /* prep to load iia queue */ |
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mtctl %r0, %cr17 /* Clear IIASQ tail */ |
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mtctl %r0, %cr17 /* Clear IIASQ head */ |
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mtctl %r1, %cr18 /* IIAOQ head */ |
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ldo 4(%r1), %r1 |
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mtctl %r1, %cr18 /* IIAOQ tail */ |
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load32 KERNEL_PSW, %r1 |
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or %r1, %r19, %r1 /* I-bit to state on entry */ |
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mtctl %r1, %ipsw /* restore I-bit (entire PSW) */ |
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rfi |
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nop |
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2: bv %r0(%r2) |
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nop |
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/* |
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* When running in qemu, drop whole flush_tlb_all_local function and |
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* replace by one pdtlbe instruction, for which QEMU will drop all |
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* local TLB entries. |
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*/ |
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3: pdtlbe %r0(%sr1,%r0) |
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bv,n %r0(%r2) |
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ALTERNATIVE_CODE(flush_tlb_all_local, 2, ALT_COND_RUN_ON_QEMU, 3b) |
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ENDPROC_CFI(flush_tlb_all_local) |
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.import cache_info,data |
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ENTRY_CFI(flush_instruction_cache_local) |
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88: load32 cache_info, %r1 |
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/* Flush Instruction Cache */ |
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LDREG ICACHE_BASE(%r1), %arg0 |
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LDREG ICACHE_STRIDE(%r1), %arg1 |
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LDREG ICACHE_COUNT(%r1), %arg2 |
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LDREG ICACHE_LOOP(%r1), %arg3 |
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rsm PSW_SM_I, %r22 /* No mmgt ops during loop*/ |
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mtsp %r0, %sr1 |
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addib,COND(=) -1, %arg3, fioneloop /* Preadjust and test */ |
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movb,<,n %arg3, %r31, fisync /* If loop < 0, do sync */ |
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fimanyloop: /* Loop if LOOP >= 2 */ |
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addib,COND(>) -1, %r31, fimanyloop /* Adjusted inner loop decr */ |
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fice %r0(%sr1, %arg0) |
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fice,m %arg1(%sr1, %arg0) /* Last fice and addr adjust */ |
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movb,tr %arg3, %r31, fimanyloop /* Re-init inner loop count */ |
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addib,COND(<=),n -1, %arg2, fisync /* Outer loop decr */ |
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fioneloop: /* Loop if LOOP = 1 */ |
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/* Some implementations may flush with a single fice instruction */ |
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cmpib,COND(>>=),n 15, %arg2, fioneloop2 |
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fioneloop1: |
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fice,m %arg1(%sr1, %arg0) |
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fice,m %arg1(%sr1, %arg0) |
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fice,m %arg1(%sr1, %arg0) |
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fice,m %arg1(%sr1, %arg0) |
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fice,m %arg1(%sr1, %arg0) |
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fice,m %arg1(%sr1, %arg0) |
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fice,m %arg1(%sr1, %arg0) |
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fice,m %arg1(%sr1, %arg0) |
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fice,m %arg1(%sr1, %arg0) |
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fice,m %arg1(%sr1, %arg0) |
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fice,m %arg1(%sr1, %arg0) |
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fice,m %arg1(%sr1, %arg0) |
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fice,m %arg1(%sr1, %arg0) |
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fice,m %arg1(%sr1, %arg0) |
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fice,m %arg1(%sr1, %arg0) |
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addib,COND(>) -16, %arg2, fioneloop1 |
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fice,m %arg1(%sr1, %arg0) |
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/* Check if done */ |
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cmpb,COND(=),n %arg2, %r0, fisync /* Predict branch taken */ |
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fioneloop2: |
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addib,COND(>) -1, %arg2, fioneloop2 /* Outer loop count decr */ |
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fice,m %arg1(%sr1, %arg0) /* Fice for one loop */ |
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fisync: |
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sync |
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mtsm %r22 /* restore I-bit */ |
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89: ALTERNATIVE(88b, 89b, ALT_COND_NO_ICACHE, INSN_NOP) |
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bv %r0(%r2) |
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nop |
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ENDPROC_CFI(flush_instruction_cache_local) |
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.import cache_info, data |
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ENTRY_CFI(flush_data_cache_local) |
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88: load32 cache_info, %r1 |
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/* Flush Data Cache */ |
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LDREG DCACHE_BASE(%r1), %arg0 |
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LDREG DCACHE_STRIDE(%r1), %arg1 |
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LDREG DCACHE_COUNT(%r1), %arg2 |
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LDREG DCACHE_LOOP(%r1), %arg3 |
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rsm PSW_SM_I, %r22 /* No mmgt ops during loop*/ |
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mtsp %r0, %sr1 |
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addib,COND(=) -1, %arg3, fdoneloop /* Preadjust and test */ |
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movb,<,n %arg3, %r31, fdsync /* If loop < 0, do sync */ |
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fdmanyloop: /* Loop if LOOP >= 2 */ |
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addib,COND(>) -1, %r31, fdmanyloop /* Adjusted inner loop decr */ |
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fdce %r0(%sr1, %arg0) |
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fdce,m %arg1(%sr1, %arg0) /* Last fdce and addr adjust */ |
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movb,tr %arg3, %r31, fdmanyloop /* Re-init inner loop count */ |
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addib,COND(<=),n -1, %arg2, fdsync /* Outer loop decr */ |
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fdoneloop: /* Loop if LOOP = 1 */ |
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/* Some implementations may flush with a single fdce instruction */ |
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cmpib,COND(>>=),n 15, %arg2, fdoneloop2 |
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fdoneloop1: |
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fdce,m %arg1(%sr1, %arg0) |
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fdce,m %arg1(%sr1, %arg0) |
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fdce,m %arg1(%sr1, %arg0) |
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fdce,m %arg1(%sr1, %arg0) |
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fdce,m %arg1(%sr1, %arg0) |
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fdce,m %arg1(%sr1, %arg0) |
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fdce,m %arg1(%sr1, %arg0) |
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fdce,m %arg1(%sr1, %arg0) |
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fdce,m %arg1(%sr1, %arg0) |
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fdce,m %arg1(%sr1, %arg0) |
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fdce,m %arg1(%sr1, %arg0) |
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fdce,m %arg1(%sr1, %arg0) |
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fdce,m %arg1(%sr1, %arg0) |
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fdce,m %arg1(%sr1, %arg0) |
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fdce,m %arg1(%sr1, %arg0) |
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addib,COND(>) -16, %arg2, fdoneloop1 |
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fdce,m %arg1(%sr1, %arg0) |
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/* Check if done */ |
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cmpb,COND(=),n %arg2, %r0, fdsync /* Predict branch taken */ |
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fdoneloop2: |
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addib,COND(>) -1, %arg2, fdoneloop2 /* Outer loop count decr */ |
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fdce,m %arg1(%sr1, %arg0) /* Fdce for one loop */ |
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fdsync: |
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syncdma |
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sync |
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mtsm %r22 /* restore I-bit */ |
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89: ALTERNATIVE(88b, 89b, ALT_COND_NO_DCACHE, INSN_NOP) |
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bv %r0(%r2) |
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nop |
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ENDPROC_CFI(flush_data_cache_local) |
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/* Clear page using kernel mapping. */ |
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ENTRY_CFI(clear_page_asm) |
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#ifdef CONFIG_64BIT |
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/* Unroll the loop. */ |
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ldi (PAGE_SIZE / 128), %r1 |
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1: |
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std %r0, 0(%r26) |
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std %r0, 8(%r26) |
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std %r0, 16(%r26) |
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std %r0, 24(%r26) |
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std %r0, 32(%r26) |
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std %r0, 40(%r26) |
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std %r0, 48(%r26) |
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std %r0, 56(%r26) |
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std %r0, 64(%r26) |
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std %r0, 72(%r26) |
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std %r0, 80(%r26) |
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std %r0, 88(%r26) |
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std %r0, 96(%r26) |
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std %r0, 104(%r26) |
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std %r0, 112(%r26) |
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std %r0, 120(%r26) |
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/* Note reverse branch hint for addib is taken. */ |
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addib,COND(>),n -1, %r1, 1b |
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ldo 128(%r26), %r26 |
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#else |
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/* |
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* Note that until (if) we start saving the full 64-bit register |
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* values on interrupt, we can't use std on a 32 bit kernel. |
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*/ |
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ldi (PAGE_SIZE / 64), %r1 |
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1: |
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stw %r0, 0(%r26) |
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stw %r0, 4(%r26) |
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stw %r0, 8(%r26) |
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stw %r0, 12(%r26) |
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stw %r0, 16(%r26) |
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stw %r0, 20(%r26) |
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stw %r0, 24(%r26) |
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stw %r0, 28(%r26) |
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stw %r0, 32(%r26) |
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stw %r0, 36(%r26) |
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stw %r0, 40(%r26) |
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stw %r0, 44(%r26) |
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stw %r0, 48(%r26) |
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stw %r0, 52(%r26) |
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stw %r0, 56(%r26) |
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stw %r0, 60(%r26) |
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addib,COND(>),n -1, %r1, 1b |
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ldo 64(%r26), %r26 |
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#endif |
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bv %r0(%r2) |
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nop |
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ENDPROC_CFI(clear_page_asm) |
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/* Copy page using kernel mapping. */ |
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ENTRY_CFI(copy_page_asm) |
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#ifdef CONFIG_64BIT |
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/* PA8x00 CPUs can consume 2 loads or 1 store per cycle. |
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* Unroll the loop by hand and arrange insn appropriately. |
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* Prefetch doesn't improve performance on rp3440. |
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* GCC probably can do this just as well... |
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*/ |
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ldi (PAGE_SIZE / 128), %r1 |
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1: ldd 0(%r25), %r19 |
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ldd 8(%r25), %r20 |
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ldd 16(%r25), %r21 |
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ldd 24(%r25), %r22 |
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std %r19, 0(%r26) |
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std %r20, 8(%r26) |
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ldd 32(%r25), %r19 |
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ldd 40(%r25), %r20 |
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std %r21, 16(%r26) |
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std %r22, 24(%r26) |
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ldd 48(%r25), %r21 |
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ldd 56(%r25), %r22 |
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std %r19, 32(%r26) |
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std %r20, 40(%r26) |
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ldd 64(%r25), %r19 |
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ldd 72(%r25), %r20 |
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std %r21, 48(%r26) |
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std %r22, 56(%r26) |
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|
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ldd 80(%r25), %r21 |
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ldd 88(%r25), %r22 |
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std %r19, 64(%r26) |
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std %r20, 72(%r26) |
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|
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ldd 96(%r25), %r19 |
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ldd 104(%r25), %r20 |
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std %r21, 80(%r26) |
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std %r22, 88(%r26) |
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|
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ldd 112(%r25), %r21 |
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ldd 120(%r25), %r22 |
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ldo 128(%r25), %r25 |
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std %r19, 96(%r26) |
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std %r20, 104(%r26) |
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|
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std %r21, 112(%r26) |
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std %r22, 120(%r26) |
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/* Note reverse branch hint for addib is taken. */ |
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addib,COND(>),n -1, %r1, 1b |
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ldo 128(%r26), %r26 |
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|
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#else |
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|
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/* |
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* This loop is optimized for PCXL/PCXL2 ldw/ldw and stw/stw |
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* bundles (very restricted rules for bundling). |
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* Note that until (if) we start saving |
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* the full 64 bit register values on interrupt, we can't |
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* use ldd/std on a 32 bit kernel. |
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*/ |
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ldw 0(%r25), %r19 |
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ldi (PAGE_SIZE / 64), %r1 |
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|
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1: |
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ldw 4(%r25), %r20 |
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ldw 8(%r25), %r21 |
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ldw 12(%r25), %r22 |
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stw %r19, 0(%r26) |
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stw %r20, 4(%r26) |
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stw %r21, 8(%r26) |
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stw %r22, 12(%r26) |
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ldw 16(%r25), %r19 |
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ldw 20(%r25), %r20 |
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ldw 24(%r25), %r21 |
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ldw 28(%r25), %r22 |
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stw %r19, 16(%r26) |
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stw %r20, 20(%r26) |
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stw %r21, 24(%r26) |
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stw %r22, 28(%r26) |
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ldw 32(%r25), %r19 |
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ldw 36(%r25), %r20 |
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ldw 40(%r25), %r21 |
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ldw 44(%r25), %r22 |
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stw %r19, 32(%r26) |
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stw %r20, 36(%r26) |
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stw %r21, 40(%r26) |
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stw %r22, 44(%r26) |
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ldw 48(%r25), %r19 |
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ldw 52(%r25), %r20 |
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ldw 56(%r25), %r21 |
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ldw 60(%r25), %r22 |
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stw %r19, 48(%r26) |
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stw %r20, 52(%r26) |
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ldo 64(%r25), %r25 |
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stw %r21, 56(%r26) |
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stw %r22, 60(%r26) |
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ldo 64(%r26), %r26 |
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addib,COND(>),n -1, %r1, 1b |
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ldw 0(%r25), %r19 |
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#endif |
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bv %r0(%r2) |
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nop |
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ENDPROC_CFI(copy_page_asm) |
|
|
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/* |
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* NOTE: Code in clear_user_page has a hard coded dependency on the |
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* maximum alias boundary being 4 Mb. We've been assured by the |
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* parisc chip designers that there will not ever be a parisc |
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* chip with a larger alias boundary (Never say never :-) ). |
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* |
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* Subtle: the dtlb miss handlers support the temp alias region by |
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* "knowing" that if a dtlb miss happens within the temp alias |
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* region it must have occurred while in clear_user_page. Since |
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* this routine makes use of processor local translations, we |
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* don't want to insert them into the kernel page table. Instead, |
|
* we load up some general registers (they need to be registers |
|
* which aren't shadowed) with the physical page numbers (preshifted |
|
* for tlb insertion) needed to insert the translations. When we |
|
* miss on the translation, the dtlb miss handler inserts the |
|
* translation into the tlb using these values: |
|
* |
|
* %r26 physical page (shifted for tlb insert) of "to" translation |
|
* %r23 physical page (shifted for tlb insert) of "from" translation |
|
*/ |
|
|
|
/* Drop prot bits and convert to page addr for iitlbt and idtlbt */ |
|
#define PAGE_ADD_SHIFT (PAGE_SHIFT-12) |
|
.macro convert_phys_for_tlb_insert20 phys |
|
extrd,u \phys, 56-PAGE_ADD_SHIFT, 32-PAGE_ADD_SHIFT, \phys |
|
#if _PAGE_SIZE_ENCODING_DEFAULT |
|
depdi _PAGE_SIZE_ENCODING_DEFAULT, 63, (63-58), \phys |
|
#endif |
|
.endm |
|
|
|
/* |
|
* copy_user_page_asm() performs a page copy using mappings |
|
* equivalent to the user page mappings. It can be used to |
|
* implement copy_user_page() but unfortunately both the `from' |
|
* and `to' pages need to be flushed through mappings equivalent |
|
* to the user mappings after the copy because the kernel accesses |
|
* the `from' page through the kmap kernel mapping and the `to' |
|
* page needs to be flushed since code can be copied. As a |
|
* result, this implementation is less efficient than the simpler |
|
* copy using the kernel mapping. It only needs the `from' page |
|
* to flushed via the user mapping. The kunmap routines handle |
|
* the flushes needed for the kernel mapping. |
|
* |
|
* I'm still keeping this around because it may be possible to |
|
* use it if more information is passed into copy_user_page(). |
|
* Have to do some measurements to see if it is worthwhile to |
|
* lobby for such a change. |
|
* |
|
*/ |
|
|
|
ENTRY_CFI(copy_user_page_asm) |
|
/* Convert virtual `to' and `from' addresses to physical addresses. |
|
Move `from' physical address to non shadowed register. */ |
|
ldil L%(__PAGE_OFFSET), %r1 |
|
sub %r26, %r1, %r26 |
|
sub %r25, %r1, %r23 |
|
|
|
ldil L%(TMPALIAS_MAP_START), %r28 |
|
#ifdef CONFIG_64BIT |
|
#if (TMPALIAS_MAP_START >= 0x80000000) |
|
depdi 0, 31,32, %r28 /* clear any sign extension */ |
|
#endif |
|
convert_phys_for_tlb_insert20 %r26 /* convert phys addr to tlb insert format */ |
|
convert_phys_for_tlb_insert20 %r23 /* convert phys addr to tlb insert format */ |
|
depd %r24,63,22, %r28 /* Form aliased virtual address 'to' */ |
|
depdi 0, 63,PAGE_SHIFT, %r28 /* Clear any offset bits */ |
|
copy %r28, %r29 |
|
depdi 1, 41,1, %r29 /* Form aliased virtual address 'from' */ |
|
#else |
|
extrw,u %r26, 24,25, %r26 /* convert phys addr to tlb insert format */ |
|
extrw,u %r23, 24,25, %r23 /* convert phys addr to tlb insert format */ |
|
depw %r24, 31,22, %r28 /* Form aliased virtual address 'to' */ |
|
depwi 0, 31,PAGE_SHIFT, %r28 /* Clear any offset bits */ |
|
copy %r28, %r29 |
|
depwi 1, 9,1, %r29 /* Form aliased virtual address 'from' */ |
|
#endif |
|
|
|
/* Purge any old translations */ |
|
|
|
#ifdef CONFIG_PA20 |
|
pdtlb,l %r0(%r28) |
|
pdtlb,l %r0(%r29) |
|
#else |
|
0: pdtlb %r0(%r28) |
|
1: pdtlb %r0(%r29) |
|
ALTERNATIVE(0b, 0b+4, ALT_COND_NO_SMP, INSN_PxTLB) |
|
ALTERNATIVE(1b, 1b+4, ALT_COND_NO_SMP, INSN_PxTLB) |
|
#endif |
|
|
|
#ifdef CONFIG_64BIT |
|
/* PA8x00 CPUs can consume 2 loads or 1 store per cycle. |
|
* Unroll the loop by hand and arrange insn appropriately. |
|
* GCC probably can do this just as well. |
|
*/ |
|
|
|
ldd 0(%r29), %r19 |
|
ldi (PAGE_SIZE / 128), %r1 |
|
|
|
1: ldd 8(%r29), %r20 |
|
|
|
ldd 16(%r29), %r21 |
|
ldd 24(%r29), %r22 |
|
std %r19, 0(%r28) |
|
std %r20, 8(%r28) |
|
|
|
ldd 32(%r29), %r19 |
|
ldd 40(%r29), %r20 |
|
std %r21, 16(%r28) |
|
std %r22, 24(%r28) |
|
|
|
ldd 48(%r29), %r21 |
|
ldd 56(%r29), %r22 |
|
std %r19, 32(%r28) |
|
std %r20, 40(%r28) |
|
|
|
ldd 64(%r29), %r19 |
|
ldd 72(%r29), %r20 |
|
std %r21, 48(%r28) |
|
std %r22, 56(%r28) |
|
|
|
ldd 80(%r29), %r21 |
|
ldd 88(%r29), %r22 |
|
std %r19, 64(%r28) |
|
std %r20, 72(%r28) |
|
|
|
ldd 96(%r29), %r19 |
|
ldd 104(%r29), %r20 |
|
std %r21, 80(%r28) |
|
std %r22, 88(%r28) |
|
|
|
ldd 112(%r29), %r21 |
|
ldd 120(%r29), %r22 |
|
std %r19, 96(%r28) |
|
std %r20, 104(%r28) |
|
|
|
ldo 128(%r29), %r29 |
|
std %r21, 112(%r28) |
|
std %r22, 120(%r28) |
|
ldo 128(%r28), %r28 |
|
|
|
/* conditional branches nullify on forward taken branch, and on |
|
* non-taken backward branch. Note that .+4 is a backwards branch. |
|
* The ldd should only get executed if the branch is taken. |
|
*/ |
|
addib,COND(>),n -1, %r1, 1b /* bundle 10 */ |
|
ldd 0(%r29), %r19 /* start next loads */ |
|
|
|
#else |
|
ldi (PAGE_SIZE / 64), %r1 |
|
|
|
/* |
|
* This loop is optimized for PCXL/PCXL2 ldw/ldw and stw/stw |
|
* bundles (very restricted rules for bundling). It probably |
|
* does OK on PCXU and better, but we could do better with |
|
* ldd/std instructions. Note that until (if) we start saving |
|
* the full 64 bit register values on interrupt, we can't |
|
* use ldd/std on a 32 bit kernel. |
|
*/ |
|
|
|
1: ldw 0(%r29), %r19 |
|
ldw 4(%r29), %r20 |
|
ldw 8(%r29), %r21 |
|
ldw 12(%r29), %r22 |
|
stw %r19, 0(%r28) |
|
stw %r20, 4(%r28) |
|
stw %r21, 8(%r28) |
|
stw %r22, 12(%r28) |
|
ldw 16(%r29), %r19 |
|
ldw 20(%r29), %r20 |
|
ldw 24(%r29), %r21 |
|
ldw 28(%r29), %r22 |
|
stw %r19, 16(%r28) |
|
stw %r20, 20(%r28) |
|
stw %r21, 24(%r28) |
|
stw %r22, 28(%r28) |
|
ldw 32(%r29), %r19 |
|
ldw 36(%r29), %r20 |
|
ldw 40(%r29), %r21 |
|
ldw 44(%r29), %r22 |
|
stw %r19, 32(%r28) |
|
stw %r20, 36(%r28) |
|
stw %r21, 40(%r28) |
|
stw %r22, 44(%r28) |
|
ldw 48(%r29), %r19 |
|
ldw 52(%r29), %r20 |
|
ldw 56(%r29), %r21 |
|
ldw 60(%r29), %r22 |
|
stw %r19, 48(%r28) |
|
stw %r20, 52(%r28) |
|
stw %r21, 56(%r28) |
|
stw %r22, 60(%r28) |
|
ldo 64(%r28), %r28 |
|
|
|
addib,COND(>) -1, %r1,1b |
|
ldo 64(%r29), %r29 |
|
#endif |
|
|
|
bv %r0(%r2) |
|
nop |
|
ENDPROC_CFI(copy_user_page_asm) |
|
|
|
ENTRY_CFI(clear_user_page_asm) |
|
tophys_r1 %r26 |
|
|
|
ldil L%(TMPALIAS_MAP_START), %r28 |
|
#ifdef CONFIG_64BIT |
|
#if (TMPALIAS_MAP_START >= 0x80000000) |
|
depdi 0, 31,32, %r28 /* clear any sign extension */ |
|
#endif |
|
convert_phys_for_tlb_insert20 %r26 /* convert phys addr to tlb insert format */ |
|
depd %r25, 63,22, %r28 /* Form aliased virtual address 'to' */ |
|
depdi 0, 63,PAGE_SHIFT, %r28 /* Clear any offset bits */ |
|
#else |
|
extrw,u %r26, 24,25, %r26 /* convert phys addr to tlb insert format */ |
|
depw %r25, 31,22, %r28 /* Form aliased virtual address 'to' */ |
|
depwi 0, 31,PAGE_SHIFT, %r28 /* Clear any offset bits */ |
|
#endif |
|
|
|
/* Purge any old translation */ |
|
|
|
#ifdef CONFIG_PA20 |
|
pdtlb,l %r0(%r28) |
|
#else |
|
0: pdtlb %r0(%r28) |
|
ALTERNATIVE(0b, 0b+4, ALT_COND_NO_SMP, INSN_PxTLB) |
|
#endif |
|
|
|
#ifdef CONFIG_64BIT |
|
ldi (PAGE_SIZE / 128), %r1 |
|
|
|
/* PREFETCH (Write) has not (yet) been proven to help here */ |
|
/* #define PREFETCHW_OP ldd 256(%0), %r0 */ |
|
|
|
1: std %r0, 0(%r28) |
|
std %r0, 8(%r28) |
|
std %r0, 16(%r28) |
|
std %r0, 24(%r28) |
|
std %r0, 32(%r28) |
|
std %r0, 40(%r28) |
|
std %r0, 48(%r28) |
|
std %r0, 56(%r28) |
|
std %r0, 64(%r28) |
|
std %r0, 72(%r28) |
|
std %r0, 80(%r28) |
|
std %r0, 88(%r28) |
|
std %r0, 96(%r28) |
|
std %r0, 104(%r28) |
|
std %r0, 112(%r28) |
|
std %r0, 120(%r28) |
|
addib,COND(>) -1, %r1, 1b |
|
ldo 128(%r28), %r28 |
|
|
|
#else /* ! CONFIG_64BIT */ |
|
ldi (PAGE_SIZE / 64), %r1 |
|
|
|
1: stw %r0, 0(%r28) |
|
stw %r0, 4(%r28) |
|
stw %r0, 8(%r28) |
|
stw %r0, 12(%r28) |
|
stw %r0, 16(%r28) |
|
stw %r0, 20(%r28) |
|
stw %r0, 24(%r28) |
|
stw %r0, 28(%r28) |
|
stw %r0, 32(%r28) |
|
stw %r0, 36(%r28) |
|
stw %r0, 40(%r28) |
|
stw %r0, 44(%r28) |
|
stw %r0, 48(%r28) |
|
stw %r0, 52(%r28) |
|
stw %r0, 56(%r28) |
|
stw %r0, 60(%r28) |
|
addib,COND(>) -1, %r1, 1b |
|
ldo 64(%r28), %r28 |
|
#endif /* CONFIG_64BIT */ |
|
|
|
bv %r0(%r2) |
|
nop |
|
ENDPROC_CFI(clear_user_page_asm) |
|
|
|
ENTRY_CFI(flush_dcache_page_asm) |
|
ldil L%(TMPALIAS_MAP_START), %r28 |
|
#ifdef CONFIG_64BIT |
|
#if (TMPALIAS_MAP_START >= 0x80000000) |
|
depdi 0, 31,32, %r28 /* clear any sign extension */ |
|
#endif |
|
convert_phys_for_tlb_insert20 %r26 /* convert phys addr to tlb insert format */ |
|
depd %r25, 63,22, %r28 /* Form aliased virtual address 'to' */ |
|
depdi 0, 63,PAGE_SHIFT, %r28 /* Clear any offset bits */ |
|
#else |
|
extrw,u %r26, 24,25, %r26 /* convert phys addr to tlb insert format */ |
|
depw %r25, 31,22, %r28 /* Form aliased virtual address 'to' */ |
|
depwi 0, 31,PAGE_SHIFT, %r28 /* Clear any offset bits */ |
|
#endif |
|
|
|
/* Purge any old translation */ |
|
|
|
#ifdef CONFIG_PA20 |
|
pdtlb,l %r0(%r28) |
|
#else |
|
0: pdtlb %r0(%r28) |
|
ALTERNATIVE(0b, 0b+4, ALT_COND_NO_SMP, INSN_PxTLB) |
|
#endif |
|
|
|
88: ldil L%dcache_stride, %r1 |
|
ldw R%dcache_stride(%r1), r31 |
|
|
|
#ifdef CONFIG_64BIT |
|
depdi,z 1, 63-PAGE_SHIFT,1, %r25 |
|
#else |
|
depwi,z 1, 31-PAGE_SHIFT,1, %r25 |
|
#endif |
|
add %r28, %r25, %r25 |
|
sub %r25, r31, %r25 |
|
|
|
1: fdc,m r31(%r28) |
|
fdc,m r31(%r28) |
|
fdc,m r31(%r28) |
|
fdc,m r31(%r28) |
|
fdc,m r31(%r28) |
|
fdc,m r31(%r28) |
|
fdc,m r31(%r28) |
|
fdc,m r31(%r28) |
|
fdc,m r31(%r28) |
|
fdc,m r31(%r28) |
|
fdc,m r31(%r28) |
|
fdc,m r31(%r28) |
|
fdc,m r31(%r28) |
|
fdc,m r31(%r28) |
|
fdc,m r31(%r28) |
|
cmpb,COND(>>) %r25, %r28, 1b /* predict taken */ |
|
fdc,m r31(%r28) |
|
|
|
89: ALTERNATIVE(88b, 89b, ALT_COND_NO_DCACHE, INSN_NOP) |
|
sync |
|
bv %r0(%r2) |
|
nop |
|
ENDPROC_CFI(flush_dcache_page_asm) |
|
|
|
ENTRY_CFI(purge_dcache_page_asm) |
|
ldil L%(TMPALIAS_MAP_START), %r28 |
|
#ifdef CONFIG_64BIT |
|
#if (TMPALIAS_MAP_START >= 0x80000000) |
|
depdi 0, 31,32, %r28 /* clear any sign extension */ |
|
#endif |
|
convert_phys_for_tlb_insert20 %r26 /* convert phys addr to tlb insert format */ |
|
depd %r25, 63,22, %r28 /* Form aliased virtual address 'to' */ |
|
depdi 0, 63,PAGE_SHIFT, %r28 /* Clear any offset bits */ |
|
#else |
|
extrw,u %r26, 24,25, %r26 /* convert phys addr to tlb insert format */ |
|
depw %r25, 31,22, %r28 /* Form aliased virtual address 'to' */ |
|
depwi 0, 31,PAGE_SHIFT, %r28 /* Clear any offset bits */ |
|
#endif |
|
|
|
/* Purge any old translation */ |
|
|
|
#ifdef CONFIG_PA20 |
|
pdtlb,l %r0(%r28) |
|
#else |
|
0: pdtlb %r0(%r28) |
|
ALTERNATIVE(0b, 0b+4, ALT_COND_NO_SMP, INSN_PxTLB) |
|
#endif |
|
|
|
88: ldil L%dcache_stride, %r1 |
|
ldw R%dcache_stride(%r1), r31 |
|
|
|
#ifdef CONFIG_64BIT |
|
depdi,z 1, 63-PAGE_SHIFT,1, %r25 |
|
#else |
|
depwi,z 1, 31-PAGE_SHIFT,1, %r25 |
|
#endif |
|
add %r28, %r25, %r25 |
|
sub %r25, r31, %r25 |
|
|
|
1: pdc,m r31(%r28) |
|
pdc,m r31(%r28) |
|
pdc,m r31(%r28) |
|
pdc,m r31(%r28) |
|
pdc,m r31(%r28) |
|
pdc,m r31(%r28) |
|
pdc,m r31(%r28) |
|
pdc,m r31(%r28) |
|
pdc,m r31(%r28) |
|
pdc,m r31(%r28) |
|
pdc,m r31(%r28) |
|
pdc,m r31(%r28) |
|
pdc,m r31(%r28) |
|
pdc,m r31(%r28) |
|
pdc,m r31(%r28) |
|
cmpb,COND(>>) %r25, %r28, 1b /* predict taken */ |
|
pdc,m r31(%r28) |
|
|
|
89: ALTERNATIVE(88b, 89b, ALT_COND_NO_DCACHE, INSN_NOP) |
|
sync |
|
bv %r0(%r2) |
|
nop |
|
ENDPROC_CFI(purge_dcache_page_asm) |
|
|
|
ENTRY_CFI(flush_icache_page_asm) |
|
ldil L%(TMPALIAS_MAP_START), %r28 |
|
#ifdef CONFIG_64BIT |
|
#if (TMPALIAS_MAP_START >= 0x80000000) |
|
depdi 0, 31,32, %r28 /* clear any sign extension */ |
|
#endif |
|
convert_phys_for_tlb_insert20 %r26 /* convert phys addr to tlb insert format */ |
|
depd %r25, 63,22, %r28 /* Form aliased virtual address 'to' */ |
|
depdi 0, 63,PAGE_SHIFT, %r28 /* Clear any offset bits */ |
|
#else |
|
extrw,u %r26, 24,25, %r26 /* convert phys addr to tlb insert format */ |
|
depw %r25, 31,22, %r28 /* Form aliased virtual address 'to' */ |
|
depwi 0, 31,PAGE_SHIFT, %r28 /* Clear any offset bits */ |
|
#endif |
|
|
|
/* Purge any old translation. Note that the FIC instruction |
|
* may use either the instruction or data TLB. Given that we |
|
* have a flat address space, it's not clear which TLB will be |
|
* used. So, we purge both entries. */ |
|
|
|
#ifdef CONFIG_PA20 |
|
pdtlb,l %r0(%r28) |
|
1: pitlb,l %r0(%sr4,%r28) |
|
ALTERNATIVE(1b, 1b+4, ALT_COND_NO_SPLIT_TLB, INSN_NOP) |
|
#else |
|
0: pdtlb %r0(%r28) |
|
1: pitlb %r0(%sr4,%r28) |
|
ALTERNATIVE(0b, 0b+4, ALT_COND_NO_SMP, INSN_PxTLB) |
|
ALTERNATIVE(1b, 1b+4, ALT_COND_NO_SMP, INSN_PxTLB) |
|
ALTERNATIVE(1b, 1b+4, ALT_COND_NO_SPLIT_TLB, INSN_NOP) |
|
#endif |
|
|
|
88: ldil L%icache_stride, %r1 |
|
ldw R%icache_stride(%r1), %r31 |
|
|
|
#ifdef CONFIG_64BIT |
|
depdi,z 1, 63-PAGE_SHIFT,1, %r25 |
|
#else |
|
depwi,z 1, 31-PAGE_SHIFT,1, %r25 |
|
#endif |
|
add %r28, %r25, %r25 |
|
sub %r25, %r31, %r25 |
|
|
|
/* fic only has the type 26 form on PA1.1, requiring an |
|
* explicit space specification, so use %sr4 */ |
|
1: fic,m %r31(%sr4,%r28) |
|
fic,m %r31(%sr4,%r28) |
|
fic,m %r31(%sr4,%r28) |
|
fic,m %r31(%sr4,%r28) |
|
fic,m %r31(%sr4,%r28) |
|
fic,m %r31(%sr4,%r28) |
|
fic,m %r31(%sr4,%r28) |
|
fic,m %r31(%sr4,%r28) |
|
fic,m %r31(%sr4,%r28) |
|
fic,m %r31(%sr4,%r28) |
|
fic,m %r31(%sr4,%r28) |
|
fic,m %r31(%sr4,%r28) |
|
fic,m %r31(%sr4,%r28) |
|
fic,m %r31(%sr4,%r28) |
|
fic,m %r31(%sr4,%r28) |
|
cmpb,COND(>>) %r25, %r28, 1b /* predict taken */ |
|
fic,m %r31(%sr4,%r28) |
|
|
|
89: ALTERNATIVE(88b, 89b, ALT_COND_NO_ICACHE, INSN_NOP) |
|
sync |
|
bv %r0(%r2) |
|
nop |
|
ENDPROC_CFI(flush_icache_page_asm) |
|
|
|
ENTRY_CFI(flush_kernel_dcache_page_asm) |
|
88: ldil L%dcache_stride, %r1 |
|
ldw R%dcache_stride(%r1), %r23 |
|
|
|
#ifdef CONFIG_64BIT |
|
depdi,z 1, 63-PAGE_SHIFT,1, %r25 |
|
#else |
|
depwi,z 1, 31-PAGE_SHIFT,1, %r25 |
|
#endif |
|
add %r26, %r25, %r25 |
|
sub %r25, %r23, %r25 |
|
|
|
1: fdc,m %r23(%r26) |
|
fdc,m %r23(%r26) |
|
fdc,m %r23(%r26) |
|
fdc,m %r23(%r26) |
|
fdc,m %r23(%r26) |
|
fdc,m %r23(%r26) |
|
fdc,m %r23(%r26) |
|
fdc,m %r23(%r26) |
|
fdc,m %r23(%r26) |
|
fdc,m %r23(%r26) |
|
fdc,m %r23(%r26) |
|
fdc,m %r23(%r26) |
|
fdc,m %r23(%r26) |
|
fdc,m %r23(%r26) |
|
fdc,m %r23(%r26) |
|
cmpb,COND(>>) %r25, %r26, 1b /* predict taken */ |
|
fdc,m %r23(%r26) |
|
|
|
89: ALTERNATIVE(88b, 89b, ALT_COND_NO_DCACHE, INSN_NOP) |
|
sync |
|
bv %r0(%r2) |
|
nop |
|
ENDPROC_CFI(flush_kernel_dcache_page_asm) |
|
|
|
ENTRY_CFI(purge_kernel_dcache_page_asm) |
|
88: ldil L%dcache_stride, %r1 |
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ldw R%dcache_stride(%r1), %r23 |
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|
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#ifdef CONFIG_64BIT |
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depdi,z 1, 63-PAGE_SHIFT,1, %r25 |
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#else |
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depwi,z 1, 31-PAGE_SHIFT,1, %r25 |
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#endif |
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add %r26, %r25, %r25 |
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sub %r25, %r23, %r25 |
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|
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1: pdc,m %r23(%r26) |
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pdc,m %r23(%r26) |
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pdc,m %r23(%r26) |
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pdc,m %r23(%r26) |
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pdc,m %r23(%r26) |
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pdc,m %r23(%r26) |
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pdc,m %r23(%r26) |
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pdc,m %r23(%r26) |
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pdc,m %r23(%r26) |
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pdc,m %r23(%r26) |
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pdc,m %r23(%r26) |
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pdc,m %r23(%r26) |
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pdc,m %r23(%r26) |
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pdc,m %r23(%r26) |
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pdc,m %r23(%r26) |
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cmpb,COND(>>) %r25, %r26, 1b /* predict taken */ |
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pdc,m %r23(%r26) |
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|
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89: ALTERNATIVE(88b, 89b, ALT_COND_NO_DCACHE, INSN_NOP) |
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sync |
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bv %r0(%r2) |
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nop |
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ENDPROC_CFI(purge_kernel_dcache_page_asm) |
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|
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ENTRY_CFI(flush_user_dcache_range_asm) |
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88: ldil L%dcache_stride, %r1 |
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ldw R%dcache_stride(%r1), %r23 |
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ldo -1(%r23), %r21 |
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ANDCM %r26, %r21, %r26 |
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|
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#ifdef CONFIG_64BIT |
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depd,z %r23, 59, 60, %r21 |
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#else |
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depw,z %r23, 27, 28, %r21 |
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#endif |
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add %r26, %r21, %r22 |
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cmpb,COND(>>),n %r22, %r25, 2f /* predict not taken */ |
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1: add %r22, %r21, %r22 |
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fdc,m %r23(%sr3, %r26) |
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fdc,m %r23(%sr3, %r26) |
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fdc,m %r23(%sr3, %r26) |
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fdc,m %r23(%sr3, %r26) |
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fdc,m %r23(%sr3, %r26) |
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fdc,m %r23(%sr3, %r26) |
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fdc,m %r23(%sr3, %r26) |
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fdc,m %r23(%sr3, %r26) |
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fdc,m %r23(%sr3, %r26) |
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fdc,m %r23(%sr3, %r26) |
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fdc,m %r23(%sr3, %r26) |
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fdc,m %r23(%sr3, %r26) |
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fdc,m %r23(%sr3, %r26) |
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fdc,m %r23(%sr3, %r26) |
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fdc,m %r23(%sr3, %r26) |
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cmpb,COND(<<=) %r22, %r25, 1b /* predict taken */ |
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fdc,m %r23(%sr3, %r26) |
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|
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2: cmpb,COND(>>),n %r25, %r26, 2b |
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fdc,m %r23(%sr3, %r26) |
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|
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89: ALTERNATIVE(88b, 89b, ALT_COND_NO_DCACHE, INSN_NOP) |
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sync |
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bv %r0(%r2) |
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nop |
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ENDPROC_CFI(flush_user_dcache_range_asm) |
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ENTRY_CFI(flush_kernel_dcache_range_asm) |
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88: ldil L%dcache_stride, %r1 |
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ldw R%dcache_stride(%r1), %r23 |
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ldo -1(%r23), %r21 |
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ANDCM %r26, %r21, %r26 |
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#ifdef CONFIG_64BIT |
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depd,z %r23, 59, 60, %r21 |
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#else |
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depw,z %r23, 27, 28, %r21 |
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#endif |
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add %r26, %r21, %r22 |
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cmpb,COND(>>),n %r22, %r25, 2f /* predict not taken */ |
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1: add %r22, %r21, %r22 |
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fdc,m %r23(%r26) |
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fdc,m %r23(%r26) |
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fdc,m %r23(%r26) |
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fdc,m %r23(%r26) |
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fdc,m %r23(%r26) |
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fdc,m %r23(%r26) |
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fdc,m %r23(%r26) |
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fdc,m %r23(%r26) |
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fdc,m %r23(%r26) |
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fdc,m %r23(%r26) |
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fdc,m %r23(%r26) |
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fdc,m %r23(%r26) |
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fdc,m %r23(%r26) |
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fdc,m %r23(%r26) |
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fdc,m %r23(%r26) |
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cmpb,COND(<<=) %r22, %r25, 1b /* predict taken */ |
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fdc,m %r23(%r26) |
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|
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2: cmpb,COND(>>),n %r25, %r26, 2b /* predict taken */ |
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fdc,m %r23(%r26) |
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|
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sync |
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89: ALTERNATIVE(88b, 89b, ALT_COND_NO_DCACHE, INSN_NOP) |
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syncdma |
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bv %r0(%r2) |
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nop |
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ENDPROC_CFI(flush_kernel_dcache_range_asm) |
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ENTRY_CFI(purge_kernel_dcache_range_asm) |
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88: ldil L%dcache_stride, %r1 |
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ldw R%dcache_stride(%r1), %r23 |
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ldo -1(%r23), %r21 |
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ANDCM %r26, %r21, %r26 |
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#ifdef CONFIG_64BIT |
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depd,z %r23, 59, 60, %r21 |
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#else |
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depw,z %r23, 27, 28, %r21 |
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#endif |
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add %r26, %r21, %r22 |
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cmpb,COND(>>),n %r22, %r25, 2f /* predict not taken */ |
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1: add %r22, %r21, %r22 |
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pdc,m %r23(%r26) |
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pdc,m %r23(%r26) |
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pdc,m %r23(%r26) |
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pdc,m %r23(%r26) |
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pdc,m %r23(%r26) |
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pdc,m %r23(%r26) |
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pdc,m %r23(%r26) |
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pdc,m %r23(%r26) |
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pdc,m %r23(%r26) |
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pdc,m %r23(%r26) |
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pdc,m %r23(%r26) |
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pdc,m %r23(%r26) |
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pdc,m %r23(%r26) |
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pdc,m %r23(%r26) |
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pdc,m %r23(%r26) |
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cmpb,COND(<<=) %r22, %r25, 1b /* predict taken */ |
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pdc,m %r23(%r26) |
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2: cmpb,COND(>>),n %r25, %r26, 2b /* predict taken */ |
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pdc,m %r23(%r26) |
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sync |
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89: ALTERNATIVE(88b, 89b, ALT_COND_NO_DCACHE, INSN_NOP) |
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syncdma |
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bv %r0(%r2) |
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nop |
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ENDPROC_CFI(purge_kernel_dcache_range_asm) |
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ENTRY_CFI(flush_user_icache_range_asm) |
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88: ldil L%icache_stride, %r1 |
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ldw R%icache_stride(%r1), %r23 |
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ldo -1(%r23), %r21 |
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ANDCM %r26, %r21, %r26 |
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#ifdef CONFIG_64BIT |
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depd,z %r23, 59, 60, %r21 |
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#else |
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depw,z %r23, 27, 28, %r21 |
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#endif |
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add %r26, %r21, %r22 |
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cmpb,COND(>>),n %r22, %r25, 2f /* predict not taken */ |
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1: add %r22, %r21, %r22 |
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fic,m %r23(%sr3, %r26) |
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fic,m %r23(%sr3, %r26) |
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fic,m %r23(%sr3, %r26) |
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fic,m %r23(%sr3, %r26) |
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fic,m %r23(%sr3, %r26) |
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fic,m %r23(%sr3, %r26) |
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fic,m %r23(%sr3, %r26) |
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fic,m %r23(%sr3, %r26) |
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fic,m %r23(%sr3, %r26) |
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fic,m %r23(%sr3, %r26) |
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fic,m %r23(%sr3, %r26) |
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fic,m %r23(%sr3, %r26) |
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fic,m %r23(%sr3, %r26) |
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fic,m %r23(%sr3, %r26) |
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fic,m %r23(%sr3, %r26) |
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cmpb,COND(<<=) %r22, %r25, 1b /* predict taken */ |
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fic,m %r23(%sr3, %r26) |
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2: cmpb,COND(>>),n %r25, %r26, 2b |
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fic,m %r23(%sr3, %r26) |
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89: ALTERNATIVE(88b, 89b, ALT_COND_NO_ICACHE, INSN_NOP) |
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sync |
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bv %r0(%r2) |
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nop |
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ENDPROC_CFI(flush_user_icache_range_asm) |
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ENTRY_CFI(flush_kernel_icache_page) |
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88: ldil L%icache_stride, %r1 |
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ldw R%icache_stride(%r1), %r23 |
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|
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#ifdef CONFIG_64BIT |
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depdi,z 1, 63-PAGE_SHIFT,1, %r25 |
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#else |
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depwi,z 1, 31-PAGE_SHIFT,1, %r25 |
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#endif |
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add %r26, %r25, %r25 |
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sub %r25, %r23, %r25 |
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|
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1: fic,m %r23(%sr4, %r26) |
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fic,m %r23(%sr4, %r26) |
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fic,m %r23(%sr4, %r26) |
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fic,m %r23(%sr4, %r26) |
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fic,m %r23(%sr4, %r26) |
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fic,m %r23(%sr4, %r26) |
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fic,m %r23(%sr4, %r26) |
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fic,m %r23(%sr4, %r26) |
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fic,m %r23(%sr4, %r26) |
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fic,m %r23(%sr4, %r26) |
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fic,m %r23(%sr4, %r26) |
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fic,m %r23(%sr4, %r26) |
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fic,m %r23(%sr4, %r26) |
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fic,m %r23(%sr4, %r26) |
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fic,m %r23(%sr4, %r26) |
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cmpb,COND(>>) %r25, %r26, 1b /* predict taken */ |
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fic,m %r23(%sr4, %r26) |
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|
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89: ALTERNATIVE(88b, 89b, ALT_COND_NO_ICACHE, INSN_NOP) |
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sync |
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bv %r0(%r2) |
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nop |
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ENDPROC_CFI(flush_kernel_icache_page) |
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ENTRY_CFI(flush_kernel_icache_range_asm) |
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88: ldil L%icache_stride, %r1 |
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ldw R%icache_stride(%r1), %r23 |
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ldo -1(%r23), %r21 |
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ANDCM %r26, %r21, %r26 |
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|
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#ifdef CONFIG_64BIT |
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depd,z %r23, 59, 60, %r21 |
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#else |
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depw,z %r23, 27, 28, %r21 |
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#endif |
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add %r26, %r21, %r22 |
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cmpb,COND(>>),n %r22, %r25, 2f /* predict not taken */ |
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1: add %r22, %r21, %r22 |
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fic,m %r23(%sr4, %r26) |
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fic,m %r23(%sr4, %r26) |
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fic,m %r23(%sr4, %r26) |
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fic,m %r23(%sr4, %r26) |
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fic,m %r23(%sr4, %r26) |
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fic,m %r23(%sr4, %r26) |
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fic,m %r23(%sr4, %r26) |
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fic,m %r23(%sr4, %r26) |
|
fic,m %r23(%sr4, %r26) |
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fic,m %r23(%sr4, %r26) |
|
fic,m %r23(%sr4, %r26) |
|
fic,m %r23(%sr4, %r26) |
|
fic,m %r23(%sr4, %r26) |
|
fic,m %r23(%sr4, %r26) |
|
fic,m %r23(%sr4, %r26) |
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cmpb,COND(<<=) %r22, %r25, 1b /* predict taken */ |
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fic,m %r23(%sr4, %r26) |
|
|
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2: cmpb,COND(>>),n %r25, %r26, 2b /* predict taken */ |
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fic,m %r23(%sr4, %r26) |
|
|
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89: ALTERNATIVE(88b, 89b, ALT_COND_NO_ICACHE, INSN_NOP) |
|
sync |
|
bv %r0(%r2) |
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nop |
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ENDPROC_CFI(flush_kernel_icache_range_asm) |
|
|
|
__INIT |
|
|
|
/* align should cover use of rfi in disable_sr_hashing_asm and |
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* srdis_done. |
|
*/ |
|
.align 256 |
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ENTRY_CFI(disable_sr_hashing_asm) |
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/* |
|
* Switch to real mode |
|
*/ |
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/* pcxt_ssm_bug */ |
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rsm PSW_SM_I, %r0 |
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load32 PA(1f), %r1 |
|
nop |
|
nop |
|
nop |
|
nop |
|
nop |
|
|
|
rsm PSW_SM_Q, %r0 /* prep to load iia queue */ |
|
mtctl %r0, %cr17 /* Clear IIASQ tail */ |
|
mtctl %r0, %cr17 /* Clear IIASQ head */ |
|
mtctl %r1, %cr18 /* IIAOQ head */ |
|
ldo 4(%r1), %r1 |
|
mtctl %r1, %cr18 /* IIAOQ tail */ |
|
load32 REAL_MODE_PSW, %r1 |
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mtctl %r1, %ipsw |
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rfi |
|
nop |
|
|
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1: cmpib,=,n SRHASH_PCXST, %r26,srdis_pcxs |
|
cmpib,=,n SRHASH_PCXL, %r26,srdis_pcxl |
|
cmpib,=,n SRHASH_PA20, %r26,srdis_pa20 |
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b,n srdis_done |
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|
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srdis_pcxs: |
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|
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/* Disable Space Register Hashing for PCXS,PCXT,PCXT' */ |
|
|
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.word 0x141c1a00 /* mfdiag %dr0, %r28 */ |
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.word 0x141c1a00 /* must issue twice */ |
|
depwi 0,18,1, %r28 /* Clear DHE (dcache hash enable) */ |
|
depwi 0,20,1, %r28 /* Clear IHE (icache hash enable) */ |
|
.word 0x141c1600 /* mtdiag %r28, %dr0 */ |
|
.word 0x141c1600 /* must issue twice */ |
|
b,n srdis_done |
|
|
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srdis_pcxl: |
|
|
|
/* Disable Space Register Hashing for PCXL */ |
|
|
|
.word 0x141c0600 /* mfdiag %dr0, %r28 */ |
|
depwi 0,28,2, %r28 /* Clear DHASH_EN & IHASH_EN */ |
|
.word 0x141c0240 /* mtdiag %r28, %dr0 */ |
|
b,n srdis_done |
|
|
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srdis_pa20: |
|
|
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/* Disable Space Register Hashing for PCXU,PCXU+,PCXW,PCXW+,PCXW2 */ |
|
|
|
.word 0x144008bc /* mfdiag %dr2, %r28 */ |
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depdi 0, 54,1, %r28 /* clear DIAG_SPHASH_ENAB (bit 54) */ |
|
.word 0x145c1840 /* mtdiag %r28, %dr2 */ |
|
|
|
|
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srdis_done: |
|
/* Switch back to virtual mode */ |
|
rsm PSW_SM_I, %r0 /* prep to load iia queue */ |
|
load32 2f, %r1 |
|
nop |
|
nop |
|
nop |
|
nop |
|
nop |
|
|
|
rsm PSW_SM_Q, %r0 /* prep to load iia queue */ |
|
mtctl %r0, %cr17 /* Clear IIASQ tail */ |
|
mtctl %r0, %cr17 /* Clear IIASQ head */ |
|
mtctl %r1, %cr18 /* IIAOQ head */ |
|
ldo 4(%r1), %r1 |
|
mtctl %r1, %cr18 /* IIAOQ tail */ |
|
load32 KERNEL_PSW, %r1 |
|
mtctl %r1, %ipsw |
|
rfi |
|
nop |
|
|
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2: bv %r0(%r2) |
|
nop |
|
ENDPROC_CFI(disable_sr_hashing_asm) |
|
|
|
.end
|
|
|