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241 lines
9.7 KiB
241 lines
9.7 KiB
/* SPDX-License-Identifier: GPL-2.0 */ |
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/* |
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* include/asm-m68k/dma.h |
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* |
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* Copyright 1995 (C) David S. Miller ([email protected]) |
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* |
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* Hacked to fit Sun3x needs by Thomas Bogendoerfer |
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*/ |
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#ifndef __M68K_DVMA_H |
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#define __M68K_DVMA_H |
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#define DVMA_PAGE_SHIFT 13 |
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#define DVMA_PAGE_SIZE (1UL << DVMA_PAGE_SHIFT) |
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#define DVMA_PAGE_MASK (~(DVMA_PAGE_SIZE-1)) |
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#define DVMA_PAGE_ALIGN(addr) ALIGN(addr, DVMA_PAGE_SIZE) |
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extern void dvma_init(void); |
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extern int dvma_map_iommu(unsigned long kaddr, unsigned long baddr, |
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int len); |
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#define dvma_malloc(x) dvma_malloc_align(x, 0) |
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#define dvma_map(x, y) dvma_map_align(x, y, 0) |
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#define dvma_map_vme(x, y) (dvma_map(x, y) & 0xfffff) |
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#define dvma_map_align_vme(x, y, z) (dvma_map_align (x, y, z) & 0xfffff) |
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extern unsigned long dvma_map_align(unsigned long kaddr, int len, |
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int align); |
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extern void *dvma_malloc_align(unsigned long len, unsigned long align); |
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extern void dvma_unmap(void *baddr); |
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extern void dvma_free(void *vaddr); |
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#ifdef CONFIG_SUN3 |
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/* sun3 dvma page support */ |
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/* memory and pmegs potentially reserved for dvma */ |
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#define DVMA_PMEG_START 10 |
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#define DVMA_PMEG_END 16 |
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#define DVMA_START 0xf00000 |
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#define DVMA_END 0xfe0000 |
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#define DVMA_SIZE (DVMA_END-DVMA_START) |
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#define IOMMU_TOTAL_ENTRIES 128 |
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#define IOMMU_ENTRIES 120 |
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/* empirical kludge -- dvma regions only seem to work right on 0x10000 |
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byte boundaries */ |
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#define DVMA_REGION_SIZE 0x10000 |
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#define DVMA_ALIGN(addr) (((addr)+DVMA_REGION_SIZE-1) & \ |
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~(DVMA_REGION_SIZE-1)) |
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/* virt <-> phys conversions */ |
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#define dvma_vtop(x) ((unsigned long)(x) & 0xffffff) |
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#define dvma_ptov(x) ((unsigned long)(x) | 0xf000000) |
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#define dvma_vtovme(x) ((unsigned long)(x) & 0x00fffff) |
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#define dvma_vmetov(x) ((unsigned long)(x) | 0xff00000) |
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#define dvma_vtob(x) dvma_vtop(x) |
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#define dvma_btov(x) dvma_ptov(x) |
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static inline int dvma_map_cpu(unsigned long kaddr, unsigned long vaddr, |
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int len) |
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{ |
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return 0; |
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} |
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#else /* Sun3x */ |
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/* sun3x dvma page support */ |
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#define DVMA_START 0x0 |
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#define DVMA_END 0xf00000 |
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#define DVMA_SIZE (DVMA_END-DVMA_START) |
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#define IOMMU_TOTAL_ENTRIES 2048 |
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/* the prom takes the top meg */ |
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#define IOMMU_ENTRIES (IOMMU_TOTAL_ENTRIES - 0x80) |
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#define dvma_vtob(x) ((unsigned long)(x) & 0x00ffffff) |
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#define dvma_btov(x) ((unsigned long)(x) | 0xff000000) |
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extern int dvma_map_cpu(unsigned long kaddr, unsigned long vaddr, int len); |
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/* everything below this line is specific to dma used for the onboard |
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ESP scsi on sun3x */ |
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/* Structure to describe the current status of DMA registers on the Sparc */ |
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struct sparc_dma_registers { |
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__volatile__ unsigned long cond_reg; /* DMA condition register */ |
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__volatile__ unsigned long st_addr; /* Start address of this transfer */ |
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__volatile__ unsigned long cnt; /* How many bytes to transfer */ |
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__volatile__ unsigned long dma_test; /* DMA test register */ |
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}; |
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/* DVMA chip revisions */ |
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enum dvma_rev { |
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dvmarev0, |
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dvmaesc1, |
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dvmarev1, |
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dvmarev2, |
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dvmarev3, |
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dvmarevplus, |
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dvmahme |
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}; |
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#define DMA_HASCOUNT(rev) ((rev)==dvmaesc1) |
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/* Linux DMA information structure, filled during probe. */ |
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struct Linux_SBus_DMA { |
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struct Linux_SBus_DMA *next; |
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struct linux_sbus_device *SBus_dev; |
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struct sparc_dma_registers *regs; |
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/* Status, misc info */ |
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int node; /* Prom node for this DMA device */ |
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int running; /* Are we doing DMA now? */ |
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int allocated; /* Are we "owned" by anyone yet? */ |
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/* Transfer information. */ |
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unsigned long addr; /* Start address of current transfer */ |
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int nbytes; /* Size of current transfer */ |
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int realbytes; /* For splitting up large transfers, etc. */ |
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/* DMA revision */ |
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enum dvma_rev revision; |
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}; |
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extern struct Linux_SBus_DMA *dma_chain; |
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/* Broken hardware... */ |
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#define DMA_ISBROKEN(dma) ((dma)->revision == dvmarev1) |
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#define DMA_ISESC1(dma) ((dma)->revision == dvmaesc1) |
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/* Fields in the cond_reg register */ |
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/* First, the version identification bits */ |
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#define DMA_DEVICE_ID 0xf0000000 /* Device identification bits */ |
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#define DMA_VERS0 0x00000000 /* Sunray DMA version */ |
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#define DMA_ESCV1 0x40000000 /* DMA ESC Version 1 */ |
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#define DMA_VERS1 0x80000000 /* DMA rev 1 */ |
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#define DMA_VERS2 0xa0000000 /* DMA rev 2 */ |
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#define DMA_VERHME 0xb0000000 /* DMA hme gate array */ |
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#define DMA_VERSPLUS 0x90000000 /* DMA rev 1 PLUS */ |
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#define DMA_HNDL_INTR 0x00000001 /* An IRQ needs to be handled */ |
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#define DMA_HNDL_ERROR 0x00000002 /* We need to take an error */ |
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#define DMA_FIFO_ISDRAIN 0x0000000c /* The DMA FIFO is draining */ |
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#define DMA_INT_ENAB 0x00000010 /* Turn on interrupts */ |
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#define DMA_FIFO_INV 0x00000020 /* Invalidate the FIFO */ |
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#define DMA_ACC_SZ_ERR 0x00000040 /* The access size was bad */ |
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#define DMA_FIFO_STDRAIN 0x00000040 /* DMA_VERS1 Drain the FIFO */ |
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#define DMA_RST_SCSI 0x00000080 /* Reset the SCSI controller */ |
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#define DMA_RST_ENET DMA_RST_SCSI /* Reset the ENET controller */ |
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#define DMA_ST_WRITE 0x00000100 /* write from device to memory */ |
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#define DMA_ENABLE 0x00000200 /* Fire up DMA, handle requests */ |
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#define DMA_PEND_READ 0x00000400 /* DMA_VERS1/0/PLUS Pending Read */ |
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#define DMA_ESC_BURST 0x00000800 /* 1=16byte 0=32byte */ |
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#define DMA_READ_AHEAD 0x00001800 /* DMA read ahead partial longword */ |
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#define DMA_DSBL_RD_DRN 0x00001000 /* No EC drain on slave reads */ |
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#define DMA_BCNT_ENAB 0x00002000 /* If on, use the byte counter */ |
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#define DMA_TERM_CNTR 0x00004000 /* Terminal counter */ |
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#define DMA_CSR_DISAB 0x00010000 /* No FIFO drains during csr */ |
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#define DMA_SCSI_DISAB 0x00020000 /* No FIFO drains during reg */ |
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#define DMA_DSBL_WR_INV 0x00020000 /* No EC inval. on slave writes */ |
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#define DMA_ADD_ENABLE 0x00040000 /* Special ESC DVMA optimization */ |
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#define DMA_E_BURST8 0x00040000 /* ENET: SBUS r/w burst size */ |
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#define DMA_BRST_SZ 0x000c0000 /* SCSI: SBUS r/w burst size */ |
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#define DMA_BRST64 0x00080000 /* SCSI: 64byte bursts (HME on UltraSparc only) */ |
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#define DMA_BRST32 0x00040000 /* SCSI: 32byte bursts */ |
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#define DMA_BRST16 0x00000000 /* SCSI: 16byte bursts */ |
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#define DMA_BRST0 0x00080000 /* SCSI: no bursts (non-HME gate arrays) */ |
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#define DMA_ADDR_DISAB 0x00100000 /* No FIFO drains during addr */ |
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#define DMA_2CLKS 0x00200000 /* Each transfer = 2 clock ticks */ |
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#define DMA_3CLKS 0x00400000 /* Each transfer = 3 clock ticks */ |
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#define DMA_EN_ENETAUI DMA_3CLKS /* Put lance into AUI-cable mode */ |
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#define DMA_CNTR_DISAB 0x00800000 /* No IRQ when DMA_TERM_CNTR set */ |
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#define DMA_AUTO_NADDR 0x01000000 /* Use "auto nxt addr" feature */ |
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#define DMA_SCSI_ON 0x02000000 /* Enable SCSI dma */ |
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#define DMA_PARITY_OFF 0x02000000 /* HME: disable parity checking */ |
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#define DMA_LOADED_ADDR 0x04000000 /* Address has been loaded */ |
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#define DMA_LOADED_NADDR 0x08000000 /* Next address has been loaded */ |
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/* Values describing the burst-size property from the PROM */ |
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#define DMA_BURST1 0x01 |
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#define DMA_BURST2 0x02 |
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#define DMA_BURST4 0x04 |
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#define DMA_BURST8 0x08 |
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#define DMA_BURST16 0x10 |
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#define DMA_BURST32 0x20 |
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#define DMA_BURST64 0x40 |
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#define DMA_BURSTBITS 0x7f |
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/* Determine highest possible final transfer address given a base */ |
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#define DMA_MAXEND(addr) (0x01000000UL-(((unsigned long)(addr))&0x00ffffffUL)) |
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/* Yes, I hack a lot of elisp in my spare time... */ |
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#define DMA_ERROR_P(regs) ((((regs)->cond_reg) & DMA_HNDL_ERROR)) |
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#define DMA_IRQ_P(regs) ((((regs)->cond_reg) & (DMA_HNDL_INTR | DMA_HNDL_ERROR))) |
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#define DMA_WRITE_P(regs) ((((regs)->cond_reg) & DMA_ST_WRITE)) |
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#define DMA_OFF(regs) ((((regs)->cond_reg) &= (~DMA_ENABLE))) |
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#define DMA_INTSOFF(regs) ((((regs)->cond_reg) &= (~DMA_INT_ENAB))) |
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#define DMA_INTSON(regs) ((((regs)->cond_reg) |= (DMA_INT_ENAB))) |
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#define DMA_PUNTFIFO(regs) ((((regs)->cond_reg) |= DMA_FIFO_INV)) |
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#define DMA_SETSTART(regs, addr) ((((regs)->st_addr) = (char *) addr)) |
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#define DMA_BEGINDMA_W(regs) \ |
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((((regs)->cond_reg |= (DMA_ST_WRITE|DMA_ENABLE|DMA_INT_ENAB)))) |
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#define DMA_BEGINDMA_R(regs) \ |
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((((regs)->cond_reg |= ((DMA_ENABLE|DMA_INT_ENAB)&(~DMA_ST_WRITE))))) |
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/* For certain DMA chips, we need to disable ints upon irq entry |
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* and turn them back on when we are done. So in any ESP interrupt |
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* handler you *must* call DMA_IRQ_ENTRY upon entry and DMA_IRQ_EXIT |
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* when leaving the handler. You have been warned... |
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*/ |
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#define DMA_IRQ_ENTRY(dma, dregs) do { \ |
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if(DMA_ISBROKEN(dma)) DMA_INTSOFF(dregs); \ |
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} while (0) |
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#define DMA_IRQ_EXIT(dma, dregs) do { \ |
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if(DMA_ISBROKEN(dma)) DMA_INTSON(dregs); \ |
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} while(0) |
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/* Reset the friggin' thing... */ |
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#define DMA_RESET(dma) do { \ |
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struct sparc_dma_registers *regs = dma->regs; \ |
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/* Let the current FIFO drain itself */ \ |
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sparc_dma_pause(regs, (DMA_FIFO_ISDRAIN)); \ |
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/* Reset the logic */ \ |
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regs->cond_reg |= (DMA_RST_SCSI); /* assert */ \ |
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__delay(400); /* let the bits set ;) */ \ |
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regs->cond_reg &= ~(DMA_RST_SCSI); /* de-assert */ \ |
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sparc_dma_enable_interrupts(regs); /* Re-enable interrupts */ \ |
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/* Enable FAST transfers if available */ \ |
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if(dma->revision>dvmarev1) regs->cond_reg |= DMA_3CLKS; \ |
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dma->running = 0; \ |
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} while(0) |
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#endif /* !CONFIG_SUN3 */ |
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#endif /* !(__M68K_DVMA_H) */
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