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813 lines
20 KiB
813 lines
20 KiB
/* |
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** linux/atarihw.h -- This header defines some macros and pointers for |
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** the various Atari custom hardware registers. |
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** |
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** Copyright 1994 by Björn Brauel |
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** |
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** 5/1/94 Roman Hodek: |
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** Added definitions for TT specific chips. |
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** |
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** 1996-09-13 lars brinkhoff <[email protected]>: |
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** Finally added definitions for the matrix/codec and the DSP56001 host |
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** interface. |
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** |
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** This file is subject to the terms and conditions of the GNU General Public |
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** License. See the file COPYING in the main directory of this archive |
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** for more details. |
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** |
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*/ |
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|
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#ifndef _LINUX_ATARIHW_H_ |
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#define _LINUX_ATARIHW_H_ |
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|
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#include <linux/types.h> |
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#include <asm/bootinfo-atari.h> |
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#include <asm/kmap.h> |
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extern u_long atari_mch_cookie; |
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extern u_long atari_mch_type; |
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extern u_long atari_switches; |
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extern int atari_rtc_year_offset; |
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extern int atari_dont_touch_floppy_select; |
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extern int atari_SCC_reset_done; |
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extern ssize_t atari_nvram_read(char *, size_t, loff_t *); |
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extern ssize_t atari_nvram_write(char *, size_t, loff_t *); |
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extern ssize_t atari_nvram_get_size(void); |
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extern long atari_nvram_set_checksum(void); |
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extern long atari_nvram_initialize(void); |
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|
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/* convenience macros for testing machine type */ |
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#define MACH_IS_ST ((atari_mch_cookie >> 16) == ATARI_MCH_ST) |
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#define MACH_IS_STE ((atari_mch_cookie >> 16) == ATARI_MCH_STE && \ |
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(atari_mch_cookie & 0xffff) == 0) |
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#define MACH_IS_MSTE ((atari_mch_cookie >> 16) == ATARI_MCH_STE && \ |
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(atari_mch_cookie & 0xffff) == 0x10) |
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#define MACH_IS_TT ((atari_mch_cookie >> 16) == ATARI_MCH_TT) |
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#define MACH_IS_FALCON ((atari_mch_cookie >> 16) == ATARI_MCH_FALCON) |
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#define MACH_IS_MEDUSA (atari_mch_type == ATARI_MACH_MEDUSA) |
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#define MACH_IS_AB40 (atari_mch_type == ATARI_MACH_AB40) |
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|
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/* values for atari_switches */ |
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#define ATARI_SWITCH_IKBD 0x01 |
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#define ATARI_SWITCH_MIDI 0x02 |
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#define ATARI_SWITCH_SND6 0x04 |
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#define ATARI_SWITCH_SND7 0x08 |
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#define ATARI_SWITCH_OVSC_SHIFT 16 |
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#define ATARI_SWITCH_OVSC_IKBD (ATARI_SWITCH_IKBD << ATARI_SWITCH_OVSC_SHIFT) |
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#define ATARI_SWITCH_OVSC_MIDI (ATARI_SWITCH_MIDI << ATARI_SWITCH_OVSC_SHIFT) |
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#define ATARI_SWITCH_OVSC_SND6 (ATARI_SWITCH_SND6 << ATARI_SWITCH_OVSC_SHIFT) |
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#define ATARI_SWITCH_OVSC_SND7 (ATARI_SWITCH_SND7 << ATARI_SWITCH_OVSC_SHIFT) |
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#define ATARI_SWITCH_OVSC_MASK 0xffff0000 |
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|
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/* |
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* Define several Hardware-Chips for indication so that for the ATARI we do |
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* no longer decide whether it is a Falcon or other machine . It's just |
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* important what hardware the machine uses |
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*/ |
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|
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/* ++roman 08/08/95: rewritten from ORing constants to a C bitfield */ |
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#define ATARIHW_DECLARE(name) unsigned name : 1 |
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#define ATARIHW_SET(name) (atari_hw_present.name = 1) |
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#define ATARIHW_PRESENT(name) (atari_hw_present.name) |
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struct atari_hw_present { |
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/* video hardware */ |
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ATARIHW_DECLARE(STND_SHIFTER); /* ST-Shifter - no base low ! */ |
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ATARIHW_DECLARE(EXTD_SHIFTER); /* STe-Shifter - 24 bit address */ |
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ATARIHW_DECLARE(TT_SHIFTER); /* TT-Shifter */ |
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ATARIHW_DECLARE(VIDEL_SHIFTER); /* Falcon-Shifter */ |
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/* sound hardware */ |
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ATARIHW_DECLARE(YM_2149); /* Yamaha YM 2149 */ |
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ATARIHW_DECLARE(PCM_8BIT); /* PCM-Sound in STe-ATARI */ |
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ATARIHW_DECLARE(CODEC); /* CODEC Sound (Falcon) */ |
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/* disk storage interfaces */ |
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ATARIHW_DECLARE(TT_SCSI); /* Directly mapped NCR5380 */ |
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ATARIHW_DECLARE(ST_SCSI); /* NCR5380 via ST-DMA (Falcon) */ |
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ATARIHW_DECLARE(ACSI); /* Standard ACSI like in STs */ |
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ATARIHW_DECLARE(IDE); /* IDE Interface */ |
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ATARIHW_DECLARE(FDCSPEED); /* 8/16 MHz switch for FDC */ |
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/* other I/O hardware */ |
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ATARIHW_DECLARE(ST_MFP); /* The ST-MFP (there should be no Atari |
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without it... but who knows?) */ |
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ATARIHW_DECLARE(TT_MFP); /* 2nd MFP */ |
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ATARIHW_DECLARE(SCC); /* Serial Communications Contr. */ |
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ATARIHW_DECLARE(ST_ESCC); /* SCC Z83230 in an ST */ |
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ATARIHW_DECLARE(ANALOG_JOY); /* Paddle Interface for STe |
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and Falcon */ |
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ATARIHW_DECLARE(MICROWIRE); /* Microwire Interface */ |
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/* DMA */ |
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ATARIHW_DECLARE(STND_DMA); /* 24 Bit limited ST-DMA */ |
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ATARIHW_DECLARE(EXTD_DMA); /* 32 Bit ST-DMA */ |
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ATARIHW_DECLARE(SCSI_DMA); /* DMA for the NCR5380 */ |
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ATARIHW_DECLARE(SCC_DMA); /* DMA for the SCC */ |
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/* real time clocks */ |
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ATARIHW_DECLARE(TT_CLK); /* TT compatible clock chip */ |
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ATARIHW_DECLARE(MSTE_CLK); /* Mega ST(E) clock chip */ |
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/* supporting hardware */ |
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ATARIHW_DECLARE(SCU); /* System Control Unit */ |
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ATARIHW_DECLARE(BLITTER); /* Blitter */ |
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ATARIHW_DECLARE(VME); /* VME Bus */ |
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ATARIHW_DECLARE(DSP56K); /* DSP56k processor in Falcon */ |
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}; |
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extern struct atari_hw_present atari_hw_present; |
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/* Reading the MFP port register gives a machine independent delay, since the |
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* MFP always has a 8 MHz clock. This avoids problems with the varying length |
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* of nops on various machines. Somebody claimed that the tstb takes 600 ns. |
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*/ |
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#define MFPDELAY() \ |
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__asm__ __volatile__ ( "tstb %0" : : "m" (st_mfp.par_dt_reg) : "cc" ); |
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/* Do cache push/invalidate for DMA read/write. This function obeys the |
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* snooping on some machines (Medusa) and processors: The Medusa itself can |
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* snoop, but only the '040 can source data from its cache to DMA writes i.e., |
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* reads from memory). Both '040 and '060 invalidate cache entries on snooped |
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* DMA reads (i.e., writes to memory). |
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*/ |
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#include <linux/mm.h> |
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#include <asm/cacheflush.h> |
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static inline void dma_cache_maintenance( unsigned long paddr, |
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unsigned long len, |
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int writeflag ) |
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{ |
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if (writeflag) { |
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if (!MACH_IS_MEDUSA || CPU_IS_060) |
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cache_push( paddr, len ); |
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} |
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else { |
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if (!MACH_IS_MEDUSA) |
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cache_clear( paddr, len ); |
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} |
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} |
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/* |
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** Shifter |
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*/ |
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#define ST_LOW 0 |
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#define ST_MID 1 |
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#define ST_HIGH 2 |
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#define TT_LOW 7 |
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#define TT_MID 4 |
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#define TT_HIGH 6 |
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#define SHF_BAS (0xffff8200) |
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struct SHIFTER_ST |
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{ |
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u_char pad1; |
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u_char bas_hi; |
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u_char pad2; |
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u_char bas_md; |
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u_char pad3; |
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u_char volatile vcounthi; |
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u_char pad4; |
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u_char volatile vcountmid; |
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u_char pad5; |
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u_char volatile vcountlow; |
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u_char volatile syncmode; |
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u_char pad6; |
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u_char pad7; |
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u_char bas_lo; |
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}; |
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# define shifter_st ((*(volatile struct SHIFTER_ST *)SHF_BAS)) |
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#define SHF_FBAS (0xffff820e) |
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struct SHIFTER_F030 |
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{ |
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u_short off_next; |
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u_short scn_width; |
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}; |
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# define shifter_f030 ((*(volatile struct SHIFTER_F030 *)SHF_FBAS)) |
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#define SHF_TBAS (0xffff8200) |
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struct SHIFTER_TT { |
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u_char char_dummy0; |
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u_char bas_hi; /* video mem base addr, high and mid byte */ |
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u_char char_dummy1; |
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u_char bas_md; |
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u_char char_dummy2; |
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u_char vcount_hi; /* pointer to currently displayed byte */ |
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u_char char_dummy3; |
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u_char vcount_md; |
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u_char char_dummy4; |
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u_char vcount_lo; |
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u_short st_sync; /* ST compatible sync mode register, unused */ |
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u_char char_dummy5; |
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u_char bas_lo; /* video mem addr, low byte */ |
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u_char char_dummy6[2+3*16]; |
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/* $ffff8240: */ |
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u_short color_reg[16]; /* 16 color registers */ |
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u_char st_shiftmode; /* ST compatible shift mode register, unused */ |
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u_char char_dummy7; |
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u_short tt_shiftmode; /* TT shift mode register */ |
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}; |
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#define shifter_tt ((*(volatile struct SHIFTER_TT *)SHF_TBAS)) |
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/* values for shifter_tt->tt_shiftmode */ |
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#define TT_SHIFTER_STLOW 0x0000 |
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#define TT_SHIFTER_STMID 0x0100 |
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#define TT_SHIFTER_STHIGH 0x0200 |
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#define TT_SHIFTER_TTLOW 0x0700 |
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#define TT_SHIFTER_TTMID 0x0400 |
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#define TT_SHIFTER_TTHIGH 0x0600 |
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#define TT_SHIFTER_MODEMASK 0x0700 |
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#define TT_SHIFTER_NUMMODE 0x0008 |
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#define TT_SHIFTER_PALETTE_MASK 0x000f |
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#define TT_SHIFTER_GRAYMODE 0x1000 |
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/* 256 TT palette registers */ |
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#define TT_PALETTE_BASE (0xffff8400) |
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#define tt_palette ((volatile u_short *)TT_PALETTE_BASE) |
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#define TT_PALETTE_RED_MASK 0x0f00 |
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#define TT_PALETTE_GREEN_MASK 0x00f0 |
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#define TT_PALETTE_BLUE_MASK 0x000f |
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/* |
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** Falcon030 VIDEL Video Controller |
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** for description see File 'linux\tools\atari\hardware.txt |
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*/ |
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#define f030_col ((u_long *) 0xffff9800) |
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#define f030_xreg ((u_short*) 0xffff8282) |
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#define f030_yreg ((u_short*) 0xffff82a2) |
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#define f030_creg ((u_short*) 0xffff82c0) |
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#define f030_sreg ((u_short*) 0xffff8260) |
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#define f030_mreg ((u_short*) 0xffff820a) |
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#define f030_linewidth ((u_short*) 0xffff820e) |
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#define f030_hscroll ((u_char*) 0xffff8265) |
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#define VIDEL_BAS (0xffff8260) |
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struct VIDEL { |
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u_short st_shift; |
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u_short pad1; |
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u_char xoffset_s; |
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u_char xoffset; |
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u_short f_shift; |
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u_char pad2[0x1a]; |
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u_short hht; |
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u_short hbb; |
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u_short hbe; |
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u_short hdb; |
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u_short hde; |
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u_short hss; |
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u_char pad3[0x14]; |
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u_short vft; |
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u_short vbb; |
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u_short vbe; |
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u_short vdb; |
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u_short vde; |
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u_short vss; |
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u_char pad4[0x12]; |
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u_short control; |
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u_short mode; |
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}; |
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#define videl ((*(volatile struct VIDEL *)VIDEL_BAS)) |
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/* |
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** DMA/WD1772 Disk Controller |
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*/ |
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#define FWD_BAS (0xffff8604) |
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struct DMA_WD |
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{ |
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u_short fdc_acces_seccount; |
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u_short dma_mode_status; |
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u_char dma_vhi; /* Some extended ST-DMAs can handle 32 bit addresses */ |
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u_char dma_hi; |
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u_char char_dummy2; |
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u_char dma_md; |
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u_char char_dummy3; |
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u_char dma_lo; |
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u_short fdc_speed; |
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}; |
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# define dma_wd ((*(volatile struct DMA_WD *)FWD_BAS)) |
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/* alias */ |
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#define st_dma dma_wd |
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/* The two highest bytes of an extended DMA as a short; this is a must |
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* for the Medusa. |
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*/ |
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#define st_dma_ext_dmahi (*((volatile unsigned short *)0xffff8608)) |
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/* |
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** YM2149 Sound Chip |
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** access in bytes |
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*/ |
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#define YM_BAS (0xffff8800) |
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struct SOUND_YM |
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{ |
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u_char rd_data_reg_sel; |
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u_char char_dummy1; |
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u_char wd_data; |
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}; |
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#define sound_ym ((*(volatile struct SOUND_YM *)YM_BAS)) |
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/* TT SCSI DMA */ |
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#define TT_SCSI_DMA_BAS (0xffff8700) |
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struct TT_DMA { |
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u_char char_dummy0; |
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u_char dma_addr_hi; |
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u_char char_dummy1; |
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u_char dma_addr_hmd; |
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u_char char_dummy2; |
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u_char dma_addr_lmd; |
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u_char char_dummy3; |
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u_char dma_addr_lo; |
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u_char char_dummy4; |
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u_char dma_cnt_hi; |
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u_char char_dummy5; |
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u_char dma_cnt_hmd; |
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u_char char_dummy6; |
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u_char dma_cnt_lmd; |
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u_char char_dummy7; |
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u_char dma_cnt_lo; |
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u_long dma_restdata; |
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u_short dma_ctrl; |
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}; |
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#define tt_scsi_dma ((*(volatile struct TT_DMA *)TT_SCSI_DMA_BAS)) |
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|
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/* TT SCSI Controller 5380 */ |
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#define TT_5380_BAS (0xffff8781) |
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struct TT_5380 { |
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u_char scsi_data; |
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u_char char_dummy1; |
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u_char scsi_icr; |
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u_char char_dummy2; |
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u_char scsi_mode; |
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u_char char_dummy3; |
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u_char scsi_tcr; |
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u_char char_dummy4; |
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u_char scsi_idstat; |
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u_char char_dummy5; |
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u_char scsi_dmastat; |
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u_char char_dummy6; |
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u_char scsi_targrcv; |
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u_char char_dummy7; |
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u_char scsi_inircv; |
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}; |
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#define tt_scsi ((*(volatile struct TT_5380 *)TT_5380_BAS)) |
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#define tt_scsi_regp ((volatile char *)TT_5380_BAS) |
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/* |
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** Falcon DMA Sound Subsystem |
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*/ |
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#define MATRIX_BASE (0xffff8930) |
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struct MATRIX |
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{ |
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u_short source; |
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u_short destination; |
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u_char external_frequency_divider; |
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u_char internal_frequency_divider; |
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}; |
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#define falcon_matrix (*(volatile struct MATRIX *)MATRIX_BASE) |
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#define CODEC_BASE (0xffff8936) |
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struct CODEC |
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{ |
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u_char tracks; |
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u_char input_source; |
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#define CODEC_SOURCE_ADC 1 |
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#define CODEC_SOURCE_MATRIX 2 |
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u_char adc_source; |
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#define ADC_SOURCE_RIGHT_PSG 1 |
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#define ADC_SOURCE_LEFT_PSG 2 |
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u_char gain; |
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#define CODEC_GAIN_RIGHT 0x0f |
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#define CODEC_GAIN_LEFT 0xf0 |
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u_char attenuation; |
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#define CODEC_ATTENUATION_RIGHT 0x0f |
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#define CODEC_ATTENUATION_LEFT 0xf0 |
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u_char unused1; |
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u_char status; |
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#define CODEC_OVERFLOW_RIGHT 1 |
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#define CODEC_OVERFLOW_LEFT 2 |
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u_char unused2, unused3, unused4, unused5; |
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u_char gpio_directions; |
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#define CODEC_GPIO_IN 0 |
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#define CODEC_GPIO_OUT 1 |
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u_char unused6; |
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u_char gpio_data; |
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}; |
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#define falcon_codec (*(volatile struct CODEC *)CODEC_BASE) |
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/* |
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** Falcon Blitter |
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*/ |
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#define BLT_BAS (0xffff8a00) |
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struct BLITTER |
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{ |
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u_short halftone[16]; |
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u_short src_x_inc; |
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u_short src_y_inc; |
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u_long src_address; |
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u_short endmask1; |
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u_short endmask2; |
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u_short endmask3; |
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u_short dst_x_inc; |
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u_short dst_y_inc; |
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u_long dst_address; |
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u_short wd_per_line; |
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u_short ln_per_bb; |
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u_short hlf_op_reg; |
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u_short log_op_reg; |
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u_short lin_nm_reg; |
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u_short skew_reg; |
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}; |
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# define blitter ((*(volatile struct BLITTER *)BLT_BAS)) |
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/* |
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** SCC Z8530 |
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*/ |
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#define SCC_BAS (0xffff8c81) |
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struct SCC |
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{ |
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u_char cha_a_ctrl; |
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u_char char_dummy1; |
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u_char cha_a_data; |
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u_char char_dummy2; |
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u_char cha_b_ctrl; |
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u_char char_dummy3; |
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u_char cha_b_data; |
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}; |
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# define atari_scc ((*(volatile struct SCC*)SCC_BAS)) |
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/* The ESCC (Z85230) in an Atari ST. The channels are reversed! */ |
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# define st_escc ((*(volatile struct SCC*)0xfffffa31)) |
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# define st_escc_dsr ((*(volatile char *)0xfffffa39)) |
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/* TT SCC DMA Controller (same chip as SCSI DMA) */ |
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#define TT_SCC_DMA_BAS (0xffff8c00) |
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#define tt_scc_dma ((*(volatile struct TT_DMA *)TT_SCC_DMA_BAS)) |
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/* |
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** VIDEL Palette Register |
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*/ |
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#define FPL_BAS (0xffff9800) |
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struct VIDEL_PALETTE |
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{ |
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u_long reg[256]; |
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}; |
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# define videl_palette ((*(volatile struct VIDEL_PALETTE*)FPL_BAS)) |
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/* |
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** Falcon DSP Host Interface |
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*/ |
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#define DSP56K_HOST_INTERFACE_BASE (0xffffa200) |
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struct DSP56K_HOST_INTERFACE { |
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u_char icr; |
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#define DSP56K_ICR_RREQ 0x01 |
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#define DSP56K_ICR_TREQ 0x02 |
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#define DSP56K_ICR_HF0 0x08 |
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#define DSP56K_ICR_HF1 0x10 |
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#define DSP56K_ICR_HM0 0x20 |
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#define DSP56K_ICR_HM1 0x40 |
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#define DSP56K_ICR_INIT 0x80 |
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u_char cvr; |
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#define DSP56K_CVR_HV_MASK 0x1f |
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#define DSP56K_CVR_HC 0x80 |
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u_char isr; |
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#define DSP56K_ISR_RXDF 0x01 |
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#define DSP56K_ISR_TXDE 0x02 |
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#define DSP56K_ISR_TRDY 0x04 |
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#define DSP56K_ISR_HF2 0x08 |
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#define DSP56K_ISR_HF3 0x10 |
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#define DSP56K_ISR_DMA 0x40 |
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#define DSP56K_ISR_HREQ 0x80 |
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u_char ivr; |
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union { |
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u_char b[4]; |
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u_short w[2]; |
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u_long l; |
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} data; |
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}; |
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#define dsp56k_host_interface ((*(volatile struct DSP56K_HOST_INTERFACE *)DSP56K_HOST_INTERFACE_BASE)) |
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|
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/* |
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** MFP 68901 |
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*/ |
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#define MFP_BAS (0xfffffa01) |
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struct MFP |
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{ |
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u_char par_dt_reg; |
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u_char char_dummy1; |
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u_char active_edge; |
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u_char char_dummy2; |
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u_char data_dir; |
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u_char char_dummy3; |
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u_char int_en_a; |
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u_char char_dummy4; |
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u_char int_en_b; |
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u_char char_dummy5; |
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u_char int_pn_a; |
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u_char char_dummy6; |
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u_char int_pn_b; |
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u_char char_dummy7; |
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u_char int_sv_a; |
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u_char char_dummy8; |
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u_char int_sv_b; |
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u_char char_dummy9; |
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u_char int_mk_a; |
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u_char char_dummy10; |
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u_char int_mk_b; |
|
u_char char_dummy11; |
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u_char vec_adr; |
|
u_char char_dummy12; |
|
u_char tim_ct_a; |
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u_char char_dummy13; |
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u_char tim_ct_b; |
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u_char char_dummy14; |
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u_char tim_ct_cd; |
|
u_char char_dummy15; |
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u_char tim_dt_a; |
|
u_char char_dummy16; |
|
u_char tim_dt_b; |
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u_char char_dummy17; |
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u_char tim_dt_c; |
|
u_char char_dummy18; |
|
u_char tim_dt_d; |
|
u_char char_dummy19; |
|
u_char sync_char; |
|
u_char char_dummy20; |
|
u_char usart_ctr; |
|
u_char char_dummy21; |
|
u_char rcv_stat; |
|
u_char char_dummy22; |
|
u_char trn_stat; |
|
u_char char_dummy23; |
|
u_char usart_dta; |
|
}; |
|
# define st_mfp ((*(volatile struct MFP*)MFP_BAS)) |
|
|
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/* TT's second MFP */ |
|
|
|
#define TT_MFP_BAS (0xfffffa81) |
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# define tt_mfp ((*(volatile struct MFP*)TT_MFP_BAS)) |
|
|
|
|
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/* TT System Control Unit */ |
|
|
|
#define TT_SCU_BAS (0xffff8e01) |
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struct TT_SCU { |
|
u_char sys_mask; |
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u_char char_dummy1; |
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u_char sys_stat; |
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u_char char_dummy2; |
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u_char softint; |
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u_char char_dummy3; |
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u_char vmeint; |
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u_char char_dummy4; |
|
u_char gp_reg1; |
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u_char char_dummy5; |
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u_char gp_reg2; |
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u_char char_dummy6; |
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u_char vme_mask; |
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u_char char_dummy7; |
|
u_char vme_stat; |
|
}; |
|
#define tt_scu ((*(volatile struct TT_SCU *)TT_SCU_BAS)) |
|
|
|
/* TT real time clock */ |
|
|
|
#define TT_RTC_BAS (0xffff8961) |
|
struct TT_RTC { |
|
u_char regsel; |
|
u_char dummy; |
|
u_char data; |
|
}; |
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#define tt_rtc ((*(volatile struct TT_RTC *)TT_RTC_BAS)) |
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|
|
|
|
/* |
|
** ACIA 6850 |
|
*/ |
|
/* constants for the ACIA registers */ |
|
|
|
/* baudrate selection and reset (Baudrate = clock/factor) */ |
|
#define ACIA_DIV1 0 |
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#define ACIA_DIV16 1 |
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#define ACIA_DIV64 2 |
|
#define ACIA_RESET 3 |
|
|
|
/* character format */ |
|
#define ACIA_D7E2S (0<<2) /* 7 data, even parity, 2 stop */ |
|
#define ACIA_D7O2S (1<<2) /* 7 data, odd parity, 2 stop */ |
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#define ACIA_D7E1S (2<<2) /* 7 data, even parity, 1 stop */ |
|
#define ACIA_D7O1S (3<<2) /* 7 data, odd parity, 1 stop */ |
|
#define ACIA_D8N2S (4<<2) /* 8 data, no parity, 2 stop */ |
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#define ACIA_D8N1S (5<<2) /* 8 data, no parity, 1 stop */ |
|
#define ACIA_D8E1S (6<<2) /* 8 data, even parity, 1 stop */ |
|
#define ACIA_D8O1S (7<<2) /* 8 data, odd parity, 1 stop */ |
|
|
|
/* transmit control */ |
|
#define ACIA_RLTID (0<<5) /* RTS low, TxINT disabled */ |
|
#define ACIA_RLTIE (1<<5) /* RTS low, TxINT enabled */ |
|
#define ACIA_RHTID (2<<5) /* RTS high, TxINT disabled */ |
|
#define ACIA_RLTIDSB (3<<5) /* RTS low, TxINT disabled, send break */ |
|
|
|
/* receive control */ |
|
#define ACIA_RID (0<<7) /* RxINT disabled */ |
|
#define ACIA_RIE (1<<7) /* RxINT enabled */ |
|
|
|
/* status fields of the ACIA */ |
|
#define ACIA_RDRF 1 /* Receive Data Register Full */ |
|
#define ACIA_TDRE (1<<1) /* Transmit Data Register Empty */ |
|
#define ACIA_DCD (1<<2) /* Data Carrier Detect */ |
|
#define ACIA_CTS (1<<3) /* Clear To Send */ |
|
#define ACIA_FE (1<<4) /* Framing Error */ |
|
#define ACIA_OVRN (1<<5) /* Receiver Overrun */ |
|
#define ACIA_PE (1<<6) /* Parity Error */ |
|
#define ACIA_IRQ (1<<7) /* Interrupt Request */ |
|
|
|
#define ACIA_BAS (0xfffffc00) |
|
struct ACIA |
|
{ |
|
u_char key_ctrl; |
|
u_char char_dummy1; |
|
u_char key_data; |
|
u_char char_dummy2; |
|
u_char mid_ctrl; |
|
u_char char_dummy3; |
|
u_char mid_data; |
|
}; |
|
# define acia ((*(volatile struct ACIA*)ACIA_BAS)) |
|
|
|
#define TT_DMASND_BAS (0xffff8900) |
|
struct TT_DMASND { |
|
u_char int_ctrl; /* Falcon: Interrupt control */ |
|
u_char ctrl; |
|
u_char pad2; |
|
u_char bas_hi; |
|
u_char pad3; |
|
u_char bas_mid; |
|
u_char pad4; |
|
u_char bas_low; |
|
u_char pad5; |
|
u_char addr_hi; |
|
u_char pad6; |
|
u_char addr_mid; |
|
u_char pad7; |
|
u_char addr_low; |
|
u_char pad8; |
|
u_char end_hi; |
|
u_char pad9; |
|
u_char end_mid; |
|
u_char pad10; |
|
u_char end_low; |
|
u_char pad11[12]; |
|
u_char track_select; /* Falcon */ |
|
u_char mode; |
|
u_char pad12[14]; |
|
/* Falcon only: */ |
|
u_short cbar_src; |
|
u_short cbar_dst; |
|
u_char ext_div; |
|
u_char int_div; |
|
u_char rec_track_select; |
|
u_char dac_src; |
|
u_char adc_src; |
|
u_char input_gain; |
|
u_short output_atten; |
|
}; |
|
# define tt_dmasnd ((*(volatile struct TT_DMASND *)TT_DMASND_BAS)) |
|
|
|
#define DMASND_MFP_INT_REPLAY 0x01 |
|
#define DMASND_MFP_INT_RECORD 0x02 |
|
#define DMASND_TIMERA_INT_REPLAY 0x04 |
|
#define DMASND_TIMERA_INT_RECORD 0x08 |
|
|
|
#define DMASND_CTRL_OFF 0x00 |
|
#define DMASND_CTRL_ON 0x01 |
|
#define DMASND_CTRL_REPEAT 0x02 |
|
#define DMASND_CTRL_RECORD_ON 0x10 |
|
#define DMASND_CTRL_RECORD_OFF 0x00 |
|
#define DMASND_CTRL_RECORD_REPEAT 0x20 |
|
#define DMASND_CTRL_SELECT_REPLAY 0x00 |
|
#define DMASND_CTRL_SELECT_RECORD 0x80 |
|
#define DMASND_MODE_MONO 0x80 |
|
#define DMASND_MODE_STEREO 0x00 |
|
#define DMASND_MODE_8BIT 0x00 |
|
#define DMASND_MODE_16BIT 0x40 /* Falcon only */ |
|
#define DMASND_MODE_6KHZ 0x00 /* Falcon: mute */ |
|
#define DMASND_MODE_12KHZ 0x01 |
|
#define DMASND_MODE_25KHZ 0x02 |
|
#define DMASND_MODE_50KHZ 0x03 |
|
|
|
|
|
#define DMASNDSetBase(bufstart) \ |
|
do { \ |
|
tt_dmasnd.bas_hi = (unsigned char)(((bufstart) & 0xff0000) >> 16); \ |
|
tt_dmasnd.bas_mid = (unsigned char)(((bufstart) & 0x00ff00) >> 8); \ |
|
tt_dmasnd.bas_low = (unsigned char) ((bufstart) & 0x0000ff); \ |
|
} while( 0 ) |
|
|
|
#define DMASNDGetAdr() ((tt_dmasnd.addr_hi << 16) + \ |
|
(tt_dmasnd.addr_mid << 8) + \ |
|
(tt_dmasnd.addr_low)) |
|
|
|
#define DMASNDSetEnd(bufend) \ |
|
do { \ |
|
tt_dmasnd.end_hi = (unsigned char)(((bufend) & 0xff0000) >> 16); \ |
|
tt_dmasnd.end_mid = (unsigned char)(((bufend) & 0x00ff00) >> 8); \ |
|
tt_dmasnd.end_low = (unsigned char) ((bufend) & 0x0000ff); \ |
|
} while( 0 ) |
|
|
|
|
|
#define TT_MICROWIRE_BAS (0xffff8922) |
|
struct TT_MICROWIRE { |
|
u_short data; |
|
u_short mask; |
|
}; |
|
# define tt_microwire ((*(volatile struct TT_MICROWIRE *)TT_MICROWIRE_BAS)) |
|
|
|
#define MW_LM1992_ADDR 0x0400 |
|
|
|
#define MW_LM1992_VOLUME(dB) \ |
|
(0x0c0 | ((dB) < -80 ? 0 : (dB) > 0 ? 40 : (((dB) + 80) / 2))) |
|
#define MW_LM1992_BALLEFT(dB) \ |
|
(0x140 | ((dB) < -40 ? 0 : (dB) > 0 ? 20 : (((dB) + 40) / 2))) |
|
#define MW_LM1992_BALRIGHT(dB) \ |
|
(0x100 | ((dB) < -40 ? 0 : (dB) > 0 ? 20 : (((dB) + 40) / 2))) |
|
#define MW_LM1992_TREBLE(dB) \ |
|
(0x080 | ((dB) < -12 ? 0 : (dB) > 12 ? 12 : (((dB) / 2) + 6))) |
|
#define MW_LM1992_BASS(dB) \ |
|
(0x040 | ((dB) < -12 ? 0 : (dB) > 12 ? 12 : (((dB) / 2) + 6))) |
|
|
|
#define MW_LM1992_PSG_LOW 0x000 |
|
#define MW_LM1992_PSG_HIGH 0x001 |
|
#define MW_LM1992_PSG_OFF 0x002 |
|
|
|
#define MSTE_RTC_BAS (0xfffffc21) |
|
|
|
struct MSTE_RTC { |
|
u_char sec_ones; |
|
u_char dummy1; |
|
u_char sec_tens; |
|
u_char dummy2; |
|
u_char min_ones; |
|
u_char dummy3; |
|
u_char min_tens; |
|
u_char dummy4; |
|
u_char hr_ones; |
|
u_char dummy5; |
|
u_char hr_tens; |
|
u_char dummy6; |
|
u_char weekday; |
|
u_char dummy7; |
|
u_char day_ones; |
|
u_char dummy8; |
|
u_char day_tens; |
|
u_char dummy9; |
|
u_char mon_ones; |
|
u_char dummy10; |
|
u_char mon_tens; |
|
u_char dummy11; |
|
u_char year_ones; |
|
u_char dummy12; |
|
u_char year_tens; |
|
u_char dummy13; |
|
u_char mode; |
|
u_char dummy14; |
|
u_char test; |
|
u_char dummy15; |
|
u_char reset; |
|
}; |
|
|
|
#define mste_rtc ((*(volatile struct MSTE_RTC *)MSTE_RTC_BAS)) |
|
|
|
/* |
|
** EtherNAT add-on card for Falcon - combined ethernet and USB adapter |
|
*/ |
|
|
|
#define ATARI_ETHERNAT_PHYS_ADDR 0x80000000 |
|
|
|
#endif /* linux/atarihw.h */ |
|
|
|
|