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225 lines
5.4 KiB
225 lines
5.4 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* linux/arch/alpha/kernel/sys_eiger.c |
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* |
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* Copyright (C) 1995 David A Rusling |
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* Copyright (C) 1996, 1999 Jay A Estabrook |
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* Copyright (C) 1998, 1999 Richard Henderson |
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* Copyright (C) 1999 Iain Grant |
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* |
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* Code supporting the EIGER (EV6+TSUNAMI). |
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*/ |
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#include <linux/kernel.h> |
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#include <linux/types.h> |
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#include <linux/mm.h> |
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#include <linux/sched.h> |
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#include <linux/pci.h> |
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#include <linux/init.h> |
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#include <linux/bitops.h> |
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#include <asm/ptrace.h> |
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#include <asm/dma.h> |
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#include <asm/irq.h> |
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#include <asm/mmu_context.h> |
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#include <asm/io.h> |
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#include <asm/core_tsunami.h> |
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#include <asm/hwrpb.h> |
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#include <asm/tlbflush.h> |
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#include "proto.h" |
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#include "irq_impl.h" |
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#include "pci_impl.h" |
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#include "machvec_impl.h" |
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/* Note that this interrupt code is identical to TAKARA. */ |
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/* Note mask bit is true for DISABLED irqs. */ |
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static unsigned long cached_irq_mask[2] = { -1, -1 }; |
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static inline void |
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eiger_update_irq_hw(unsigned long irq, unsigned long mask) |
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{ |
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int regaddr; |
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mask = (irq >= 64 ? mask << 16 : mask >> ((irq - 16) & 0x30)); |
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regaddr = 0x510 + (((irq - 16) >> 2) & 0x0c); |
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outl(mask & 0xffff0000UL, regaddr); |
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} |
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static inline void |
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eiger_enable_irq(struct irq_data *d) |
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{ |
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unsigned int irq = d->irq; |
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unsigned long mask; |
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mask = (cached_irq_mask[irq >= 64] &= ~(1UL << (irq & 63))); |
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eiger_update_irq_hw(irq, mask); |
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} |
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static void |
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eiger_disable_irq(struct irq_data *d) |
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{ |
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unsigned int irq = d->irq; |
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unsigned long mask; |
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mask = (cached_irq_mask[irq >= 64] |= 1UL << (irq & 63)); |
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eiger_update_irq_hw(irq, mask); |
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} |
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static struct irq_chip eiger_irq_type = { |
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.name = "EIGER", |
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.irq_unmask = eiger_enable_irq, |
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.irq_mask = eiger_disable_irq, |
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.irq_mask_ack = eiger_disable_irq, |
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}; |
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static void |
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eiger_device_interrupt(unsigned long vector) |
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{ |
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unsigned intstatus; |
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/* |
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* The PALcode will have passed us vectors 0x800 or 0x810, |
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* which are fairly arbitrary values and serve only to tell |
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* us whether an interrupt has come in on IRQ0 or IRQ1. If |
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* it's IRQ1 it's a PCI interrupt; if it's IRQ0, it's |
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* probably ISA, but PCI interrupts can come through IRQ0 |
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* as well if the interrupt controller isn't in accelerated |
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* mode. |
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* |
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* OTOH, the accelerator thing doesn't seem to be working |
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* overly well, so what we'll do instead is try directly |
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* examining the Master Interrupt Register to see if it's a |
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* PCI interrupt, and if _not_ then we'll pass it on to the |
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* ISA handler. |
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*/ |
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intstatus = inw(0x500) & 15; |
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if (intstatus) { |
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/* |
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* This is a PCI interrupt. Check each bit and |
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* despatch an interrupt if it's set. |
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*/ |
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if (intstatus & 8) handle_irq(16+3); |
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if (intstatus & 4) handle_irq(16+2); |
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if (intstatus & 2) handle_irq(16+1); |
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if (intstatus & 1) handle_irq(16+0); |
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} else { |
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isa_device_interrupt(vector); |
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} |
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} |
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static void |
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eiger_srm_device_interrupt(unsigned long vector) |
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{ |
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int irq = (vector - 0x800) >> 4; |
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handle_irq(irq); |
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} |
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static void __init |
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eiger_init_irq(void) |
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{ |
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long i; |
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outb(0, DMA1_RESET_REG); |
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outb(0, DMA2_RESET_REG); |
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outb(DMA_MODE_CASCADE, DMA2_MODE_REG); |
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outb(0, DMA2_MASK_REG); |
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if (alpha_using_srm) |
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alpha_mv.device_interrupt = eiger_srm_device_interrupt; |
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for (i = 16; i < 128; i += 16) |
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eiger_update_irq_hw(i, -1); |
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init_i8259a_irqs(); |
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for (i = 16; i < 128; ++i) { |
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irq_set_chip_and_handler(i, &eiger_irq_type, handle_level_irq); |
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irq_set_status_flags(i, IRQ_LEVEL); |
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} |
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} |
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static int |
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eiger_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) |
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{ |
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u8 irq_orig; |
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/* The SRM console has already calculated out the IRQ value's for |
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option cards. As this works lets just read in the value already |
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set and change it to a useable value by Linux. |
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All the IRQ values generated by the console are greater than 90, |
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so we subtract 80 because it is (90 - allocated ISA IRQ's). */ |
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pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq_orig); |
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return irq_orig - 0x80; |
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} |
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static u8 |
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eiger_swizzle(struct pci_dev *dev, u8 *pinp) |
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{ |
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struct pci_controller *hose = dev->sysdata; |
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int slot, pin = *pinp; |
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int bridge_count = 0; |
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/* Find the number of backplane bridges. */ |
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int backplane = inw(0x502) & 0x0f; |
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switch (backplane) |
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{ |
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case 0x00: bridge_count = 0; break; /* No bridges */ |
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case 0x01: bridge_count = 1; break; /* 1 */ |
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case 0x03: bridge_count = 2; break; /* 2 */ |
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case 0x07: bridge_count = 3; break; /* 3 */ |
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case 0x0f: bridge_count = 4; break; /* 4 */ |
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} |
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slot = PCI_SLOT(dev->devfn); |
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while (dev->bus->self) { |
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/* Check for built-in bridges on hose 0. */ |
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if (hose->index == 0 |
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&& (PCI_SLOT(dev->bus->self->devfn) |
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> 20 - bridge_count)) { |
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slot = PCI_SLOT(dev->devfn); |
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break; |
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} |
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/* Must be a card-based bridge. */ |
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pin = pci_swizzle_interrupt_pin(dev, pin); |
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/* Move up the chain of bridges. */ |
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dev = dev->bus->self; |
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} |
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*pinp = pin; |
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return slot; |
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} |
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/* |
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* The System Vectors |
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*/ |
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struct alpha_machine_vector eiger_mv __initmv = { |
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.vector_name = "Eiger", |
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DO_EV6_MMU, |
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DO_DEFAULT_RTC, |
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DO_TSUNAMI_IO, |
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.machine_check = tsunami_machine_check, |
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.max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS, |
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.min_io_address = DEFAULT_IO_BASE, |
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.min_mem_address = DEFAULT_MEM_BASE, |
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.pci_dac_offset = TSUNAMI_DAC_OFFSET, |
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.nr_irqs = 128, |
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.device_interrupt = eiger_device_interrupt, |
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.init_arch = tsunami_init_arch, |
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.init_irq = eiger_init_irq, |
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.init_rtc = common_init_rtc, |
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.init_pci = common_init_pci, |
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.kill_arch = tsunami_kill_arch, |
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.pci_map_irq = eiger_map_irq, |
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.pci_swizzle = eiger_swizzle, |
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}; |
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ALIAS_MV(eiger)
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