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444 lines
12 KiB
444 lines
12 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* linux/arch/alpha/kernel/sys_cabriolet.c |
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* |
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* Copyright (C) 1995 David A Rusling |
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* Copyright (C) 1996 Jay A Estabrook |
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* Copyright (C) 1998, 1999, 2000 Richard Henderson |
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* |
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* Code supporting the Cabriolet (AlphaPC64), EB66+, and EB164, |
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* PC164 and LX164. |
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*/ |
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#include <linux/kernel.h> |
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#include <linux/types.h> |
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#include <linux/mm.h> |
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#include <linux/sched.h> |
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#include <linux/pci.h> |
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#include <linux/init.h> |
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#include <linux/bitops.h> |
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#include <asm/ptrace.h> |
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#include <asm/dma.h> |
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#include <asm/irq.h> |
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#include <asm/mmu_context.h> |
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#include <asm/io.h> |
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#include <asm/core_apecs.h> |
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#include <asm/core_cia.h> |
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#include <asm/core_lca.h> |
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#include <asm/tlbflush.h> |
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#include "proto.h" |
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#include "irq_impl.h" |
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#include "pci_impl.h" |
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#include "machvec_impl.h" |
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#include "pc873xx.h" |
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/* Note mask bit is true for DISABLED irqs. */ |
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static unsigned long cached_irq_mask = ~0UL; |
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static inline void |
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cabriolet_update_irq_hw(unsigned int irq, unsigned long mask) |
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{ |
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int ofs = (irq - 16) / 8; |
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outb(mask >> (16 + ofs * 8), 0x804 + ofs); |
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} |
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static inline void |
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cabriolet_enable_irq(struct irq_data *d) |
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{ |
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cabriolet_update_irq_hw(d->irq, cached_irq_mask &= ~(1UL << d->irq)); |
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} |
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static void |
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cabriolet_disable_irq(struct irq_data *d) |
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{ |
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cabriolet_update_irq_hw(d->irq, cached_irq_mask |= 1UL << d->irq); |
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} |
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static struct irq_chip cabriolet_irq_type = { |
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.name = "CABRIOLET", |
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.irq_unmask = cabriolet_enable_irq, |
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.irq_mask = cabriolet_disable_irq, |
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.irq_mask_ack = cabriolet_disable_irq, |
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}; |
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static void |
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cabriolet_device_interrupt(unsigned long v) |
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{ |
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unsigned long pld; |
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unsigned int i; |
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/* Read the interrupt summary registers */ |
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pld = inb(0x804) | (inb(0x805) << 8) | (inb(0x806) << 16); |
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/* |
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* Now for every possible bit set, work through them and call |
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* the appropriate interrupt handler. |
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*/ |
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while (pld) { |
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i = ffz(~pld); |
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pld &= pld - 1; /* clear least bit set */ |
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if (i == 4) { |
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isa_device_interrupt(v); |
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} else { |
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handle_irq(16 + i); |
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} |
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} |
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} |
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static void __init |
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common_init_irq(void (*srm_dev_int)(unsigned long v)) |
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{ |
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init_i8259a_irqs(); |
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if (alpha_using_srm) { |
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alpha_mv.device_interrupt = srm_dev_int; |
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init_srm_irqs(35, 0); |
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} |
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else { |
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long i; |
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outb(0xff, 0x804); |
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outb(0xff, 0x805); |
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outb(0xff, 0x806); |
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for (i = 16; i < 35; ++i) { |
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irq_set_chip_and_handler(i, &cabriolet_irq_type, |
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handle_level_irq); |
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irq_set_status_flags(i, IRQ_LEVEL); |
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} |
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} |
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common_init_isa_dma(); |
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if (request_irq(16 + 4, no_action, 0, "isa-cascade", NULL)) |
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pr_err("Failed to register isa-cascade interrupt\n"); |
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} |
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#ifndef CONFIG_ALPHA_PC164 |
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static void __init |
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cabriolet_init_irq(void) |
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{ |
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common_init_irq(srm_device_interrupt); |
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} |
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#endif |
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#if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_PC164) |
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/* In theory, the PC164 has the same interrupt hardware as the other |
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Cabriolet based systems. However, something got screwed up late |
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in the development cycle which broke the interrupt masking hardware. |
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Repeat, it is not possible to mask and ack interrupts. At all. |
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In an attempt to work around this, while processing interrupts, |
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we do not allow the IPL to drop below what it is currently. This |
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prevents the possibility of recursion. |
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??? Another option might be to force all PCI devices to use edge |
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triggered rather than level triggered interrupts. That might be |
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too invasive though. */ |
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static void |
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pc164_srm_device_interrupt(unsigned long v) |
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{ |
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__min_ipl = getipl(); |
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srm_device_interrupt(v); |
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__min_ipl = 0; |
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} |
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static void |
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pc164_device_interrupt(unsigned long v) |
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{ |
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__min_ipl = getipl(); |
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cabriolet_device_interrupt(v); |
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__min_ipl = 0; |
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} |
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static void __init |
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pc164_init_irq(void) |
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{ |
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common_init_irq(pc164_srm_device_interrupt); |
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} |
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#endif |
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/* |
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* The EB66+ is very similar to the EB66 except that it does not have |
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* the on-board NCR and Tulip chips. In the code below, I have used |
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* slot number to refer to the id select line and *not* the slot |
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* number used in the EB66+ documentation. However, in the table, |
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* I've given the slot number, the id select line and the Jxx number |
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* that's printed on the board. The interrupt pins from the PCI slots |
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* are wired into 3 interrupt summary registers at 0x804, 0x805 and |
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* 0x806 ISA. |
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* |
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* In the table, -1 means don't assign an IRQ number. This is usually |
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* because it is the Saturn IO (SIO) PCI/ISA Bridge Chip. |
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*/ |
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static inline int |
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eb66p_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) |
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{ |
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static char irq_tab[5][5] = { |
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/*INT INTA INTB INTC INTD */ |
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{16+0, 16+0, 16+5, 16+9, 16+13}, /* IdSel 6, slot 0, J25 */ |
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{16+1, 16+1, 16+6, 16+10, 16+14}, /* IdSel 7, slot 1, J26 */ |
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{ -1, -1, -1, -1, -1}, /* IdSel 8, SIO */ |
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{16+2, 16+2, 16+7, 16+11, 16+15}, /* IdSel 9, slot 2, J27 */ |
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{16+3, 16+3, 16+8, 16+12, 16+6} /* IdSel 10, slot 3, J28 */ |
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}; |
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const long min_idsel = 6, max_idsel = 10, irqs_per_slot = 5; |
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return COMMON_TABLE_LOOKUP; |
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} |
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/* |
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* The AlphaPC64 is very similar to the EB66+ except that its slots |
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* are numbered differently. In the code below, I have used slot |
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* number to refer to the id select line and *not* the slot number |
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* used in the AlphaPC64 documentation. However, in the table, I've |
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* given the slot number, the id select line and the Jxx number that's |
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* printed on the board. The interrupt pins from the PCI slots are |
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* wired into 3 interrupt summary registers at 0x804, 0x805 and 0x806 |
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* ISA. |
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* |
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* In the table, -1 means don't assign an IRQ number. This is usually |
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* because it is the Saturn IO (SIO) PCI/ISA Bridge Chip. |
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*/ |
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static inline int |
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cabriolet_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) |
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{ |
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static char irq_tab[5][5] = { |
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/*INT INTA INTB INTC INTD */ |
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{ 16+2, 16+2, 16+7, 16+11, 16+15}, /* IdSel 5, slot 2, J21 */ |
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{ 16+0, 16+0, 16+5, 16+9, 16+13}, /* IdSel 6, slot 0, J19 */ |
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{ 16+1, 16+1, 16+6, 16+10, 16+14}, /* IdSel 7, slot 1, J20 */ |
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{ -1, -1, -1, -1, -1}, /* IdSel 8, SIO */ |
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{ 16+3, 16+3, 16+8, 16+12, 16+16} /* IdSel 9, slot 3, J22 */ |
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}; |
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const long min_idsel = 5, max_idsel = 9, irqs_per_slot = 5; |
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return COMMON_TABLE_LOOKUP; |
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} |
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static inline void __init |
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cabriolet_enable_ide(void) |
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{ |
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if (pc873xx_probe() == -1) { |
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printk(KERN_ERR "Probing for PC873xx Super IO chip failed.\n"); |
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} else { |
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printk(KERN_INFO "Found %s Super IO chip at 0x%x\n", |
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pc873xx_get_model(), pc873xx_get_base()); |
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pc873xx_enable_ide(); |
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} |
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} |
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static inline void __init |
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cabriolet_init_pci(void) |
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{ |
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common_init_pci(); |
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cabriolet_enable_ide(); |
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} |
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static inline void __init |
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cia_cab_init_pci(void) |
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{ |
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cia_init_pci(); |
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cabriolet_enable_ide(); |
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} |
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/* |
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* The PC164 and LX164 have 19 PCI interrupts, four from each of the four |
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* PCI slots, the SIO, PCI/IDE, and USB. |
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* |
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* Each of the interrupts can be individually masked. This is |
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* accomplished by setting the appropriate bit in the mask register. |
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* A bit is set by writing a "1" to the desired position in the mask |
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* register and cleared by writing a "0". There are 3 mask registers |
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* located at ISA address 804h, 805h and 806h. |
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* |
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* An I/O read at ISA address 804h, 805h, 806h will return the |
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* state of the 11 PCI interrupts and not the state of the MASKED |
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* interrupts. |
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* |
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* Note: A write to I/O 804h, 805h, and 806h the mask register will be |
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* updated. |
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* |
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* |
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* ISA DATA<7:0> |
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* ISA +--------------------------------------------------------------+ |
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* ADDRESS | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
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* +==============================================================+ |
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* 0x804 | INTB0 | USB | IDE | SIO | INTA3 |INTA2 | INTA1 | INTA0 | |
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* +--------------------------------------------------------------+ |
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* 0x805 | INTD0 | INTC3 | INTC2 | INTC1 | INTC0 |INTB3 | INTB2 | INTB1 | |
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* +--------------------------------------------------------------+ |
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* 0x806 | Rsrv | Rsrv | Rsrv | Rsrv | Rsrv |INTD3 | INTD2 | INTD1 | |
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* +--------------------------------------------------------------+ |
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* * Rsrv = reserved bits |
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* Note: The mask register is write-only. |
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* |
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* IdSel |
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* 5 32 bit PCI option slot 2 |
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* 6 64 bit PCI option slot 0 |
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* 7 64 bit PCI option slot 1 |
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* 8 Saturn I/O |
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* 9 32 bit PCI option slot 3 |
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* 10 USB |
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* 11 IDE |
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* |
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*/ |
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static inline int |
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alphapc164_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) |
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{ |
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static char irq_tab[7][5] = { |
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/*INT INTA INTB INTC INTD */ |
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{ 16+2, 16+2, 16+9, 16+13, 16+17}, /* IdSel 5, slot 2, J20 */ |
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{ 16+0, 16+0, 16+7, 16+11, 16+15}, /* IdSel 6, slot 0, J29 */ |
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{ 16+1, 16+1, 16+8, 16+12, 16+16}, /* IdSel 7, slot 1, J26 */ |
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{ -1, -1, -1, -1, -1}, /* IdSel 8, SIO */ |
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{ 16+3, 16+3, 16+10, 16+14, 16+18}, /* IdSel 9, slot 3, J19 */ |
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{ 16+6, 16+6, 16+6, 16+6, 16+6}, /* IdSel 10, USB */ |
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{ 16+5, 16+5, 16+5, 16+5, 16+5} /* IdSel 11, IDE */ |
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}; |
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const long min_idsel = 5, max_idsel = 11, irqs_per_slot = 5; |
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return COMMON_TABLE_LOOKUP; |
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} |
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static inline void __init |
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alphapc164_init_pci(void) |
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{ |
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cia_init_pci(); |
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SMC93x_Init(); |
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} |
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/* |
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* The System Vector |
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*/ |
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#if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_CABRIOLET) |
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struct alpha_machine_vector cabriolet_mv __initmv = { |
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.vector_name = "Cabriolet", |
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DO_EV4_MMU, |
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DO_DEFAULT_RTC, |
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DO_APECS_IO, |
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.machine_check = apecs_machine_check, |
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.max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS, |
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.min_io_address = DEFAULT_IO_BASE, |
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.min_mem_address = APECS_AND_LCA_DEFAULT_MEM_BASE, |
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.nr_irqs = 35, |
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.device_interrupt = cabriolet_device_interrupt, |
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.init_arch = apecs_init_arch, |
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.init_irq = cabriolet_init_irq, |
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.init_rtc = common_init_rtc, |
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.init_pci = cabriolet_init_pci, |
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.pci_map_irq = cabriolet_map_irq, |
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.pci_swizzle = common_swizzle, |
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}; |
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#ifndef CONFIG_ALPHA_EB64P |
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ALIAS_MV(cabriolet) |
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#endif |
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#endif |
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#if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_EB164) |
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struct alpha_machine_vector eb164_mv __initmv = { |
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.vector_name = "EB164", |
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DO_EV5_MMU, |
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DO_DEFAULT_RTC, |
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DO_CIA_IO, |
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.machine_check = cia_machine_check, |
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.max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS, |
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.min_io_address = DEFAULT_IO_BASE, |
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.min_mem_address = CIA_DEFAULT_MEM_BASE, |
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.nr_irqs = 35, |
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.device_interrupt = cabriolet_device_interrupt, |
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.init_arch = cia_init_arch, |
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.init_irq = cabriolet_init_irq, |
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.init_rtc = common_init_rtc, |
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.init_pci = cia_cab_init_pci, |
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.kill_arch = cia_kill_arch, |
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.pci_map_irq = cabriolet_map_irq, |
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.pci_swizzle = common_swizzle, |
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}; |
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ALIAS_MV(eb164) |
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#endif |
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#if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_EB66P) |
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struct alpha_machine_vector eb66p_mv __initmv = { |
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.vector_name = "EB66+", |
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DO_EV4_MMU, |
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DO_DEFAULT_RTC, |
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DO_LCA_IO, |
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.machine_check = lca_machine_check, |
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.max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS, |
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.min_io_address = DEFAULT_IO_BASE, |
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.min_mem_address = APECS_AND_LCA_DEFAULT_MEM_BASE, |
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.nr_irqs = 35, |
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.device_interrupt = cabriolet_device_interrupt, |
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.init_arch = lca_init_arch, |
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.init_irq = cabriolet_init_irq, |
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.init_rtc = common_init_rtc, |
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.init_pci = cabriolet_init_pci, |
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.pci_map_irq = eb66p_map_irq, |
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.pci_swizzle = common_swizzle, |
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}; |
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ALIAS_MV(eb66p) |
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#endif |
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#if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_LX164) |
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struct alpha_machine_vector lx164_mv __initmv = { |
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.vector_name = "LX164", |
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DO_EV5_MMU, |
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DO_DEFAULT_RTC, |
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DO_PYXIS_IO, |
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.machine_check = cia_machine_check, |
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.max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS, |
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.min_io_address = DEFAULT_IO_BASE, |
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.min_mem_address = DEFAULT_MEM_BASE, |
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.pci_dac_offset = PYXIS_DAC_OFFSET, |
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.nr_irqs = 35, |
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.device_interrupt = cabriolet_device_interrupt, |
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.init_arch = pyxis_init_arch, |
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.init_irq = cabriolet_init_irq, |
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.init_rtc = common_init_rtc, |
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.init_pci = alphapc164_init_pci, |
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.kill_arch = cia_kill_arch, |
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.pci_map_irq = alphapc164_map_irq, |
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.pci_swizzle = common_swizzle, |
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}; |
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ALIAS_MV(lx164) |
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#endif |
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#if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_PC164) |
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struct alpha_machine_vector pc164_mv __initmv = { |
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.vector_name = "PC164", |
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DO_EV5_MMU, |
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DO_DEFAULT_RTC, |
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DO_CIA_IO, |
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.machine_check = cia_machine_check, |
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.max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS, |
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.min_io_address = DEFAULT_IO_BASE, |
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.min_mem_address = CIA_DEFAULT_MEM_BASE, |
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.nr_irqs = 35, |
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.device_interrupt = pc164_device_interrupt, |
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.init_arch = cia_init_arch, |
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.init_irq = pc164_init_irq, |
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.init_rtc = common_init_rtc, |
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.init_pci = alphapc164_init_pci, |
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.kill_arch = cia_kill_arch, |
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.pci_map_irq = alphapc164_map_irq, |
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.pci_swizzle = common_swizzle, |
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}; |
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ALIAS_MV(pc164) |
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#endif
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