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484 lines
13 KiB
484 lines
13 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* linux/arch/alpha/kernel/core_tsunami.c |
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* |
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* Based on code written by David A. Rusling ([email protected]). |
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* |
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* Code common to all TSUNAMI core logic chips. |
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*/ |
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|
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#define __EXTERN_INLINE inline |
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#include <asm/io.h> |
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#include <asm/core_tsunami.h> |
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#undef __EXTERN_INLINE |
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#include <linux/module.h> |
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#include <linux/types.h> |
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#include <linux/pci.h> |
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#include <linux/sched.h> |
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#include <linux/init.h> |
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#include <linux/memblock.h> |
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|
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#include <asm/ptrace.h> |
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#include <asm/smp.h> |
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#include <asm/vga.h> |
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|
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#include "proto.h" |
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#include "pci_impl.h" |
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|
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/* Save Tsunami configuration data as the console had it set up. */ |
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|
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struct |
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{ |
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unsigned long wsba[4]; |
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unsigned long wsm[4]; |
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unsigned long tba[4]; |
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} saved_config[2] __attribute__((common)); |
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|
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/* |
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* NOTE: Herein lie back-to-back mb instructions. They are magic. |
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* One plausible explanation is that the I/O controller does not properly |
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* handle the system transaction. Another involves timing. Ho hum. |
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*/ |
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|
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/* |
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* BIOS32-style PCI interface: |
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*/ |
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|
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#define DEBUG_CONFIG 0 |
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|
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#if DEBUG_CONFIG |
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# define DBG_CFG(args) printk args |
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#else |
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# define DBG_CFG(args) |
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#endif |
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|
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/* |
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* Given a bus, device, and function number, compute resulting |
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* configuration space address |
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* accordingly. It is therefore not safe to have concurrent |
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* invocations to configuration space access routines, but there |
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* really shouldn't be any need for this. |
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* |
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* Note that all config space accesses use Type 1 address format. |
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* |
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* Note also that type 1 is determined by non-zero bus number. |
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* |
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* Type 1: |
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* |
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* 3 3|3 3 2 2|2 2 2 2|2 2 2 2|1 1 1 1|1 1 1 1|1 1 |
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* 3 2|1 0 9 8|7 6 5 4|3 2 1 0|9 8 7 6|5 4 3 2|1 0 9 8|7 6 5 4|3 2 1 0 |
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* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ |
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* | | | | | | | | | | |B|B|B|B|B|B|B|B|D|D|D|D|D|F|F|F|R|R|R|R|R|R|0|1| |
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* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ |
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* |
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* 31:24 reserved |
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* 23:16 bus number (8 bits = 128 possible buses) |
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* 15:11 Device number (5 bits) |
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* 10:8 function number |
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* 7:2 register number |
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* |
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* Notes: |
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* The function number selects which function of a multi-function device |
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* (e.g., SCSI and Ethernet). |
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* |
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* The register selects a DWORD (32 bit) register offset. Hence it |
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* doesn't get shifted by 2 bits as we want to "drop" the bottom two |
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* bits. |
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*/ |
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|
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static int |
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mk_conf_addr(struct pci_bus *pbus, unsigned int device_fn, int where, |
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unsigned long *pci_addr, unsigned char *type1) |
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{ |
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struct pci_controller *hose = pbus->sysdata; |
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unsigned long addr; |
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u8 bus = pbus->number; |
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DBG_CFG(("mk_conf_addr(bus=%d ,device_fn=0x%x, where=0x%x, " |
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"pci_addr=0x%p, type1=0x%p)\n", |
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bus, device_fn, where, pci_addr, type1)); |
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if (!pbus->parent) /* No parent means peer PCI bus. */ |
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bus = 0; |
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*type1 = (bus != 0); |
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addr = (bus << 16) | (device_fn << 8) | where; |
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addr |= hose->config_space_base; |
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*pci_addr = addr; |
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DBG_CFG(("mk_conf_addr: returning pci_addr 0x%lx\n", addr)); |
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return 0; |
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} |
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static int |
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tsunami_read_config(struct pci_bus *bus, unsigned int devfn, int where, |
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int size, u32 *value) |
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{ |
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unsigned long addr; |
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unsigned char type1; |
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if (mk_conf_addr(bus, devfn, where, &addr, &type1)) |
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return PCIBIOS_DEVICE_NOT_FOUND; |
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switch (size) { |
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case 1: |
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*value = __kernel_ldbu(*(vucp)addr); |
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break; |
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case 2: |
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*value = __kernel_ldwu(*(vusp)addr); |
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break; |
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case 4: |
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*value = *(vuip)addr; |
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break; |
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} |
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return PCIBIOS_SUCCESSFUL; |
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} |
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static int |
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tsunami_write_config(struct pci_bus *bus, unsigned int devfn, int where, |
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int size, u32 value) |
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{ |
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unsigned long addr; |
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unsigned char type1; |
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if (mk_conf_addr(bus, devfn, where, &addr, &type1)) |
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return PCIBIOS_DEVICE_NOT_FOUND; |
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switch (size) { |
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case 1: |
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__kernel_stb(value, *(vucp)addr); |
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mb(); |
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__kernel_ldbu(*(vucp)addr); |
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break; |
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case 2: |
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__kernel_stw(value, *(vusp)addr); |
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mb(); |
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__kernel_ldwu(*(vusp)addr); |
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break; |
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case 4: |
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*(vuip)addr = value; |
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mb(); |
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*(vuip)addr; |
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break; |
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} |
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return PCIBIOS_SUCCESSFUL; |
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} |
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struct pci_ops tsunami_pci_ops = |
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{ |
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.read = tsunami_read_config, |
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.write = tsunami_write_config, |
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}; |
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void |
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tsunami_pci_tbi(struct pci_controller *hose, dma_addr_t start, dma_addr_t end) |
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{ |
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tsunami_pchip *pchip = hose->index ? TSUNAMI_pchip1 : TSUNAMI_pchip0; |
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volatile unsigned long *csr; |
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unsigned long value; |
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/* We can invalidate up to 8 tlb entries in a go. The flush |
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matches against <31:16> in the pci address. */ |
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csr = &pchip->tlbia.csr; |
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if (((start ^ end) & 0xffff0000) == 0) |
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csr = &pchip->tlbiv.csr; |
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/* For TBIA, it doesn't matter what value we write. For TBI, |
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it's the shifted tag bits. */ |
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value = (start & 0xffff0000) >> 12; |
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*csr = value; |
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mb(); |
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*csr; |
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} |
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#ifdef NXM_MACHINE_CHECKS_ON_TSUNAMI |
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static long __init |
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tsunami_probe_read(volatile unsigned long *vaddr) |
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{ |
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long dont_care, probe_result; |
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int cpu = smp_processor_id(); |
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int s = swpipl(IPL_MCHECK - 1); |
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mcheck_taken(cpu) = 0; |
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mcheck_expected(cpu) = 1; |
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mb(); |
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dont_care = *vaddr; |
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draina(); |
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mcheck_expected(cpu) = 0; |
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probe_result = !mcheck_taken(cpu); |
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mcheck_taken(cpu) = 0; |
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setipl(s); |
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printk("dont_care == 0x%lx\n", dont_care); |
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return probe_result; |
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} |
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static long __init |
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tsunami_probe_write(volatile unsigned long *vaddr) |
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{ |
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long true_contents, probe_result = 1; |
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TSUNAMI_cchip->misc.csr |= (1L << 28); /* clear NXM... */ |
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true_contents = *vaddr; |
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*vaddr = 0; |
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draina(); |
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if (TSUNAMI_cchip->misc.csr & (1L << 28)) { |
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int source = (TSUNAMI_cchip->misc.csr >> 29) & 7; |
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TSUNAMI_cchip->misc.csr |= (1L << 28); /* ...and unlock NXS. */ |
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probe_result = 0; |
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printk("tsunami_probe_write: unit %d at 0x%016lx\n", source, |
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(unsigned long)vaddr); |
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} |
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if (probe_result) |
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*vaddr = true_contents; |
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return probe_result; |
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} |
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#else |
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#define tsunami_probe_read(ADDR) 1 |
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#endif /* NXM_MACHINE_CHECKS_ON_TSUNAMI */ |
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static void __init |
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tsunami_init_one_pchip(tsunami_pchip *pchip, int index) |
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{ |
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struct pci_controller *hose; |
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if (tsunami_probe_read(&pchip->pctl.csr) == 0) |
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return; |
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hose = alloc_pci_controller(); |
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if (index == 0) |
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pci_isa_hose = hose; |
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hose->io_space = alloc_resource(); |
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hose->mem_space = alloc_resource(); |
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/* This is for userland consumption. For some reason, the 40-bit |
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PIO bias that we use in the kernel through KSEG didn't work for |
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the page table based user mappings. So make sure we get the |
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43-bit PIO bias. */ |
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hose->sparse_mem_base = 0; |
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hose->sparse_io_base = 0; |
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hose->dense_mem_base |
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= (TSUNAMI_MEM(index) & 0xffffffffffL) | 0x80000000000L; |
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hose->dense_io_base |
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= (TSUNAMI_IO(index) & 0xffffffffffL) | 0x80000000000L; |
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hose->config_space_base = TSUNAMI_CONF(index); |
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hose->index = index; |
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hose->io_space->start = TSUNAMI_IO(index) - TSUNAMI_IO_BIAS; |
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hose->io_space->end = hose->io_space->start + TSUNAMI_IO_SPACE - 1; |
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hose->io_space->name = pci_io_names[index]; |
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hose->io_space->flags = IORESOURCE_IO; |
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hose->mem_space->start = TSUNAMI_MEM(index) - TSUNAMI_MEM_BIAS; |
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hose->mem_space->end = hose->mem_space->start + 0xffffffff; |
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hose->mem_space->name = pci_mem_names[index]; |
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hose->mem_space->flags = IORESOURCE_MEM; |
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if (request_resource(&ioport_resource, hose->io_space) < 0) |
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printk(KERN_ERR "Failed to request IO on hose %d\n", index); |
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if (request_resource(&iomem_resource, hose->mem_space) < 0) |
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printk(KERN_ERR "Failed to request MEM on hose %d\n", index); |
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/* |
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* Save the existing PCI window translations. SRM will |
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* need them when we go to reboot. |
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*/ |
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saved_config[index].wsba[0] = pchip->wsba[0].csr; |
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saved_config[index].wsm[0] = pchip->wsm[0].csr; |
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saved_config[index].tba[0] = pchip->tba[0].csr; |
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saved_config[index].wsba[1] = pchip->wsba[1].csr; |
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saved_config[index].wsm[1] = pchip->wsm[1].csr; |
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saved_config[index].tba[1] = pchip->tba[1].csr; |
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saved_config[index].wsba[2] = pchip->wsba[2].csr; |
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saved_config[index].wsm[2] = pchip->wsm[2].csr; |
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saved_config[index].tba[2] = pchip->tba[2].csr; |
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saved_config[index].wsba[3] = pchip->wsba[3].csr; |
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saved_config[index].wsm[3] = pchip->wsm[3].csr; |
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saved_config[index].tba[3] = pchip->tba[3].csr; |
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/* |
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* Set up the PCI to main memory translation windows. |
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* |
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* Note: Window 3 is scatter-gather only |
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* |
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* Window 0 is scatter-gather 8MB at 8MB (for isa) |
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* Window 1 is scatter-gather (up to) 1GB at 1GB |
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* Window 2 is direct access 2GB at 2GB |
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* |
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* NOTE: we need the align_entry settings for Acer devices on ES40, |
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* specifically floppy and IDE when memory is larger than 2GB. |
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*/ |
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hose->sg_isa = iommu_arena_new(hose, 0x00800000, 0x00800000, |
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SMP_CACHE_BYTES); |
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/* Initially set for 4 PTEs, but will be overridden to 64K for ISA. */ |
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hose->sg_isa->align_entry = 4; |
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hose->sg_pci = iommu_arena_new(hose, 0x40000000, |
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size_for_memory(0x40000000), |
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SMP_CACHE_BYTES); |
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hose->sg_pci->align_entry = 4; /* Tsunami caches 4 PTEs at a time */ |
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__direct_map_base = 0x80000000; |
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__direct_map_size = 0x80000000; |
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pchip->wsba[0].csr = hose->sg_isa->dma_base | 3; |
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pchip->wsm[0].csr = (hose->sg_isa->size - 1) & 0xfff00000; |
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pchip->tba[0].csr = virt_to_phys(hose->sg_isa->ptes); |
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pchip->wsba[1].csr = hose->sg_pci->dma_base | 3; |
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pchip->wsm[1].csr = (hose->sg_pci->size - 1) & 0xfff00000; |
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pchip->tba[1].csr = virt_to_phys(hose->sg_pci->ptes); |
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pchip->wsba[2].csr = 0x80000000 | 1; |
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pchip->wsm[2].csr = (0x80000000 - 1) & 0xfff00000; |
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pchip->tba[2].csr = 0; |
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pchip->wsba[3].csr = 0; |
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/* Enable the Monster Window to make DAC pci64 possible. */ |
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pchip->pctl.csr |= pctl_m_mwin; |
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tsunami_pci_tbi(hose, 0, -1); |
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} |
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void __iomem * |
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tsunami_ioportmap(unsigned long addr) |
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{ |
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FIXUP_IOADDR_VGA(addr); |
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return (void __iomem *)(addr + TSUNAMI_IO_BIAS); |
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} |
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void __iomem * |
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tsunami_ioremap(unsigned long addr, unsigned long size) |
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{ |
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FIXUP_MEMADDR_VGA(addr); |
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return (void __iomem *)(addr + TSUNAMI_MEM_BIAS); |
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} |
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#ifndef CONFIG_ALPHA_GENERIC |
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EXPORT_SYMBOL(tsunami_ioportmap); |
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EXPORT_SYMBOL(tsunami_ioremap); |
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#endif |
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void __init |
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tsunami_init_arch(void) |
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{ |
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#ifdef NXM_MACHINE_CHECKS_ON_TSUNAMI |
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unsigned long tmp; |
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/* Ho hum.. init_arch is called before init_IRQ, but we need to be |
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able to handle machine checks. So install the handler now. */ |
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wrent(entInt, 0); |
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/* NXMs just don't matter to Tsunami--unless they make it |
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choke completely. */ |
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tmp = (unsigned long)(TSUNAMI_cchip - 1); |
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printk("%s: probing bogus address: 0x%016lx\n", __func__, bogus_addr); |
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printk("\tprobe %s\n", |
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tsunami_probe_write((unsigned long *)bogus_addr) |
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? "succeeded" : "failed"); |
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#endif /* NXM_MACHINE_CHECKS_ON_TSUNAMI */ |
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#if 0 |
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printk("%s: CChip registers:\n", __func__); |
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printk("%s: CSR_CSC 0x%lx\n", __func__, TSUNAMI_cchip->csc.csr); |
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printk("%s: CSR_MTR 0x%lx\n", __func__, TSUNAMI_cchip.mtr.csr); |
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printk("%s: CSR_MISC 0x%lx\n", __func__, TSUNAMI_cchip->misc.csr); |
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printk("%s: CSR_DIM0 0x%lx\n", __func__, TSUNAMI_cchip->dim0.csr); |
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printk("%s: CSR_DIM1 0x%lx\n", __func__, TSUNAMI_cchip->dim1.csr); |
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printk("%s: CSR_DIR0 0x%lx\n", __func__, TSUNAMI_cchip->dir0.csr); |
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printk("%s: CSR_DIR1 0x%lx\n", __func__, TSUNAMI_cchip->dir1.csr); |
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printk("%s: CSR_DRIR 0x%lx\n", __func__, TSUNAMI_cchip->drir.csr); |
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printk("%s: DChip registers:\n"); |
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printk("%s: CSR_DSC 0x%lx\n", __func__, TSUNAMI_dchip->dsc.csr); |
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printk("%s: CSR_STR 0x%lx\n", __func__, TSUNAMI_dchip->str.csr); |
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printk("%s: CSR_DREV 0x%lx\n", __func__, TSUNAMI_dchip->drev.csr); |
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#endif |
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/* With multiple PCI busses, we play with I/O as physical addrs. */ |
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ioport_resource.end = ~0UL; |
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|
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/* Find how many hoses we have, and initialize them. TSUNAMI |
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and TYPHOON can have 2, but might only have 1 (DS10). */ |
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tsunami_init_one_pchip(TSUNAMI_pchip0, 0); |
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if (TSUNAMI_cchip->csc.csr & 1L<<14) |
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tsunami_init_one_pchip(TSUNAMI_pchip1, 1); |
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/* Check for graphic console location (if any). */ |
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find_console_vga_hose(); |
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} |
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static void |
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tsunami_kill_one_pchip(tsunami_pchip *pchip, int index) |
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{ |
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pchip->wsba[0].csr = saved_config[index].wsba[0]; |
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pchip->wsm[0].csr = saved_config[index].wsm[0]; |
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pchip->tba[0].csr = saved_config[index].tba[0]; |
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|
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pchip->wsba[1].csr = saved_config[index].wsba[1]; |
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pchip->wsm[1].csr = saved_config[index].wsm[1]; |
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pchip->tba[1].csr = saved_config[index].tba[1]; |
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|
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pchip->wsba[2].csr = saved_config[index].wsba[2]; |
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pchip->wsm[2].csr = saved_config[index].wsm[2]; |
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pchip->tba[2].csr = saved_config[index].tba[2]; |
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|
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pchip->wsba[3].csr = saved_config[index].wsba[3]; |
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pchip->wsm[3].csr = saved_config[index].wsm[3]; |
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pchip->tba[3].csr = saved_config[index].tba[3]; |
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} |
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|
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void |
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tsunami_kill_arch(int mode) |
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{ |
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tsunami_kill_one_pchip(TSUNAMI_pchip0, 0); |
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if (TSUNAMI_cchip->csc.csr & 1L<<14) |
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tsunami_kill_one_pchip(TSUNAMI_pchip1, 1); |
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} |
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|
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static inline void |
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tsunami_pci_clr_err_1(tsunami_pchip *pchip) |
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{ |
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pchip->perror.csr; |
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pchip->perror.csr = 0x040; |
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mb(); |
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pchip->perror.csr; |
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} |
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|
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static inline void |
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tsunami_pci_clr_err(void) |
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{ |
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tsunami_pci_clr_err_1(TSUNAMI_pchip0); |
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/* TSUNAMI and TYPHOON can have 2, but might only have 1 (DS10) */ |
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if (TSUNAMI_cchip->csc.csr & 1L<<14) |
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tsunami_pci_clr_err_1(TSUNAMI_pchip1); |
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} |
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void |
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tsunami_machine_check(unsigned long vector, unsigned long la_ptr) |
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{ |
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/* Clear error before any reporting. */ |
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mb(); |
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mb(); /* magic */ |
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draina(); |
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tsunami_pci_clr_err(); |
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wrmces(0x7); |
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mb(); |
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process_mcheck_info(vector, la_ptr, "TSUNAMI", |
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mcheck_expected(smp_processor_id())); |
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}
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|