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136 lines
4.1 KiB
136 lines
4.1 KiB
/* SPDX-License-Identifier: (GPL-2.0 OR Linux-OpenIB) OR BSD-2-Clause */ |
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/* Copyright (c) 2018-2019 Pensando Systems, Inc. All rights reserved. */ |
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#ifndef IONIC_REGS_H |
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#define IONIC_REGS_H |
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#include <linux/io.h> |
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/** struct ionic_intr - interrupt control register set. |
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* @coal_init: coalesce timer initial value. |
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* @mask: interrupt mask value. |
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* @credits: interrupt credit count and return. |
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* @mask_assert: interrupt mask value on assert. |
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* @coal: coalesce timer time remaining. |
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*/ |
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struct ionic_intr { |
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u32 coal_init; |
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u32 mask; |
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u32 credits; |
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u32 mask_assert; |
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u32 coal; |
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u32 rsvd[3]; |
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}; |
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#define IONIC_INTR_CTRL_REGS_MAX 2048 |
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#define IONIC_INTR_CTRL_COAL_MAX 0x3F |
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/** enum ionic_intr_mask_vals - valid values for mask and mask_assert. |
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* @IONIC_INTR_MASK_CLEAR: unmask interrupt. |
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* @IONIC_INTR_MASK_SET: mask interrupt. |
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*/ |
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enum ionic_intr_mask_vals { |
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IONIC_INTR_MASK_CLEAR = 0, |
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IONIC_INTR_MASK_SET = 1, |
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}; |
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/** enum ionic_intr_credits_bits - bitwise composition of credits values. |
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* @IONIC_INTR_CRED_COUNT: bit mask of credit count, no shift needed. |
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* @IONIC_INTR_CRED_COUNT_SIGNED: bit mask of credit count, including sign bit. |
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* @IONIC_INTR_CRED_UNMASK: unmask the interrupt. |
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* @IONIC_INTR_CRED_RESET_COALESCE: reset the coalesce timer. |
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* @IONIC_INTR_CRED_REARM: unmask the and reset the timer. |
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*/ |
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enum ionic_intr_credits_bits { |
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IONIC_INTR_CRED_COUNT = 0x7fffu, |
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IONIC_INTR_CRED_COUNT_SIGNED = 0xffffu, |
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IONIC_INTR_CRED_UNMASK = 0x10000u, |
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IONIC_INTR_CRED_RESET_COALESCE = 0x20000u, |
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IONIC_INTR_CRED_REARM = (IONIC_INTR_CRED_UNMASK | |
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IONIC_INTR_CRED_RESET_COALESCE), |
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}; |
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static inline void ionic_intr_coal_init(struct ionic_intr __iomem *intr_ctrl, |
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int intr_idx, u32 coal) |
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{ |
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iowrite32(coal, &intr_ctrl[intr_idx].coal_init); |
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} |
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static inline void ionic_intr_mask(struct ionic_intr __iomem *intr_ctrl, |
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int intr_idx, u32 mask) |
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{ |
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iowrite32(mask, &intr_ctrl[intr_idx].mask); |
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} |
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static inline void ionic_intr_credits(struct ionic_intr __iomem *intr_ctrl, |
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int intr_idx, u32 cred, u32 flags) |
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{ |
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if (WARN_ON_ONCE(cred > IONIC_INTR_CRED_COUNT)) { |
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cred = ioread32(&intr_ctrl[intr_idx].credits); |
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cred &= IONIC_INTR_CRED_COUNT_SIGNED; |
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} |
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iowrite32(cred | flags, &intr_ctrl[intr_idx].credits); |
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} |
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static inline void ionic_intr_clean(struct ionic_intr __iomem *intr_ctrl, |
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int intr_idx) |
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{ |
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u32 cred; |
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cred = ioread32(&intr_ctrl[intr_idx].credits); |
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cred &= IONIC_INTR_CRED_COUNT_SIGNED; |
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cred |= IONIC_INTR_CRED_RESET_COALESCE; |
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iowrite32(cred, &intr_ctrl[intr_idx].credits); |
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} |
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static inline void ionic_intr_mask_assert(struct ionic_intr __iomem *intr_ctrl, |
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int intr_idx, u32 mask) |
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{ |
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iowrite32(mask, &intr_ctrl[intr_idx].mask_assert); |
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} |
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/** enum ionic_dbell_bits - bitwise composition of dbell values. |
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* |
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* @IONIC_DBELL_QID_MASK: unshifted mask of valid queue id bits. |
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* @IONIC_DBELL_QID_SHIFT: queue id shift amount in dbell value. |
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* @IONIC_DBELL_QID: macro to build QID component of dbell value. |
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* |
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* @IONIC_DBELL_RING_MASK: unshifted mask of valid ring bits. |
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* @IONIC_DBELL_RING_SHIFT: ring shift amount in dbell value. |
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* @IONIC_DBELL_RING: macro to build ring component of dbell value. |
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* |
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* @IONIC_DBELL_RING_0: ring zero dbell component value. |
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* @IONIC_DBELL_RING_1: ring one dbell component value. |
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* @IONIC_DBELL_RING_2: ring two dbell component value. |
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* @IONIC_DBELL_RING_3: ring three dbell component value. |
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* |
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* @IONIC_DBELL_INDEX_MASK: bit mask of valid index bits, no shift needed. |
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*/ |
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enum ionic_dbell_bits { |
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IONIC_DBELL_QID_MASK = 0xffffff, |
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IONIC_DBELL_QID_SHIFT = 24, |
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#define IONIC_DBELL_QID(n) \ |
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(((u64)(n) & IONIC_DBELL_QID_MASK) << IONIC_DBELL_QID_SHIFT) |
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IONIC_DBELL_RING_MASK = 0x7, |
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IONIC_DBELL_RING_SHIFT = 16, |
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#define IONIC_DBELL_RING(n) \ |
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(((u64)(n) & IONIC_DBELL_RING_MASK) << IONIC_DBELL_RING_SHIFT) |
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IONIC_DBELL_RING_0 = 0, |
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IONIC_DBELL_RING_1 = IONIC_DBELL_RING(1), |
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IONIC_DBELL_RING_2 = IONIC_DBELL_RING(2), |
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IONIC_DBELL_RING_3 = IONIC_DBELL_RING(3), |
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IONIC_DBELL_INDEX_MASK = 0xffff, |
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}; |
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static inline void ionic_dbell_ring(u64 __iomem *db_page, int qtype, u64 val) |
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{ |
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writeq(val, &db_page[qtype]); |
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} |
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#endif /* IONIC_REGS_H */
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