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327 lines
9.2 KiB
327 lines
9.2 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* Copyright (C) 2016 Google, Inc |
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* |
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* This device driver implements a TCG PTP FIFO interface over SPI for chips |
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* with Cr50 firmware. |
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* It is based on tpm_tis_spi driver by Peter Huewe and Christophe Ricard. |
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*/ |
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#include <linux/completion.h> |
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#include <linux/interrupt.h> |
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#include <linux/module.h> |
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#include <linux/of.h> |
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#include <linux/pm.h> |
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#include <linux/spi/spi.h> |
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#include <linux/wait.h> |
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#include "tpm_tis_core.h" |
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#include "tpm_tis_spi.h" |
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/* |
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* Cr50 timing constants: |
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* - can go to sleep not earlier than after CR50_SLEEP_DELAY_MSEC. |
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* - needs up to CR50_WAKE_START_DELAY_USEC to wake after sleep. |
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* - requires waiting for "ready" IRQ, if supported; or waiting for at least |
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* CR50_NOIRQ_ACCESS_DELAY_MSEC between transactions, if IRQ is not supported. |
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* - waits for up to CR50_FLOW_CONTROL for flow control 'ready' indication. |
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*/ |
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#define CR50_SLEEP_DELAY_MSEC 1000 |
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#define CR50_WAKE_START_DELAY_USEC 1000 |
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#define CR50_NOIRQ_ACCESS_DELAY msecs_to_jiffies(2) |
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#define CR50_READY_IRQ_TIMEOUT msecs_to_jiffies(TPM2_TIMEOUT_A) |
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#define CR50_FLOW_CONTROL msecs_to_jiffies(TPM2_TIMEOUT_A) |
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#define MAX_IRQ_CONFIRMATION_ATTEMPTS 3 |
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#define TPM_CR50_FW_VER(l) (0x0f90 | ((l) << 12)) |
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#define TPM_CR50_MAX_FW_VER_LEN 64 |
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struct cr50_spi_phy { |
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struct tpm_tis_spi_phy spi_phy; |
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struct mutex time_track_mutex; |
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unsigned long last_access; |
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unsigned long access_delay; |
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unsigned int irq_confirmation_attempt; |
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bool irq_needs_confirmation; |
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bool irq_confirmed; |
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}; |
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static inline struct cr50_spi_phy *to_cr50_spi_phy(struct tpm_tis_spi_phy *phy) |
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{ |
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return container_of(phy, struct cr50_spi_phy, spi_phy); |
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} |
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/* |
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* The cr50 interrupt handler just signals waiting threads that the |
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* interrupt was asserted. It does not do any processing triggered |
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* by interrupts but is instead used to avoid fixed delays. |
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*/ |
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static irqreturn_t cr50_spi_irq_handler(int dummy, void *dev_id) |
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{ |
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struct cr50_spi_phy *cr50_phy = dev_id; |
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cr50_phy->irq_confirmed = true; |
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complete(&cr50_phy->spi_phy.ready); |
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return IRQ_HANDLED; |
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} |
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/* |
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* Cr50 needs to have at least some delay between consecutive |
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* transactions. Make sure we wait. |
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*/ |
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static void cr50_ensure_access_delay(struct cr50_spi_phy *phy) |
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{ |
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unsigned long allowed_access = phy->last_access + phy->access_delay; |
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unsigned long time_now = jiffies; |
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struct device *dev = &phy->spi_phy.spi_device->dev; |
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/* |
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* Note: There is a small chance, if Cr50 is not accessed in a few days, |
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* that time_in_range will not provide the correct result after the wrap |
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* around for jiffies. In this case, we'll have an unneeded short delay, |
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* which is fine. |
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*/ |
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if (time_in_range_open(time_now, phy->last_access, allowed_access)) { |
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unsigned long remaining, timeout = allowed_access - time_now; |
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remaining = wait_for_completion_timeout(&phy->spi_phy.ready, |
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timeout); |
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if (!remaining && phy->irq_confirmed) |
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dev_warn(dev, "Timeout waiting for TPM ready IRQ\n"); |
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} |
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if (phy->irq_needs_confirmation) { |
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unsigned int attempt = ++phy->irq_confirmation_attempt; |
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if (phy->irq_confirmed) { |
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phy->irq_needs_confirmation = false; |
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phy->access_delay = CR50_READY_IRQ_TIMEOUT; |
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dev_info(dev, "TPM ready IRQ confirmed on attempt %u\n", |
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attempt); |
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} else if (attempt > MAX_IRQ_CONFIRMATION_ATTEMPTS) { |
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phy->irq_needs_confirmation = false; |
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dev_warn(dev, "IRQ not confirmed - will use delays\n"); |
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} |
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} |
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} |
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/* |
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* Cr50 might go to sleep if there is no SPI activity for some time and |
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* miss the first few bits/bytes on the bus. In such case, wake it up |
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* by asserting CS and give it time to start up. |
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*/ |
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static bool cr50_needs_waking(struct cr50_spi_phy *phy) |
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{ |
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/* |
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* Note: There is a small chance, if Cr50 is not accessed in a few days, |
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* that time_in_range will not provide the correct result after the wrap |
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* around for jiffies. In this case, we'll probably timeout or read |
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* incorrect value from TPM_STS and just retry the operation. |
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*/ |
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return !time_in_range_open(jiffies, phy->last_access, |
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phy->spi_phy.wake_after); |
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} |
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static void cr50_wake_if_needed(struct cr50_spi_phy *cr50_phy) |
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{ |
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struct tpm_tis_spi_phy *phy = &cr50_phy->spi_phy; |
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if (cr50_needs_waking(cr50_phy)) { |
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/* Assert CS, wait 1 msec, deassert CS */ |
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struct spi_transfer spi_cs_wake = { |
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.delay = { |
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.value = 1000, |
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.unit = SPI_DELAY_UNIT_USECS |
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} |
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}; |
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spi_sync_transfer(phy->spi_device, &spi_cs_wake, 1); |
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/* Wait for it to fully wake */ |
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usleep_range(CR50_WAKE_START_DELAY_USEC, |
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CR50_WAKE_START_DELAY_USEC * 2); |
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} |
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/* Reset the time when we need to wake Cr50 again */ |
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phy->wake_after = jiffies + msecs_to_jiffies(CR50_SLEEP_DELAY_MSEC); |
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} |
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/* |
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* Flow control: clock the bus and wait for cr50 to set LSB before |
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* sending/receiving data. TCG PTP spec allows it to happen during |
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* the last byte of header, but cr50 never does that in practice, |
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* and earlier versions had a bug when it was set too early, so don't |
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* check for it during header transfer. |
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*/ |
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static int cr50_spi_flow_control(struct tpm_tis_spi_phy *phy, |
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struct spi_transfer *spi_xfer) |
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{ |
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struct device *dev = &phy->spi_device->dev; |
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unsigned long timeout = jiffies + CR50_FLOW_CONTROL; |
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struct spi_message m; |
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int ret; |
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spi_xfer->len = 1; |
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do { |
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spi_message_init(&m); |
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spi_message_add_tail(spi_xfer, &m); |
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ret = spi_sync_locked(phy->spi_device, &m); |
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if (ret < 0) |
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return ret; |
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if (time_after(jiffies, timeout)) { |
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dev_warn(dev, "Timeout during flow control\n"); |
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return -EBUSY; |
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} |
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} while (!(phy->iobuf[0] & 0x01)); |
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return 0; |
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} |
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static int tpm_tis_spi_cr50_transfer(struct tpm_tis_data *data, u32 addr, u16 len, |
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u8 *in, const u8 *out) |
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{ |
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struct tpm_tis_spi_phy *phy = to_tpm_tis_spi_phy(data); |
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struct cr50_spi_phy *cr50_phy = to_cr50_spi_phy(phy); |
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int ret; |
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mutex_lock(&cr50_phy->time_track_mutex); |
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/* |
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* Do this outside of spi_bus_lock in case cr50 is not the |
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* only device on that spi bus. |
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*/ |
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cr50_ensure_access_delay(cr50_phy); |
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cr50_wake_if_needed(cr50_phy); |
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ret = tpm_tis_spi_transfer(data, addr, len, in, out); |
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cr50_phy->last_access = jiffies; |
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mutex_unlock(&cr50_phy->time_track_mutex); |
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return ret; |
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} |
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static int tpm_tis_spi_cr50_read_bytes(struct tpm_tis_data *data, u32 addr, |
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u16 len, u8 *result) |
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{ |
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return tpm_tis_spi_cr50_transfer(data, addr, len, result, NULL); |
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} |
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static int tpm_tis_spi_cr50_write_bytes(struct tpm_tis_data *data, u32 addr, |
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u16 len, const u8 *value) |
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{ |
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return tpm_tis_spi_cr50_transfer(data, addr, len, NULL, value); |
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} |
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static const struct tpm_tis_phy_ops tpm_spi_cr50_phy_ops = { |
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.read_bytes = tpm_tis_spi_cr50_read_bytes, |
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.write_bytes = tpm_tis_spi_cr50_write_bytes, |
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.read16 = tpm_tis_spi_read16, |
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.read32 = tpm_tis_spi_read32, |
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.write32 = tpm_tis_spi_write32, |
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}; |
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static void cr50_print_fw_version(struct tpm_tis_data *data) |
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{ |
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struct tpm_tis_spi_phy *phy = to_tpm_tis_spi_phy(data); |
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int i, len = 0; |
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char fw_ver[TPM_CR50_MAX_FW_VER_LEN + 1]; |
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char fw_ver_block[4]; |
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/* |
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* Write anything to TPM_CR50_FW_VER to start from the beginning |
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* of the version string |
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*/ |
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tpm_tis_write8(data, TPM_CR50_FW_VER(data->locality), 0); |
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/* Read the string, 4 bytes at a time, until we get '\0' */ |
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do { |
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tpm_tis_read_bytes(data, TPM_CR50_FW_VER(data->locality), 4, |
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fw_ver_block); |
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for (i = 0; i < 4 && fw_ver_block[i]; ++len, ++i) |
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fw_ver[len] = fw_ver_block[i]; |
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} while (i == 4 && len < TPM_CR50_MAX_FW_VER_LEN); |
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fw_ver[len] = '\0'; |
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dev_info(&phy->spi_device->dev, "Cr50 firmware version: %s\n", fw_ver); |
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} |
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int cr50_spi_probe(struct spi_device *spi) |
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{ |
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struct tpm_tis_spi_phy *phy; |
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struct cr50_spi_phy *cr50_phy; |
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int ret; |
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struct tpm_chip *chip; |
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cr50_phy = devm_kzalloc(&spi->dev, sizeof(*cr50_phy), GFP_KERNEL); |
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if (!cr50_phy) |
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return -ENOMEM; |
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phy = &cr50_phy->spi_phy; |
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phy->flow_control = cr50_spi_flow_control; |
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phy->wake_after = jiffies; |
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init_completion(&phy->ready); |
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cr50_phy->access_delay = CR50_NOIRQ_ACCESS_DELAY; |
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cr50_phy->last_access = jiffies; |
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mutex_init(&cr50_phy->time_track_mutex); |
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if (spi->irq > 0) { |
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ret = devm_request_irq(&spi->dev, spi->irq, |
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cr50_spi_irq_handler, |
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IRQF_TRIGGER_RISING | IRQF_ONESHOT, |
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"cr50_spi", cr50_phy); |
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if (ret < 0) { |
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if (ret == -EPROBE_DEFER) |
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return ret; |
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dev_warn(&spi->dev, "Requesting IRQ %d failed: %d\n", |
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spi->irq, ret); |
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/* |
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* This is not fatal, the driver will fall back to |
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* delays automatically, since ready will never |
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* be completed without a registered irq handler. |
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* So, just fall through. |
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*/ |
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} else { |
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/* |
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* IRQ requested, let's verify that it is actually |
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* triggered, before relying on it. |
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*/ |
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cr50_phy->irq_needs_confirmation = true; |
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} |
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} else { |
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dev_warn(&spi->dev, |
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"No IRQ - will use delays between transactions.\n"); |
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} |
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ret = tpm_tis_spi_init(spi, phy, -1, &tpm_spi_cr50_phy_ops); |
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if (ret) |
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return ret; |
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cr50_print_fw_version(&phy->priv); |
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chip = dev_get_drvdata(&spi->dev); |
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chip->flags |= TPM_CHIP_FLAG_FIRMWARE_POWER_MANAGED; |
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return 0; |
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} |
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#ifdef CONFIG_PM_SLEEP |
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int tpm_tis_spi_resume(struct device *dev) |
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{ |
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struct tpm_chip *chip = dev_get_drvdata(dev); |
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struct tpm_tis_data *data = dev_get_drvdata(&chip->dev); |
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struct tpm_tis_spi_phy *phy = to_tpm_tis_spi_phy(data); |
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/* |
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* Jiffies not increased during suspend, so we need to reset |
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* the time to wake Cr50 after resume. |
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*/ |
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phy->wake_after = jiffies; |
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return tpm_tis_resume(dev); |
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} |
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#endif
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