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401 lines
9.8 KiB
401 lines
9.8 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* Atheros AR71xx PCI host controller driver |
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* |
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* Copyright (C) 2008-2011 Gabor Juhos <[email protected]> |
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* Copyright (C) 2008 Imre Kaloz <[email protected]> |
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* |
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* Parts of this file are based on Atheros' 2.6.15 BSP |
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*/ |
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#include <linux/resource.h> |
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#include <linux/types.h> |
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#include <linux/delay.h> |
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#include <linux/bitops.h> |
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#include <linux/pci.h> |
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#include <linux/pci_regs.h> |
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#include <linux/interrupt.h> |
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#include <linux/init.h> |
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#include <linux/platform_device.h> |
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#include <asm/mach-ath79/ar71xx_regs.h> |
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#include <asm/mach-ath79/ath79.h> |
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#define AR71XX_PCI_REG_CRP_AD_CBE 0x00 |
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#define AR71XX_PCI_REG_CRP_WRDATA 0x04 |
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#define AR71XX_PCI_REG_CRP_RDDATA 0x08 |
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#define AR71XX_PCI_REG_CFG_AD 0x0c |
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#define AR71XX_PCI_REG_CFG_CBE 0x10 |
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#define AR71XX_PCI_REG_CFG_WRDATA 0x14 |
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#define AR71XX_PCI_REG_CFG_RDDATA 0x18 |
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#define AR71XX_PCI_REG_PCI_ERR 0x1c |
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#define AR71XX_PCI_REG_PCI_ERR_ADDR 0x20 |
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#define AR71XX_PCI_REG_AHB_ERR 0x24 |
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#define AR71XX_PCI_REG_AHB_ERR_ADDR 0x28 |
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#define AR71XX_PCI_CRP_CMD_WRITE 0x00010000 |
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#define AR71XX_PCI_CRP_CMD_READ 0x00000000 |
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#define AR71XX_PCI_CFG_CMD_READ 0x0000000a |
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#define AR71XX_PCI_CFG_CMD_WRITE 0x0000000b |
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#define AR71XX_PCI_INT_CORE BIT(4) |
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#define AR71XX_PCI_INT_DEV2 BIT(2) |
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#define AR71XX_PCI_INT_DEV1 BIT(1) |
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#define AR71XX_PCI_INT_DEV0 BIT(0) |
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#define AR71XX_PCI_IRQ_COUNT 5 |
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struct ar71xx_pci_controller { |
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void __iomem *cfg_base; |
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int irq; |
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int irq_base; |
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struct pci_controller pci_ctrl; |
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struct resource io_res; |
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struct resource mem_res; |
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}; |
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/* Byte lane enable bits */ |
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static const u8 ar71xx_pci_ble_table[4][4] = { |
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{0x0, 0xf, 0xf, 0xf}, |
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{0xe, 0xd, 0xb, 0x7}, |
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{0xc, 0xf, 0x3, 0xf}, |
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{0xf, 0xf, 0xf, 0xf}, |
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}; |
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static const u32 ar71xx_pci_read_mask[8] = { |
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0, 0xff, 0xffff, 0, 0xffffffff, 0, 0, 0 |
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}; |
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static inline u32 ar71xx_pci_get_ble(int where, int size, int local) |
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{ |
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u32 t; |
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t = ar71xx_pci_ble_table[size & 3][where & 3]; |
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BUG_ON(t == 0xf); |
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t <<= (local) ? 20 : 4; |
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return t; |
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} |
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static inline u32 ar71xx_pci_bus_addr(struct pci_bus *bus, unsigned int devfn, |
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int where) |
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{ |
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u32 ret; |
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if (!bus->number) { |
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/* type 0 */ |
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ret = (1 << PCI_SLOT(devfn)) | (PCI_FUNC(devfn) << 8) | |
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(where & ~3); |
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} else { |
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/* type 1 */ |
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ret = (bus->number << 16) | (PCI_SLOT(devfn) << 11) | |
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(PCI_FUNC(devfn) << 8) | (where & ~3) | 1; |
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} |
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return ret; |
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} |
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static inline struct ar71xx_pci_controller * |
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pci_bus_to_ar71xx_controller(struct pci_bus *bus) |
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{ |
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struct pci_controller *hose; |
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hose = (struct pci_controller *) bus->sysdata; |
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return container_of(hose, struct ar71xx_pci_controller, pci_ctrl); |
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} |
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static int ar71xx_pci_check_error(struct ar71xx_pci_controller *apc, int quiet) |
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{ |
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void __iomem *base = apc->cfg_base; |
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u32 pci_err; |
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u32 ahb_err; |
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pci_err = __raw_readl(base + AR71XX_PCI_REG_PCI_ERR) & 3; |
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if (pci_err) { |
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if (!quiet) { |
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u32 addr; |
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addr = __raw_readl(base + AR71XX_PCI_REG_PCI_ERR_ADDR); |
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pr_crit("ar71xx: %s bus error %d at addr 0x%x\n", |
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"PCI", pci_err, addr); |
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} |
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/* clear PCI error status */ |
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__raw_writel(pci_err, base + AR71XX_PCI_REG_PCI_ERR); |
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} |
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ahb_err = __raw_readl(base + AR71XX_PCI_REG_AHB_ERR) & 1; |
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if (ahb_err) { |
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if (!quiet) { |
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u32 addr; |
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addr = __raw_readl(base + AR71XX_PCI_REG_AHB_ERR_ADDR); |
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pr_crit("ar71xx: %s bus error %d at addr 0x%x\n", |
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"AHB", ahb_err, addr); |
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} |
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/* clear AHB error status */ |
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__raw_writel(ahb_err, base + AR71XX_PCI_REG_AHB_ERR); |
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} |
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return !!(ahb_err | pci_err); |
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} |
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static inline void ar71xx_pci_local_write(struct ar71xx_pci_controller *apc, |
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int where, int size, u32 value) |
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{ |
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void __iomem *base = apc->cfg_base; |
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u32 ad_cbe; |
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value = value << (8 * (where & 3)); |
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ad_cbe = AR71XX_PCI_CRP_CMD_WRITE | (where & ~3); |
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ad_cbe |= ar71xx_pci_get_ble(where, size, 1); |
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__raw_writel(ad_cbe, base + AR71XX_PCI_REG_CRP_AD_CBE); |
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__raw_writel(value, base + AR71XX_PCI_REG_CRP_WRDATA); |
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} |
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static inline int ar71xx_pci_set_cfgaddr(struct pci_bus *bus, |
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unsigned int devfn, |
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int where, int size, u32 cmd) |
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{ |
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struct ar71xx_pci_controller *apc = pci_bus_to_ar71xx_controller(bus); |
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void __iomem *base = apc->cfg_base; |
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u32 addr; |
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addr = ar71xx_pci_bus_addr(bus, devfn, where); |
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__raw_writel(addr, base + AR71XX_PCI_REG_CFG_AD); |
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__raw_writel(cmd | ar71xx_pci_get_ble(where, size, 0), |
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base + AR71XX_PCI_REG_CFG_CBE); |
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return ar71xx_pci_check_error(apc, 1); |
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} |
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static int ar71xx_pci_read_config(struct pci_bus *bus, unsigned int devfn, |
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int where, int size, u32 *value) |
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{ |
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struct ar71xx_pci_controller *apc = pci_bus_to_ar71xx_controller(bus); |
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void __iomem *base = apc->cfg_base; |
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u32 data; |
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int err; |
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int ret; |
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ret = PCIBIOS_SUCCESSFUL; |
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data = ~0; |
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err = ar71xx_pci_set_cfgaddr(bus, devfn, where, size, |
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AR71XX_PCI_CFG_CMD_READ); |
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if (err) |
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ret = PCIBIOS_DEVICE_NOT_FOUND; |
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else |
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data = __raw_readl(base + AR71XX_PCI_REG_CFG_RDDATA); |
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*value = (data >> (8 * (where & 3))) & ar71xx_pci_read_mask[size & 7]; |
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return ret; |
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} |
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static int ar71xx_pci_write_config(struct pci_bus *bus, unsigned int devfn, |
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int where, int size, u32 value) |
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{ |
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struct ar71xx_pci_controller *apc = pci_bus_to_ar71xx_controller(bus); |
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void __iomem *base = apc->cfg_base; |
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int err; |
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int ret; |
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value = value << (8 * (where & 3)); |
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ret = PCIBIOS_SUCCESSFUL; |
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err = ar71xx_pci_set_cfgaddr(bus, devfn, where, size, |
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AR71XX_PCI_CFG_CMD_WRITE); |
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if (err) |
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ret = PCIBIOS_DEVICE_NOT_FOUND; |
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else |
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__raw_writel(value, base + AR71XX_PCI_REG_CFG_WRDATA); |
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return ret; |
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} |
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static struct pci_ops ar71xx_pci_ops = { |
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.read = ar71xx_pci_read_config, |
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.write = ar71xx_pci_write_config, |
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}; |
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static void ar71xx_pci_irq_handler(struct irq_desc *desc) |
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{ |
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struct ar71xx_pci_controller *apc; |
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void __iomem *base = ath79_reset_base; |
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u32 pending; |
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apc = irq_desc_get_handler_data(desc); |
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pending = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_STATUS) & |
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__raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE); |
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if (pending & AR71XX_PCI_INT_DEV0) |
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generic_handle_irq(apc->irq_base + 0); |
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else if (pending & AR71XX_PCI_INT_DEV1) |
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generic_handle_irq(apc->irq_base + 1); |
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else if (pending & AR71XX_PCI_INT_DEV2) |
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generic_handle_irq(apc->irq_base + 2); |
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else if (pending & AR71XX_PCI_INT_CORE) |
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generic_handle_irq(apc->irq_base + 4); |
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else |
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spurious_interrupt(); |
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} |
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static void ar71xx_pci_irq_unmask(struct irq_data *d) |
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{ |
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struct ar71xx_pci_controller *apc; |
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unsigned int irq; |
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void __iomem *base = ath79_reset_base; |
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u32 t; |
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apc = irq_data_get_irq_chip_data(d); |
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irq = d->irq - apc->irq_base; |
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t = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE); |
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__raw_writel(t | (1 << irq), base + AR71XX_RESET_REG_PCI_INT_ENABLE); |
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/* flush write */ |
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__raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE); |
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} |
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static void ar71xx_pci_irq_mask(struct irq_data *d) |
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{ |
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struct ar71xx_pci_controller *apc; |
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unsigned int irq; |
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void __iomem *base = ath79_reset_base; |
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u32 t; |
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apc = irq_data_get_irq_chip_data(d); |
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irq = d->irq - apc->irq_base; |
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t = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE); |
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__raw_writel(t & ~(1 << irq), base + AR71XX_RESET_REG_PCI_INT_ENABLE); |
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/* flush write */ |
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__raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE); |
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} |
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static struct irq_chip ar71xx_pci_irq_chip = { |
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.name = "AR71XX PCI", |
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.irq_mask = ar71xx_pci_irq_mask, |
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.irq_unmask = ar71xx_pci_irq_unmask, |
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.irq_mask_ack = ar71xx_pci_irq_mask, |
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}; |
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static void ar71xx_pci_irq_init(struct ar71xx_pci_controller *apc) |
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{ |
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void __iomem *base = ath79_reset_base; |
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int i; |
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__raw_writel(0, base + AR71XX_RESET_REG_PCI_INT_ENABLE); |
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__raw_writel(0, base + AR71XX_RESET_REG_PCI_INT_STATUS); |
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BUILD_BUG_ON(ATH79_PCI_IRQ_COUNT < AR71XX_PCI_IRQ_COUNT); |
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apc->irq_base = ATH79_PCI_IRQ_BASE; |
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for (i = apc->irq_base; |
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i < apc->irq_base + AR71XX_PCI_IRQ_COUNT; i++) { |
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irq_set_chip_and_handler(i, &ar71xx_pci_irq_chip, |
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handle_level_irq); |
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irq_set_chip_data(i, apc); |
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} |
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irq_set_chained_handler_and_data(apc->irq, ar71xx_pci_irq_handler, |
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apc); |
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} |
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static void ar71xx_pci_reset(void) |
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{ |
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ath79_device_reset_set(AR71XX_RESET_PCI_BUS | AR71XX_RESET_PCI_CORE); |
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mdelay(100); |
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ath79_device_reset_clear(AR71XX_RESET_PCI_BUS | AR71XX_RESET_PCI_CORE); |
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mdelay(100); |
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ath79_ddr_set_pci_windows(); |
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mdelay(100); |
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} |
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static int ar71xx_pci_probe(struct platform_device *pdev) |
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{ |
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struct ar71xx_pci_controller *apc; |
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struct resource *res; |
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u32 t; |
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apc = devm_kzalloc(&pdev->dev, sizeof(struct ar71xx_pci_controller), |
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GFP_KERNEL); |
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if (!apc) |
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return -ENOMEM; |
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apc->cfg_base = devm_platform_ioremap_resource_byname(pdev, |
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"cfg_base"); |
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if (IS_ERR(apc->cfg_base)) |
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return PTR_ERR(apc->cfg_base); |
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apc->irq = platform_get_irq(pdev, 0); |
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if (apc->irq < 0) |
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return -EINVAL; |
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res = platform_get_resource_byname(pdev, IORESOURCE_IO, "io_base"); |
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if (!res) |
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return -EINVAL; |
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apc->io_res.parent = res; |
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apc->io_res.name = "PCI IO space"; |
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apc->io_res.start = res->start; |
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apc->io_res.end = res->end; |
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apc->io_res.flags = IORESOURCE_IO; |
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res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mem_base"); |
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if (!res) |
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return -EINVAL; |
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apc->mem_res.parent = res; |
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apc->mem_res.name = "PCI memory space"; |
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apc->mem_res.start = res->start; |
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apc->mem_res.end = res->end; |
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apc->mem_res.flags = IORESOURCE_MEM; |
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ar71xx_pci_reset(); |
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/* setup COMMAND register */ |
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t = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE |
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| PCI_COMMAND_PARITY | PCI_COMMAND_SERR | PCI_COMMAND_FAST_BACK; |
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ar71xx_pci_local_write(apc, PCI_COMMAND, 4, t); |
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/* clear bus errors */ |
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ar71xx_pci_check_error(apc, 1); |
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ar71xx_pci_irq_init(apc); |
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apc->pci_ctrl.pci_ops = &ar71xx_pci_ops; |
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apc->pci_ctrl.mem_resource = &apc->mem_res; |
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apc->pci_ctrl.io_resource = &apc->io_res; |
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register_pci_controller(&apc->pci_ctrl); |
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return 0; |
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} |
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static struct platform_driver ar71xx_pci_driver = { |
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.probe = ar71xx_pci_probe, |
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.driver = { |
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.name = "ar71xx-pci", |
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}, |
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}; |
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static int __init ar71xx_pci_init(void) |
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{ |
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return platform_driver_register(&ar71xx_pci_driver); |
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} |
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postcore_initcall(ar71xx_pci_init);
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