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285 lines
7.5 KiB
285 lines
7.5 KiB
/* |
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* Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights |
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* reserved. |
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* |
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* This software is available to you under a choice of one of two |
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* licenses. You may choose to be licensed under the terms of the GNU |
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* General Public License (GPL) Version 2, available from the file |
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* COPYING in the main directory of this source tree, or the NetLogic |
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* license below: |
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* |
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* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions |
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* are met: |
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* |
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* 1. Redistributions of source code must retain the above copyright |
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* notice, this list of conditions and the following disclaimer. |
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* 2. Redistributions in binary form must reproduce the above copyright |
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* notice, this list of conditions and the following disclaimer in |
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* the documentation and/or other materials provided with the |
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* distribution. |
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* |
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* THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR |
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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* ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE |
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR |
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* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, |
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE |
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* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN |
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* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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*/ |
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#include <linux/kernel.h> |
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#include <linux/delay.h> |
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#include <linux/init.h> |
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#include <linux/sched/task_stack.h> |
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#include <linux/smp.h> |
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#include <linux/irq.h> |
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#include <asm/mmu_context.h> |
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#include <asm/netlogic/interrupt.h> |
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#include <asm/netlogic/mips-extns.h> |
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#include <asm/netlogic/haldefs.h> |
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#include <asm/netlogic/common.h> |
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#if defined(CONFIG_CPU_XLP) |
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#include <asm/netlogic/xlp-hal/iomap.h> |
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#include <asm/netlogic/xlp-hal/xlp.h> |
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#include <asm/netlogic/xlp-hal/pic.h> |
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#elif defined(CONFIG_CPU_XLR) |
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#include <asm/netlogic/xlr/iomap.h> |
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#include <asm/netlogic/xlr/pic.h> |
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#include <asm/netlogic/xlr/xlr.h> |
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#else |
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#error "Unknown CPU" |
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#endif |
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void nlm_send_ipi_single(int logical_cpu, unsigned int action) |
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{ |
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unsigned int hwtid; |
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uint64_t picbase; |
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/* node id is part of hwtid, and needed for send_ipi */ |
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hwtid = cpu_logical_map(logical_cpu); |
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picbase = nlm_get_node(nlm_hwtid_to_node(hwtid))->picbase; |
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if (action & SMP_CALL_FUNCTION) |
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nlm_pic_send_ipi(picbase, hwtid, IRQ_IPI_SMP_FUNCTION, 0); |
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if (action & SMP_RESCHEDULE_YOURSELF) |
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nlm_pic_send_ipi(picbase, hwtid, IRQ_IPI_SMP_RESCHEDULE, 0); |
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} |
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void nlm_send_ipi_mask(const struct cpumask *mask, unsigned int action) |
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{ |
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int cpu; |
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for_each_cpu(cpu, mask) { |
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nlm_send_ipi_single(cpu, action); |
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} |
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} |
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/* IRQ_IPI_SMP_FUNCTION Handler */ |
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void nlm_smp_function_ipi_handler(struct irq_desc *desc) |
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{ |
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unsigned int irq = irq_desc_get_irq(desc); |
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clear_c0_eimr(irq); |
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ack_c0_eirr(irq); |
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generic_smp_call_function_interrupt(); |
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set_c0_eimr(irq); |
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} |
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/* IRQ_IPI_SMP_RESCHEDULE handler */ |
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void nlm_smp_resched_ipi_handler(struct irq_desc *desc) |
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{ |
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unsigned int irq = irq_desc_get_irq(desc); |
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clear_c0_eimr(irq); |
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ack_c0_eirr(irq); |
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scheduler_ipi(); |
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set_c0_eimr(irq); |
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} |
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/* |
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* Called before going into mips code, early cpu init |
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*/ |
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void nlm_early_init_secondary(int cpu) |
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{ |
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change_c0_config(CONF_CM_CMASK, 0x3); |
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#ifdef CONFIG_CPU_XLP |
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xlp_mmu_init(); |
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#endif |
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write_c0_ebase(nlm_current_node()->ebase); |
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} |
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/* |
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* Code to run on secondary just after probing the CPU |
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*/ |
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static void nlm_init_secondary(void) |
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{ |
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int hwtid; |
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hwtid = hard_smp_processor_id(); |
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cpu_set_core(¤t_cpu_data, hwtid / NLM_THREADS_PER_CORE); |
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current_cpu_data.package = nlm_nodeid(); |
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nlm_percpu_init(hwtid); |
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nlm_smp_irq_init(hwtid); |
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} |
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void nlm_prepare_cpus(unsigned int max_cpus) |
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{ |
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/* declare we are SMT capable */ |
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smp_num_siblings = nlm_threads_per_core; |
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} |
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void nlm_smp_finish(void) |
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{ |
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local_irq_enable(); |
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} |
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/* |
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* Boot all other cpus in the system, initialize them, and bring them into |
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* the boot function |
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*/ |
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unsigned long nlm_next_gp; |
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unsigned long nlm_next_sp; |
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static cpumask_t phys_cpu_present_mask; |
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int nlm_boot_secondary(int logical_cpu, struct task_struct *idle) |
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{ |
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uint64_t picbase; |
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int hwtid; |
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hwtid = cpu_logical_map(logical_cpu); |
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picbase = nlm_get_node(nlm_hwtid_to_node(hwtid))->picbase; |
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nlm_next_sp = (unsigned long)__KSTK_TOS(idle); |
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nlm_next_gp = (unsigned long)task_thread_info(idle); |
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/* barrier for sp/gp store above */ |
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__sync(); |
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nlm_pic_send_ipi(picbase, hwtid, 1, 1); /* NMI */ |
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return 0; |
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} |
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void __init nlm_smp_setup(void) |
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{ |
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unsigned int boot_cpu; |
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int num_cpus, i, ncore, node; |
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volatile u32 *cpu_ready = nlm_get_boot_data(BOOT_CPU_READY); |
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boot_cpu = hard_smp_processor_id(); |
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cpumask_clear(&phys_cpu_present_mask); |
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cpumask_set_cpu(boot_cpu, &phys_cpu_present_mask); |
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__cpu_number_map[boot_cpu] = 0; |
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__cpu_logical_map[0] = boot_cpu; |
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set_cpu_possible(0, true); |
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num_cpus = 1; |
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for (i = 0; i < NR_CPUS; i++) { |
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/* |
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* cpu_ready array is not set for the boot_cpu, |
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* it is only set for ASPs (see smpboot.S) |
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*/ |
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if (cpu_ready[i]) { |
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cpumask_set_cpu(i, &phys_cpu_present_mask); |
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__cpu_number_map[i] = num_cpus; |
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__cpu_logical_map[num_cpus] = i; |
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set_cpu_possible(num_cpus, true); |
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node = nlm_hwtid_to_node(i); |
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cpumask_set_cpu(num_cpus, &nlm_get_node(node)->cpumask); |
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++num_cpus; |
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} |
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} |
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pr_info("Physical CPU mask: %*pb\n", |
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cpumask_pr_args(&phys_cpu_present_mask)); |
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pr_info("Possible CPU mask: %*pb\n", |
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cpumask_pr_args(cpu_possible_mask)); |
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/* check with the cores we have woken up */ |
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for (ncore = 0, i = 0; i < NLM_NR_NODES; i++) |
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ncore += hweight32(nlm_get_node(i)->coremask); |
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pr_info("Detected (%dc%dt) %d Slave CPU(s)\n", ncore, |
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nlm_threads_per_core, num_cpus); |
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/* switch NMI handler to boot CPUs */ |
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nlm_set_nmi_handler(nlm_boot_secondary_cpus); |
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} |
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static int nlm_parse_cpumask(cpumask_t *wakeup_mask) |
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{ |
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uint32_t core0_thr_mask, core_thr_mask; |
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int threadmode, i, j; |
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core0_thr_mask = 0; |
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for (i = 0; i < NLM_THREADS_PER_CORE; i++) |
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if (cpumask_test_cpu(i, wakeup_mask)) |
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core0_thr_mask |= (1 << i); |
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switch (core0_thr_mask) { |
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case 1: |
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nlm_threads_per_core = 1; |
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threadmode = 0; |
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break; |
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case 3: |
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nlm_threads_per_core = 2; |
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threadmode = 2; |
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break; |
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case 0xf: |
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nlm_threads_per_core = 4; |
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threadmode = 3; |
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break; |
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default: |
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goto unsupp; |
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} |
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/* Verify other cores CPU masks */ |
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for (i = 0; i < NR_CPUS; i += NLM_THREADS_PER_CORE) { |
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core_thr_mask = 0; |
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for (j = 0; j < NLM_THREADS_PER_CORE; j++) |
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if (cpumask_test_cpu(i + j, wakeup_mask)) |
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core_thr_mask |= (1 << j); |
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if (core_thr_mask != 0 && core_thr_mask != core0_thr_mask) |
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goto unsupp; |
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} |
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return threadmode; |
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unsupp: |
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panic("Unsupported CPU mask %*pb", cpumask_pr_args(wakeup_mask)); |
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return 0; |
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} |
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int nlm_wakeup_secondary_cpus(void) |
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{ |
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u32 *reset_data; |
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int threadmode; |
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/* verify the mask and setup core config variables */ |
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threadmode = nlm_parse_cpumask(&nlm_cpumask); |
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/* Setup CPU init parameters */ |
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reset_data = nlm_get_boot_data(BOOT_THREAD_MODE); |
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*reset_data = threadmode; |
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#ifdef CONFIG_CPU_XLP |
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xlp_wakeup_secondary_cpus(); |
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#else |
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xlr_wakeup_secondary_cpus(); |
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#endif |
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return 0; |
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} |
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const struct plat_smp_ops nlm_smp_ops = { |
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.send_ipi_single = nlm_send_ipi_single, |
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.send_ipi_mask = nlm_send_ipi_mask, |
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.init_secondary = nlm_init_secondary, |
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.smp_finish = nlm_smp_finish, |
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.boot_secondary = nlm_boot_secondary, |
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.smp_setup = nlm_smp_setup, |
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.prepare_cpus = nlm_prepare_cpus, |
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};
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